LMH4345

LMH4345, LMH4045, LMH4075 3Gbps, HD, SD, DVB-ASI SDI Dual Serializer / Deserializer (SER/ DES) with Loopthrough and LVDS Interface ADVANCE INFORMATION September 4, 2008 LMH4345, LMH4045, LMH4075 3 Gbps, HD, SD, DVB-ASI SDI Dual Serializer / Deserializer (SER/DES) with Loopthrough and LVDS Interface General Description The Dual SER/DES 5:1 Serializer and 1:5 De-serializer provides four independent high-speed Serial Digital Interface (SDI) links, two RX and two TX links, compliant with SMPTE 259M C, SMPTE 292M or SMPTE 424M at datarates of 270 Mbps, 1.5 Gbps or 3 Gbps as applicable. The channels also will support DVB_ASI interfaces, with internal 8b10b coding/ decoding. Built-in programmable serializer and deserializer signal conditioning blocks improve signal integrity performance and allow flexible board layout. The input and output of the Dual Serdes are designed to interface easily to FPGA/ ASIC devices. Each input or output channel is supported by 5 pairs of high-speed LVDS connections to reduce FPGA pin count as well as provide better signal integrity and EMI performance. The serializer outputs have integrated cable drivers which support SMPTE 259M (270 Mb/s), SMPTE 292M, and SMPTE 424M standards with excellent output jitter performance. Each Deserializer channel has a reclocked loopthrough output which also has an integrated cable driver. When paired with a host FPGA the LMH4345 deserializers automatically detect the incoming data rate and decode the raw 5-bit data words compliant to any of the supported standards. The interface between the LMH4345 and the host FPGA consists of four 5-bit wide LVDS buses (two input and two output), an LVDS clock per channel and an SMBus interface. No external VCOs or clocks are required. The LMH4345 receivers detect the frequency from the incoming data stream, generate a clean clock and transmit both clock and data to the host FPGA. Refer to table 1 for a listing of the variants of this product offered. National Semiconductor also offers single serializers and single deserializers as a part of the FPGA-Attach SER/DES product family. The FPGA-Attach SER/DES product family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The product is packaged in a 100 pin TQFP package. Key Specifications ■ Output compliant with SMPTE 259M-C, SMPTE 292M, SMPTE 424M and DVB-ASI ■ Typical power dissipation: TBD mW (loopthrough disabled, 3G datarate) ■ Jitter Tolerance (Deserializer) 0.6UI ■ Output Jitter (Serializers) 0.1 UI Features ■ Two Independent Serializers and Two Independent ■ ■ ■ ■ ■ ■ ■ Deserializers No external VCO or clocks required Reclocked serial loopthrough with Cable Driver Integrated Cable Drivers Powerdown Mode 3.3V SMBus configuration interface Small 100 Pin TQFP package Industrial Temperature range:-40°C to +85°C Applications ■ SDI interfaces for: — — — — Video Cameras DVRs Video Switchers Video Editing Systems TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 300682 www.national.com LMH4345, LMH4045, LMH4075 General Block Diagram 30068201 www.national.com 2 LMH4345, LMH4045, LMH4075 Pin Descriptions Pin Name RXOUT[4:0]_1± RXOUT[4:0]_2± RXCLK_1± RXCLK_2± TXIN[4:0]_0± TXIN[4:0]_3± TXCLK_0± TXCLK_3± Serial Data Inputs RXIN1± RXIN2± Serial Data Outputs TXOUT_0± TXOUT_3± RXLP_1± RXLP_2± SMBus Interface SDA SCK SMB_CS I/O, LVCMOS Input, LVCMOS Input, LVCMOS SMBus Data I/O Pin SMBus Clock Input Pin SMBus Chip Select Input Pin Device is selected when High. Reset Input Pin H = normal mode L = device in RESET PLL LOCK Status Output H = unlock condition L = PLL is Locked Each Lock pin corresponds to one channel. General Purpose Input / Output Software configurable I/O pins. Configuration Input – Must tie Low Connect to GND for normal operation Serializer output, channel 0 Serializer output, channel 3 Deserializer output, channel 1 Deserializer output, channel 2 Serial Differential Output Pins Channel 0 Serial Differential Output Pins Channel 3 Differential Reclocked Loopthrough output channel 1 Differential Reclocked Loopthrough output channel 2 Input, Differential Input, Differential Serial differential input Pins Channel 1 Serial differential input Pins Channel 2 Type Output, LVDS Output, LVDS Input, LVDS Input, LVDS Description LVDS Data Output Pins Two, Five channel wide DDR interfaces. LVDS Clock Output Pins DDR Interfaces. LVDS Data Input Pins Five bit wide DDR interfaces, internal 100Ω termination. LVDS Clock Input Pins DDR Interface, Internal 100Ω termination. LVDS HOST Interface Control and Configuration Pins RESET Input, LVCMOS LOCK0, LOCK1, LOCK2, LOCK3 Output, LVCMOS GPIO[3:0] RSVD_L I/O, LVCMOS Input, LVCMOS 3 www.national.com LMH4345, LMH4045, LMH4075 Pin Name Analog Inputs RSET Type Input Description SDI Output Amplitude Control Resistor connected from this pin to ground to set the signal amplitude for all four SDI outputs. Nominally 8.06kΩ for 800mV output (SMPTE Compliant). Loop Filter Connection Loop Filter Reference LF_CP0, LF_CP1, LF_CP2, LF_CP3 LF_REF0, LF_REF1, LF_REF2, LF_REF3 Input Power Supply and Ground VDD3V3 VDDPLL VDD2V5 VDD2V5A GND Power Power Power Power Ground 3.3V Power Supply connection 3.3V PLL Power Supply connection 2.5V Power Supply connection Analog 2.5V Power Supply connection Ground connection – The DAP (large center pad) is the primary GND connection for the device and must be connected to Ground along with the GND pins. TABLE 1. Feature Table Device LMH4345 LMH4045 LMH4075 SMPTE 424M Support × SMPTE 292M Support × × SMPTE 259M Support × × × DVB-ASI Support × × × www.national.com 4 LMH4345, LMH4045, LMH4075 Physical Dimensions inches (millimeters) unless otherwise noted 100-Lead TQFP Package NS Package Number VXF100A 5 www.national.com LMH4345, LMH4045, LMH4075 3Gbps, HD, SD, DVB-ASI SDI Dual Serializer / Deserializer (SER/ DES) with Loopthrough and LVDS Interface Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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