LMH6552MA

LMH6552 1 GHz Fully Differential Amplifier April 2007 LMH6552 1 GHz Fully Differential Amplifier General Description The LMH6552 is a high performance fully differential amplifier designed to provide the exceptional signal fidelity and wide large-signal bandwidth necessary for driving 8 to 14 bit high speed data acquisition systems. Using National's proprietary differential current mode input stage architecture, the LMH6552 allows operation at gains greater than unity without sacrificing response flatness, bandwidth, harmonic distortion, or output noise performance. With external gain set resistors and integrated common mode feedback, the LMH6552 can be configured as either a differential input to differential output or single ended input to differential output gain block. The LMH6552 can be AC or DC coupled at the input which makes it suitable for a wide range of applications including communication systems and high speed oscilloscope front ends. The LMH6552 is available in an 8-pin SOIC package as well as a space saving, thermally enhanced 8-pin LLP package for higher performance. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ 1.0 GHz bandwidth @ AV = 1 800 MHz bandwidth @ AV = 4 450 MHz 0.1 dB flatness 3800 V/µs slew rate 10 ns settling time to 0.1% −90 dB THD @ 20 MHz −74 dB THD @ 70 MHz 20 ns enable/shutdown pin 5 to 12V operation Applications ■ ■ ■ ■ ■ ■ ■ Differential ADC driver Video over twisted pair Differential line driver Single end to differential converter High speed differential signaling IF/RF amplifier SAW filter buffer/driver Typical Application Single-Ended Input Differential Output 30003544 LMH™ is a trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 300035 www.national.com LMH6552 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 6) Human Body Model Machine Model Supply Voltage Common Mode Input Voltage Maximum Input Current (pins 1, 2, 7, 8) Maximum Output Current (pins 4, 5) Soldering Information 2000V 200V 13.2V ±VS 30 mA (Note 4) Infrared or Convection (20 sec) Wave Soldering (10 sec) 235°C 260°C Operating Ratings Operating Temperature Range (Note 3) Storage Temperature Range Total Supply Voltage (Note 1) −40°C to +85°C −65°C to +150°C 4.5V to 12V 150°C/W Package Thermal Resistance (θJA) (Note 5) 8-Pin SOIC ±5V Electrical Characteristics Symbol Parameter (Note 2) Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = +5V, V− = −5V, AV= 1, VCM = 0V, RF = RG = 357Ω, RL = 500Ω, for single ended in, differential out. Boldface limits apply at the temperature extremes. Conditions Min (Note 8) Typ (Note 7) 1000 930 810 590 950 820 740 590 450 3800 750 10 −92 −74 −93 −84 −87 1.1 19.5 10.3 60 VCM = 0V, VID = 0V, IBoffset = (IB− - IB+)/2 DC, VCM = 0V, VID = 0V Differential Differential CMRR > 38 dB ±3.5 2.47 80 15 0.5 ±3.8 110 18 dBc dBc nV/ pA/ dB µA µA dBc Ω pF V dBc MHz V/μs ps ns MHz MHz Max (Note 8) Units AC Performance (Differential) SSBW Small Signal −3 dB Bandwidth (Note 8) VOUT = 0.2 VPP, AV = 1 VOUT = 0.2 VPP, AV = 2 VOUT = 0.2 VPP, AV = 4 VOUT = 0.2 VPP, AV = 8 LSBW Large Signal −3 dB Bandwidth VOUT = 2 VPP, AV = 1 VOUT = 2 VPP, AV = 2 VOUT = 2 VPP, AV = 4 VOUT = 2 VPP, AV = 8 0.1 dB Bandwidth Slew Rate Rise/Fall Time, 10%-90% 0.1% Settling Time Distortion and Noise Response HD2 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800Ω VOUT = 2 VPP, f = 70 MHz, RL = 800Ω HD3 3rd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800Ω VOUT = 2 VPP, f = 70 MHz, RL = 800Ω IMD3 Two-Tone Intermodulation Input Noise Voltage Input Noise Current Noise Figure (See Figure 5) Input Characteristics IBI IBoffset CMRR RIN CIN CMVR Input Bias Current (Note 10) Input Bias Current Differential (Note 7) Common Mode Rejection Ratio (Note 7) Input Resistance Input Capacitance Input Common Mode Voltage Range Freq >70 MHz, Third Order Products, VOUT = 2 VPP Composite f ≥ 1 MHz f ≥ 1 MHz 50Ω System, AV = 9, 10 MHz VOUT = 0.2 VPP, AV = 1 4V Step, AV = 1 2V Step 2V Step www.national.com 2 LMH6552 Symbol Output Performance Parameter Conditions Min (Note 8) 14.8 ±70 Typ (Note 7) 15.4 ±80 ±141 -60 Max (Note 8) Units Output Voltage Swing (Note 7) IOUT ISC Linear Output Current (Note 7) Short Circuit Current Output Balance Error Miscellaneous Performance ZT PSRR IS Open Loop Transimpedance Power Supply Rejection Ratio Supply Current (Note 7) Enable Voltage Threshold Disable Voltage Threshold Enable/Disable time ISD Disable Shutdown Current Common Mode Small Signal Bandwidth Slew Rate VOSCM Input Offset Voltage Input Bias Current Voltage Range CMRR Input Resistance Gain Output Common Mode Control Circuit Differential Output VOUT = 0V One Output Shorted to Ground VIN = 2V Single Ended (Note 6) ΔVOUT Common Mode /ΔVOUT Differential , ΔVOD = 1V, f < 1 MHz Differential DC, ΔVS = ±1V RL = ∞ VPP mA mA dB 108 80 19 3.0 2.0 15 500 600 22.5 25 28 dBΩ dB mA V V ns μA MHz V/μs ±16.5 ±8 mV µA V dB kΩ 1.012 V/V VIN+ = VIN− = 0 VIN+ = VIN− = 0 Common Mode, VID = 0, VCM = 0 (Note 9) ±3.7 Measure VOD, VID = 0V ΔVO,CM/ΔVCM (Note 2) 0.995 400 607 1.5 −3.2 ±3.8 80 200 1.0 ±2.5V Electrical Characteristics Symbol SSBW Parameter Small Signal −3 dB Bandwidth (Note 8) Unless otherwise specified, all limits are guaranteed for TA = 25°C, V+ = +2.5V, V− = −2.5V, AV = 1, VCM = 0V, RF = RG = 357Ω, RL = 500Ω, for single ended in, differential out. Boldface limits apply at the temperature extremes. Conditions VOUT = 0.2 VPP, AV = 1 VOUT = 0.2 VPP, AV = 2 VOUT = 0.2 VPP, AV = 4 VOUT = 0.2 VPP, AV = 8 LSBW Large Signal −3 dB Bandwidth VOUT = 2 VPP, AV = 1 VOUT = 2 VPP, AV = 2 VOUT = 2 VPP, AV = 4 VOUT = 2 VPP, AV = 8 0.1 dB Bandwidth Slew Rate Rise/Fall Time, 10% to 90% 0.1% Settling Time Distortion and Noise Response HD2 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800Ω VOUT = 2 VPP, f = 70 MHz, RL = 800Ω 82 65 dBc VOUT = 0.2 VPP, AV = 1 2V Step, AV = 1 2V Step 2V Step Min (Note 8) Typ (Note 7) 800 740 660 498 690 620 589 480 300 2100 1.2 10 MHz V/μs ns ns MHz MHz Max (Note 8) Units 3 www.national.com LMH6552 Symbol HD3 Parameter 3rd Harmonic Distortion Conditions VOUT = 2 VPP, f = 20 MHz, RL = 800Ω VOUT = 2 VPP, f = 70 MHz, RL = 800Ω f ≥ 70 MHz, Third Order Products, VOUT = 2 VPP Composite f ≥ 1 MHz f ≥ 1 MHz 50Ω System, AV = 9, 10 MHz Min (Note 8) Typ (Note 7) 79 67 −77 1.1 19.5 10.2 54 Max (Note 8) Units dBc dBc IMD3 Two-Tone Intermodulation Input Noise Voltage Input Noise Current Noise Figure (See Figure 5) nV/ pA/ dB 90 18 µA μA dBc Ω pF V VPP mA mA dB Input Characteristics IBI IBoffset CMRR RIN CIN CMVR Input Bias Current (Note 10) Input Bias Current Differential (Note 7) Common-Mode Rejection Ratio (Note 7) Input Resistance Input Capacitance Input Common Mode Range Output Voltage Swing (Note 7) IOUT ISC Linear Output Current (Note 7) Short Circuit Current Output Balance Error Miscellaneous Performance ZT PSRR IS Open Loop Transimpedance Power Supply Rejection Ratio Supply Current (Note 7) Enable Voltage Threshold Disable Voltage Threshold Enable/Disable time ISD Disable Shutdown Current Common Mode Small Signal Bandwidth Slew Rate VOSCM Input Offset Voltage Input Bias Current Voltage Range CMRR Input Resistance Gain ΔVO,CM/ΔVCM 0.995 Measure VOD, VID = 0V VIN+ = VIN− = 0 VIN+ = VIN− = 0 Common Mode, VID = 0, VCM = 0 (Note 9) ±1.19 Output Common Mode Control Circuit 310 430 1.65 −2.9 ±1.25 80 200 1.0 1.012 ±15 MHz V/μs mV µA V dB kΩ V/V 15 500 600 Differential DC, ΔVS = ±1V RL = ∞ 17 3.0 2.0 107 80 20.4 24 27 dBΩ dB mA V V ns µA VCM = 0V, VID = 0V, IBoffset = (IB− - IB+ )/2 DC, VCM = 0V, VID = 0V Differential Differential CMRR > 38 dB Differential Output VOUT = 0V One Output Shorted to Ground, VIN = 2V Single Ended (Note 6) ΔVOUT Common Mode /ΔVOUT Differential , ΔVOD = 1V, f < 1 MHz 1.5-3.5 5.6 ±55 2.3 75 15 0.5 1.2-3.8 6.0 ±65 ±131 60 Output Performance www.national.com 4 LMH6552 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Applications Section for information on temperature de-rating of this device." Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX)– TA) / θJA. All numbers apply for packages soldered directly onto a PC Board. Note 4: The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Application Section for more details. Note 5: Human Body Model, applicable std. MIL-STD-883, Method 30157. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). FieldInduced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 6: Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application Information for more details. Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 8: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Note 9: Negative input current implies current flowing out of the device. Note 10: IBI is referred to a differential output offset voltage by the following relationship: VOD(offset) = IBI*2RF Connection Diagram 8-Pin SOIC 30003508 Top View Ordering Information Package 8-Pin SOIC Part Number LMH6552MA LMH6552MAX Package Marking LMH6552MA Transport Media 95/Rails 2.5k Units Tape and Reel NSC Drawing M08A 5 www.national.com LMH6552 357Ω, RL = 500Ω, AV = 1, for single ended in, differential out, unless specified). Frequency Response vs. Gain Typical Performance Characteristics V+ = +5V, V− = −5V (TA = 25°C, RF = RG = Frequency Response vs. Gain 30003547 30003534 Frequency Response vs. VOUT Frequency Response vs. VOUT 30003548 30003516 Frequency Response vs. Supply Voltage Frequency Response vs. Supply Voltage 30003514 30003515 www.national.com 6 LMH6552 Frequency Response vs. Capacitive Load Suggested ROUT vs. Capacitive Load 30003521 30003522 1 VPP Pulse Response Single Ended Input 2 VPP Pulse Response Single Ended Input 30003526 30003527 Large Signal Pulse Response Output Common Mode Pulse Response 30003525 30003524 7 www.national.com LMH6552 Distortion vs. Frequency Single Ended Input Distortion vs. Supply Voltage 30003529 30003543 Distortion vs. Supply Voltage Distortion vs. Output Common Mode Voltage 30003537 30003538 Maximum VOUT vs. IOUT Minimum VOUT vs. IOUT 30003530 30003531 www.national.com 8 LMH6552 Open Loop Transimpedance Open Loop Transimpedance 30003541 30003542 Closed Loop Output Impedance Closed Loop Output Impedance 30003517 30003518 Overdrive Recovery Overdrive Recovery 30003557 30003558 9 www.national.com LMH6552 PSRR PSRR 30003519 30003520 CMRR Balance Error 30003533 30003513 Noise Figure Noise Figure 30003545 30003546 www.national.com 10 LMH6552 Input Noise vs. Frequency Differential S-Parameter Magnitude vs. Frequency 30003549 30003555 Differential S-Parameter Phase vs. Frequency 3rd Order Intermodulation Products vs. VOUT 30003556 30003551 3rd Order Intermodulation Products vs. VOUT 30003552 11 www.national.com LMH6552 Application Information The LMH6552 is a fully differential current feedback amplifier with integrated output common mode control, designed to provide low distortion amplification to wide bandwidth differential signals. The common mode feedback circuit sets the output common mode voltage independent of the input common mode, as well as forcing the V+ and V− outputs to be equal in magnitude and opposite in phase, even when only one of the inputs is driven as in single to differential conversion. The proprietary current feedback architecture of the LMH6552 offers gain and bandwidth independence with exceptional gain flatness and noise performance, even at high values of gain, simply with the appropriate choice of RF1 and RF2. Generally RF1 is set equal to RF2, and RG1 equal to RG2, so that the gain is set by the ratio RF/RG. Matching of these resistors greatly affects CMRR, DC offset error, and output balance. A minimum of 0.1% tolerance resistors are recommended for optimal performance, and the amplifier is internally compensated to operate with optimum gain flatness with values of RF between 270Ω and 390Ω depending on package selection and PCB layout. The output common mode voltage is set by the VCM pin with a fixed gain of 1 V/V. This pin should be driven by a low impedance reference and should be bypassed to ground with a 0.1 µF ceramic capacitor. Any unwanted signal coupling into the VCM pin will be passed along to the outputs, reducing the performance of the amplifier. This pin must not be left floating. The LMH6552 can be operated on a supply range as either a single 5V supply or as a split +5V and −5V. Operation on a single 5V supply, depending on gain, is limited by the input common mode range: therefore, AC coupling may be required. For example, in a DC coupled input application on a single 5V supply, with a VCM of 1.5V, the input common voltage at a gain of 1 will be 0.75V which is outside the minimum 1.2V to 3.8V input common mode range of the amplifier. The minimum VCM for this application should be greater than 2.5V depending on output signal swing. Alternatively, AC coupling of the inputs in this example results in equal input and output common mode voltages, so a 1.5V VCM would be achievable. Split supplies will allow much less restricted AC and DC coupled operation with optimum distortion performance. The LMH6552 is equipped with an ENABLE pin to reduce power consumption when not in use. The ENABLE pin, when not driven, floats high (on). When the ENABLE pin is pulled low the amplifier is disabled and the amplifier output stage goes into a high impedance state so the feedback and gain set resistors determine the output impedance of the circuit. For this reason input to output isolation will be poor in the disabled state and the part is not recommended in multiplexed applications where outputs are all tied together. FULLY DIFFERENTIAL OPERATION The LMH6552 will perform best in a fully differential configuration. The circuit shown in Figure 1 is a typical fully differential application circuit as might be used to drive an analog to digital converter (ADC). In this circuit the closed loop gain, AV = VOUT/ VIN = RF/RG, where the feedback is symmetric. The series output resistors, RO, are optional and help keep the amplifier stable when presented with a capacitive load. Refer to the Driving Capacitive Loads section for details. 30003504 FIGURE 1. Typical Application When driven from a differential source, the LMH6552 provides low distortion, excellent balance, and common mode rejection. This is true provided the resistors RF, RG and RO are well matched and strict symmetry is observed in board layout. With an intrinsic device CMRR of 80 dB, using 0.1% resistors will give a worst case CMRR of around 60 dB for most circuits. 30003553 FIGURE 2. Differential S-Parameter Test Circuit The circuit configuration shown in Figure 2 was used to measure differential S parameters in a 50Ω environment at a gain of 1 V/V. Refer to the Differential S-Parameter vs. Frequency plots in the Typical Performance Characteristics section for measurement results. SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT OPERATION In many applications, it is required to drive a differential input ADC from a single ended source. Traditionally, transformers have been used to provide single to differential conversion, but these are inherently bandpass by nature and cannot be used for DC coupled applications. The LMH6552 provides excellent performance as a single-to-differential converter down to DC. Figure 3 shows a typical application circuit where an LMH6552 is used to produce a differential signal from a single ended source. www.national.com 12 LMH6552 30003554 FIGURE 4. Single Ended Input S-Parameter Test Circuit (50Ω System) 30003510 FIGURE 3. Single Ended Input with Differential Output When using the LMH6552 in single to differential mode, the complimentary output is forced to a phase inverted replica of the driven output by the common mode feedback circuit as opposed to being driven by its own complimentary input. Consequently, as the driven input changes, the common mode feedback action results in a varying common mode voltage at the amplifier's inputs, proportional to the driving signal. Due to the non-ideal common mode rejection of the amplifier's input stage, a small common mode signal appears at the outputs which is superimposed on the differential output signal. The ratio of the change in output common mode voltage to output differential voltage is commonly referred to as output balance error. The output balance error response of the LMH6552 over frequency is shown in the Typical Performance Characteristics section. To match the input impedance of the circuit in Figure 3 to a specified source resistance, RS, requires that RT || RIN = RS. The equations governing RIN and AV for single to differential operation are also provided in Figure 3. These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain with the proper input termination. Component values for several common gain configurations in a 50Ω environment are given in Table 1. Table 1. Gain Component Values for 50Ω System Gain 0 dB 6 dB 12 dB RF 357Ω 357Ω 357Ω RG 348Ω 169Ω 76.8Ω RT 56.2Ω 61.8Ω 76.8Ω RM 26.4Ω 27.6Ω 30.9Ω The circuit shown in Figure 4 was used to measure S parameters for a single to differential configuration. The S parameter plots in the Typical Performance Curves are taken using the recommended component values for 0 dB gain. SINGLE SUPPLY OPERATION Single supply operation is possible on supplies from 5V to 10V: however, as discussed earlier, AC input coupling is recommended for low supplies such as 5V due to input common mode limitations. An example of an AC coupled, single supply, single to differential circuit is shown in Figure 5. Note that when AC coupling, both inputs need to be AC coupled irrespective of single to differential or differential to differential configuration. For higher supply voltages DC coupling of the inputs may be possible provided that the output common mode DC level is set high enough so that the amplifier's inputs and outputs are within their specified operating ranges. 30003509 FIGURE 5. AC Coupled for Single Supply Operation 13 www.national.com LMH6552 SPLIT SUPPLY OPERATION For optimum performance, split supply operation is recommended using +5V and −5V supplies however operation is possible on split supplies as low as +2.25V and −2.25V and as high as +6V and −6V. Provided the total supply voltage does not exceed the 4.5V to 12V operating specification, non symmetric supply operation is also possible and in some cases advantageous. For example , if a 5V DC coupled operation is required for low power dissipation but the amplifier input common mode range prevents this operation, it is still possible with split supplies of (V+) and (V−). Where (V+) - (V−) = 5V and V+ and V− are selected to center the amplifier input common mode range to suit the application. OUTPUT NOISE PERFORMANCE AND MEASUREMENT Unlike differential amplifiers based on voltage feedback architectures, noise sources internal to the LMH6552 refer to the inputs largely as current sources, hence the low input referred voltage noise and relatively higher input referred current noise. The output noise is therefore more strongly coupled to the value of the feedback resistor and not to the closed loop gain, as would be the case with a voltage feedback differential amplifier. This allows operation of the LMH6552 at much higher values of gain without incurring a substantial noise performance penalty, simply by choosing a suitable feedback resistor. Figure 6 shows a circuit configuration used to measure noise figure for the LMH6552 in a 50Ω system. A RF value of 275Ω is chosen to minimize output noise while simultaneously allowing both high gain (9 V/V) and proper 50Ω input termination. Refer to the section titled Single Ended Input Operation for calculation of resistor and gain values. Noise figure values at various frequencies are shown in the plot titled Noise Figure in the Typical Performance Characteristics section. capacitor input ADCs, the input capacitance will vary based on the clock cycle, as the ADC switches between the sample and hold mode. See your particular ADC's data sheet for details. 30003505 FIGURE 7. Driving an ADC Figure 8 shows the SFDR and SNR performance vs. frequency for the LMH6552 and ADC12DL080 combination circuit with the ADC input signal level at −1 dBFS. The ADC12DL080 is a dual 12-bit ADC with maximum sampling rate of 80 MSPS. The amplifier is configured to provide a gain of 2 V/V in single to differential mode. An external band-pass filter is inserted in series between the input signal source and the amplifier to reduce harmonics and noise from the signal generator. In order to properly match the input impedance seen at the LMH6552 amplifier inputs, RM is chosen to match ZS || RT for proper input balance. 30003540 30003550 FIGURE 6. Noise Figure Circuit Configuration DRIVING ANALOG TO DIGITAL CONVERTERS Analog to digital converters present challenging load conditions. They typically have high impedance inputs with large and often variable capacitive components. As well, there are usually current spikes associated with switched capacitor or sample and hold circuits. Figure 7 shows a combination circuit of the LMH6552 driving the ADC12DL080. The two 125Ω resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In addition, the resistors, along with a 2.2 pF capacitor across the outputs (in parallel with the ADC input capacitance), form a low pass anti-aliasing filter with a pole frequency of about 60 MHz. For switched www.national.com 14 FIGURE 8. LMH6552/ADC12DL080 SFDR and SNR Performance vs. Frequency The amplifier and ADC should be located as close as possible. Both devices require that the filter components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output traces and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2). The LMH6552 is capable of driving a variety of National Semiconductor Analog to Digital Converters. This is shown in Table 2, which offers a complete list of possible signal path LMH6552 ADC+Amplifier combinations. The use of the LMH6552 to drive an ADC is determined by the application and the desired sampling process (Nyquist operation, sub-sampling or oversampling). See application note (AN-236) for more details on the sampling processes and application note (AN-1393) for details on 'Using High Speed Differential Amplifiers to Drive ADC's'. For more information regarding a particular ADC, refer to the particular ADC datasheet for details. TABLE 2. DIFFERENTIAL INPUT ADC's COMPATIBLE WITH LMH6552 DRIVER Product Number Max Sampling Rate (MSPS) 15 20 42 50 60 60 100 200 1000 1000 20 20 27 40 65 65 80 66 66 10 20 40 40 40 65 66 63 70 80 170 20 40 155 Resolution Channels DRIVING CAPACITIVE LOADS As noted previously, capacitive loads should be isolated from the amplifier output with small valued resistors. This is particularly the case when the load has a resistive component that is 500Ω or higher. A typical ADC has capacitive components of around 10 pF and the resistive component could be 1000Ω or higher. If driving a transmission line, such as 50Ω coaxial or 100Ω twisted pair, using matching resistors will be sufficient to isolate any subsequent capacitance. For other applications see the Suggested ROUT vs. Capacitive Load charts in the Typical Performance Characteristics section. BALANCED CABLE DRIVER With up to 15 VPP differential output voltage swing and 80 mA of linear drive current the LMH6552 makes an excellent cable driver as shown in Figure 9. The LMH6552 is also suitable for driving differential cables from a single ended source. ADC1173 ADC1175 ADC08351 ADC1175-50 ADC08060 ADC08L060 ADC08100 ADC08200 ADC081000 ADC08D1000 ADC10321 ADC10D020 ADC10030 ADC10040 ADC10065 ADC10DL065 ADC10080 ADC11DL066 ADC11L066 ADC12010 ADC12020 ADC12040 ADC12D040 ADC12DL040 ADC12DL065 ADC12DL066 ADC12L063 CLC5957 ADC12L080 ADC12C170 ADC14L020 ADC14L040 ADC14155 8 8 8 8 8 8 8 8 8 8 10 10 10 10 10 10 10 11 11 12 12 12 12 12 12 12 12 12 12 12 14 14 14 SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE DUAL SINGLE DUAL SINGLE DUAL SINGLE DUAL SINGLE DUAL SINGLE SINGLE SINGLE SINGLE DUAL DUAL DUAL DUAL SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE 30003502 FIGURE 9. Fully Differential Cable Driver POWER SUPPLY BYPASSING The LMH6552 requires supply bypassing capacitors as shown in Figure 10 and Figure 11. The 0.01 µF and 0.1 µF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply pins. These capacitors should be star routed with a dedicated ground return plane or trace for best harmonic distortion performance. A small capacitor, ~0.01 µF, placed across the supply rails, and as close to the chip's supply pins as possible, can further improve HD2 performance. Thin traces or small vias will reduce the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM and ENABLE pins to ground. These inputs are high impedance and can provide a coupling path into the amplifier for external noise sources, possibly resulting in loss of dynamic range, degraded CMRR, degraded balance and higher distortion. 15 www.national.com LMH6552 The maximum power that the LMH6552 package can dissipate at a given temperature can be derived with the following equation: PMAX = (150° – TAMB)/ θJA, where TAMB = Ambient temperature (°C) and θJA = Thermal resistance, from junction to ambient, for a given package (°C/W). For the SOIC package θJA is 150°C/W. NOTE: If VCM is not 0V then there will be quiescent current flowing in the feedback network. This current should be included in the thermal calculations and added into the quiescent power dissipation of the amplifier. ESD PROTECTION The LMH6552 is protected against electrostatic discharge (ESD) on all pins. The LMH6552 will survive 2000V Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no affect on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6552 is driven by a large signal while the device is powered down the ESD diodes will conduct . The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to conserve power and still prevent unexpected operation. BOARD LAYOUT The LMH6552 is a very high performance amplifier. In order to get maximum benefit from the differential circuit architecture board layout and component selection is very critical. The circuit board should have a low inductance ground plane and well bypassed broad supply lines. External components should be leadless surface mount types. The feedback network and output matching resistors should be composed of short traces and precision resistors (0.1%). The output matching resistors should be placed within 3 or 4 mm of the amplifier as should the supply bypass capacitors. Refer to the section titled "Power Supply Bypassing" for recommendations on bypass circuit layout. Evaluation boards are available free of charge through the product folder on National’s web site. By design, the LMH6552 is relatively insensitive to parasitic capacitance at its inputs. Nonetheless, ground and power plane metal should be removed from beneath the amplifier and from beneath RF and RG for best performance at high frequency. With any differential signal path, symmetry is very important. Even small amounts of asymmetry can contribute to distortion and balance errors. EVALUATION BOARD National Semiconductor suggests the following evaluation boards to be used with the LMH6552: Device LMH6552MA Package SOIC Evaluation Board Ordering ID LMH730154 30003501 FIGURE 10. Split Supply Bypassing Capacitors 30003512 FIGURE 11. Single Supply Bypassing Capacitors POWER DISSIPATION The LMH6552 is optimized for maximum speed and performance in the small form factor of the standard SOIC package, and is essentially a dual channel amplifier. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation. Follow these steps to determine the maximum power dissipation for the LMH6552: 1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS), where VS = V+ - V−. (Be sure to include any current through the feedback network if VOCM is not mid rail.) 2. Calculate the RMS power dissipated in each of the output stages: PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms ((VS − V−OUT) * I−OUT) , where VOUT and IOUT are the voltage and the current measured at the output pins of the differential amplifier as if they were single ended amplifiers and VS is the total supply voltage. 3. Calculate the total RMS power: PT = PAMP + PD. These evaluation boards can be shipped when a device sample request is placed with National Semiconductor. www.national.com 16 LMH6552 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 17 www.national.com LMH6552 1 GHz Fully Differential Amplifier Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS. 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