LMH6553MRE

LMH6553 900 MHz Fully Differential Amplifier With Output Limiting Clamp November 17, 2008 LMH6553 900 MHz Fully Differential Amplifier With Output Limiting Clamp General Description The LMH6553 is a 900 MHz differential amplifier with an integrated adjustable output limiting clamp. The clamp increases system performance and provides transient over-voltage protection to following stages. The internal clamp feature of the LMH6553 reduces or eliminates the need for external discrete overload protection networks. When used to drive ADCs, the amplifier's output clamp allows low voltage ADC inputs to be protected from being overdriven and damaged by large input signals appearing at the system input. Fast overdrive recovery of 600 ps ensures the amplifier output rapidly recovers from a clamping event and quickly resumes to follow the input signal. The LMH6553 delivers exceptional bandwidth, distortion, and noise performance ideal for driving ADCs up to 14-bits. The LMH6553 could also be used for automotive, communication, medical, test and measurement, video, and LIDAR applications. With external gain set resistors and integrated common mode feedback, the LMH6553 can be configured as either a differential input to differential output or single ended input to differential output gain block. The LMH6553 can be AC or DC coupled at the input which makes it suitable for a wide range of applications including communication systems and high speed oscilloscope front ends. The LMH6553 is available in 8-pin PSOP and 8-pin LLP packages, and is part of our LMH® high speed amplifier family. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ 900 MHz −3 dB small signal bandwidth @ AV = 1 670 MHz −3 dB large signal bandwidth @ AV = 1 −79 dB THD @ 20 MHz −92 dB IMD3 @ fc = 20 MHz 10 ns settling time to 0.1% 600 ps clamp overdrive recovery time 40 mV clamp accuracy with 100% Overdrive −0.1 mV/°C clamp temperature drift 4.5 to 12 supply voltage operation Applications ■ ■ ■ ■ ■ ■ ■ ■ ■ Differential ADC driver Video over twisted pair Differential line driver Single end to differential converter High speed differential signaling IF/RF amplifier SAW filter buffer/driver CCD Output Limiting Amplifier Automotive Safety Applications Typical Application Single-Ended Input Differential Output ADC Driver 30043769 LMH® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 300437 www.national.com LMH6553 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 5) Human Body Model Machine Model Supply Voltage Common Mode Input Voltage Maximum Input Current (pins 1, 2, 7, 8) Maximum Output Current (pins 4, 5) Maximum Junction Temperature 4000V 350V 13.2V ±VS 30 mA (Note 4) 150°C (Note 2) Soldering Information Infrared or Convection (20 sec) Wave Soldering (10 sec) 235°C 260°C Operating Ratings Operating Temperature Range (Note 3) Storage Temperature Range Total Supply Voltage (Note 1) −40°C to +125°C −65°C to +150°C 4.5V to 12V 59°C/W 58°C/W Package Thermal Resistance (θJA) 8-Pin PSOP 8-Pin LLP Unless otherwise specified, all limits are guaranteed for TA = 25°C, VS = ±5V, AV = 1, VCM = 0V, VCLAMP = 3V, RF = RG = 275Ω, RL = 200Ω, for single-ended in, differential out. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min Typ Max (Note 8) (Note 7) (Note 8) 900 720 680 630 350 670 540 530 490 350 50 525 2300 690 10 6 −79 −78 −90 −71 −92 −76 1.2 13.6 10.3 dBc dBc dBc MHz MHz V/μs ps ns ns MHz MHz Units VS = ±5V Electrical Characteristics AC Performance (Differential) SSBW Small Signal −3 dB Bandwidth (Note 8) VOUT = 0.2 VPP, AV = 1, RL = 1 kΩ VOUT = 0.2 VPP, AV = 1 VOUT = 0.2 VPP, AV = 2 VOUT = 0.2 VPP, AV = 4 VOUT = 0.2 VPP, AV = 8, (RF = 400Ω, RG = 50Ω) LSBW Large Signal −3 dB Bandwidth VOUT = 2 VPP, AV = 1, RL = 1 kΩ VOUT = 2 VPP, AV = 1 VOUT = 2 VPP, AV = 2 VOUT = 2 VPP, AV = 4 VOUT = 2 VPP, AV = 8, (RF = 400Ω, RG = 50Ω) 0.1 dB Bandwidth 0.5 dB Bandwidth Slew Rate Rise/Fall Time, 10%-90% 0.1% Settling Time 1.0% Settling Time Distortion and Noise Response HD2 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800Ω VOUT = 2 VPP, f = 70 MHz, RL = 800Ω HD3 3rd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800Ω VOUT = 2 VPP, f = 70 MHz, RL = 800Ω IMD3 3rd-Order Two-Tone Intermodulation fc = 20 MHz, , VOUT = 2 VPP Composite, RL = 200Ω fc = 150 MHz, , VOUT = 2 VPP Composite, RL = 200Ω Input Noise Voltage Input Noise Current Noise Figure (See Figure 5) f = 100 kHz f = 100 kHz 50Ω System, AV = 9, 10 MHz nV/ pA/ dB VOUT = 0.2 VPP, AV = 1 VOUT = 0.2 VPP, AV = 1 4V Step, AV = 1 2V Step 2V Step 2V Step www.national.com 2 LMH6553 Symbol Parameter Conditions Min Typ Max (Note 8) (Note 7) (Note 8) −95 50 2.5 82 15 0.5 ±3.3 ±3.6 95 18 Units Input Characteristics IBI IBoffset CMRR RIN CIN CMVR Input Bias Current (Note 11) Input Bias Current Differential (Note 7) Common Mode Rejection Ratio (Note 7) Input Resistance Input Capacitance Input Common Mode Voltage Range Output Voltage Level (Note 7) IOUT ISC Linear Output Current (Note 7) Short Circuit Current VCM = 0V, VID = 0V, IBoffset = (IB− - IB+)/2 DC, VCM = 0V, VID = 0V Differential Differential CMRR > 38 dB µA µA dBc Ω pF V −18 Output Performance Single-Ended Output VOUT = 0V One Output Shorted to Ground VIN = 2V Single-Ended (Note 6) Continuous Operation (Note 11) (Note 14) VCLAMP Floating VCLAMP = 2V, VCM = 1.5V, VO = 2V, 100% Overdrive VCLAMP = 2V, VCM = 1.5V, VO = 1V, 100% Overdrive VIN = 0V, VCLAMP(MIN) = −3.1 V VIN = 0V, VCLAMP(MAX) = +4.5V Clamp Pin Bias Drift Diff Amp Input Bias Shift Clamp Pin Input Impedance Clamp Pin Feedthrough Clamp Bandwidth Clamp Slew Rate Clamp Overshoot Clamp Overshoot Clamp Overshoot Width Clamp Overdrive Recovery Time Linearity Guardband (Note 12) Output Common Mode Control Circuit Common Mode Small Signal Bandwidth Slew Rate VOSCM Output Common Mode Error VIN+ = VIN− = 0 VIN+ = VIN− = 0 Common Mode, VIN = Float, VCM = 0 −25 220 340 1 25 MHz V/μs mV f = 10 MHz 0.5VDC + 40 mVPP, SE VIN = 2V 100% Overdrive VIN = 2V Step, AV = 2 V/V, VCLAMP = 0.5V, VCM = 0V, 100% Overdrive VIN = 2V Step, AV = 2 V/V, VCLAMP = 2V, VCM = 1.5V, 100% Overdrive (Note 13) VIN = 2V Step, AV = 2 V/V, VCLAMP = 0.5V, VCM = 0V, 50% Output Crossing f = 75 MHz, VOD = 2 VPP, RL = 800, SFDR Down 3 dB Linear to Clamped Operation 0.92 −53 −30 1.0 −40 −8 −0.1 −200 −175 150 0.3 60 30 1 −60 140 64 125 250 650 600 22 175 VCM −3.7 ±100 ±3.78 ±120 ±150 +3.7 V mA mA Clamp Performance VCLAMP VCLAMP Voltage Range VCLAMP Peak Voltage Default VCLAMP Voltage Upper Clamp Level Accuracy Lower Clamp Level Accuracy Clamp Accuracy Temperature Drift Clamp Pin Bias Current VCM + 2.0 VCM + 3.0 1.08 +53 +30 mV V V mV/°C µA µA/°C µA KΩ/pF dB MHz V/µs mV mV ps ps mV 3 www.national.com LMH6553 Symbol Parameter Input Bias Current Conditions VCM(TYPICAL) = 0, (Note 9) VCM(MIN) = −3.2 V, (Note 9) VCM(MAX) = +3.2V, (Note 9) Min Typ Max (Note 8) (Note 7) (Note 8) −8 −9 ±3.14 −3.5 −4.5 −2.5 ±3.18 80 200 0.995 1.00 112 87 25 29.1 33 37 1.008 2 1 Units µA V dB kΩ V/V dBΩ dB mA Voltage Range CMRR Input Resistance Gain Miscellaneous Performance ZT PSRR IS Open Loop Transimpedance Power Supply Rejection Ratio Supply Current Differential DC, ΔVS = ±1V RL = ∞ ΔVO,CM/ΔVCM Measure VOD, VID = 0V Unless otherwise specified, all limits are guaranteed for TA = 25°C, VS = ±2.5V, AV = 1, VCM = 0V, VCLAMP = 2V, RF = RG = 275Ω, RL = 200Ω, for single-ended in, differential out. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min Typ Max (Note 8) (Note 7) (Note 8) 875 630 580 540 315 640 485 435 420 405 60 236 1350 860 10 6 −80 −72 −78 −66 −87 −68 1.1 13.6 dBc dBc dBc MHz MHz V/μs ps ns ns MHz MHz Units VS = ±2.5V Electrical Characteristics (Note 2) AC Performance (Differential) SSBW Small Signal −3 dB Bandwidth (Note 8) VOUT = 0.2 VPP, AV = 1, RL = 1 kΩ VOUT = 0.2 VPP, AV = 1 VOUT = 0.2 VPP, AV = 2 VOUT = 0.2 VPP, AV = 4 VOUT = 0.2 VPP, AV = 8 , (RF = 400Ω, RG = 50Ω) LSBW Large Signal −3 dB Bandwidth VOUT = 2 VPP, AV = 1, RL = 1 kΩ VOUT = 2 VPP, AV = 1 VOUT = 2 VPP, AV = 2 VOUT = 2 VPP, AV = 4 VOUT = 2 VPP, AV = 8, (RF = 400Ω, RG = 50Ω) 0.1 dB Bandwidth 0.5 dB Bandwidth Slew Rate Rise/Fall Time, 10%-90% 0.1% Settling Time 1.0% Settling Time Distortion and Noise Response HD2 2nd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800Ω VOUT = 2 VPP, f = 70 MHz, RL = 800Ω HD3 3rd Harmonic Distortion VOUT = 2 VPP, f = 20 MHz, RL = 800Ω VOUT = 2 VPP, f = 70 MHz, RL = 800Ω IMD3 3rd-Order Two-Tone Intermodulation fc = 20 MHz, VOUT = 2 VPP Composite, RL = 200Ω fc = 150 MHz, VOUT = 2 VPP Composite, RL = 200Ω Input Noise Voltage Input Noise Current f = 100 kHz f = 100 kHz nV/ pA/ VOUT = 0.2 VPP, AV = 1 VOUT = 0.2 VPP, AV = 1 2V Step, AV = 1 2V Step 2V Step 2V Step www.national.com 4 LMH6553 Symbol Parameter Noise Figure (See Figure 5) Conditions 50Ω System, AV = 9, 10 MHz Min Typ Max (Note 8) (Note 7) (Note 8) 10.3 −90 45 2 80 15 0.5 ±1.0 ±1.2 90 24 Units dB µA µA dBc Ω pF V Input Characteristics IBI IBoffset CMRR RIN CIN CMVR Input Bias Current (Note 11) Input Bias Current Differential (Note 7) Common Mode Rejection Ratio (Note 7) Input Resistance Input Capacitance Input Common Mode Voltage Range Output Voltage Swing (Note 7) IOUT ISC Linear Output Current (Note 7) Short Circuit Current VCM = 0V, VID = 0V, IBoffset = (IB− - IB+)/2 DC, VCM = 0V, VID = 0V Differential Differential CMRR > 38 dB −24 Output Performance Differential Output VOUT = 0V One Output Shorted to Ground VIN = 2V Single-Ended (Note 6) Continuous Operation (Note 11) (Note 14) VCLAMP Floating VIN = 0V, VCLAMP = +0.5V, VCM = 0, VO = +0.5V, 100% Overdrive VIN = 0V, VCLAMP = +0.5V, VCM = 0, VO = −0.5V, 100% Overdrive VIN = 0V, VCLAMP = 1V, VCM = 0 Linear to Clamped Operation 0.42 −39 −18 0.48 −30 6 −0.1 23.5 0.3 50 30 1 f = 10 MHz 0.5VDC + 40 mVPP, SE VIN = 2V 100% Overdrive VIN = 1V Step, AV = 2 V/V, VCLAMP = 0.5V, VCM= 0V, 100% Overdrive VIN = 1V Step, AV= 2 V/V, VCLAMP = 1V, VCM = 0.5V, 100% Overdrive (Note 13) VIN = 2V Step, AV = 2 V/V, VCLAMP = 0.5V, VCM = 0V, 50% Output Crossing f = 75 MHz, VOD = 2 VPP, RL = 800, SFDR Down 3 dB VIN+ = VIN− = 0 VIN+ = VIN− = 0 Common Mode, VIN = float, VCM = 0 −20 −60 125 52 105 105 650 600 40 VCM 5.32 ±75 5.47 ±95 ±140 VPP mA mA Clamp Performance VCLAMP VCLAMP Voltage Range VCLAMP Peak Voltage Default VCLAMP Voltage Upper Clamp Level Accuracy Lower Clamp Level Accuracy Clamp Accuracy Temperature Drift Clamp Pin Bias Current Clamp Pin Bias Drift Diff Amp Input Bias Shift Clamp Pin Input Impedance Clamp Pin Feedthrough Clamp Bandwidth Clamp Slew Rate Clamp Overshoot Clamp Overshoot Clamp Overshoot Width Clamp Overdrive Recovery Time Linearity Guardband (Note 12) Output Common Mode Control Circuit Common Mode Small Signal Bandwidth Slew Rate VOSCM Output Common Mode Error 130 186 2 20 MHz V/μs mV VCM + 2.0 VCM + 3.0 0.54 +39 +18 mV V V mV/°C µA µA/°C µA kΩ/pF dB MHz V/µs mV mV ps ps mV 5 www.national.com LMH6553 Symbol Parameter Input Bias Current Voltage Range CMRR Input Resistance Gain ΔVO,CM/ΔVCM Differential DC, ΔVS = ±1V RL = ∞ Conditions VCM = 0, (Note 9) Min Typ Max (Note 8) (Note 7) (Note 8) −3.5 ±0.75 ±0.81 84 200 0.995 1.00 105 85 23 26.5 30 34 1.008 Units µA V dB kΩ V/V dBΩ dB mA Measure VOD, VID = 0V Miscellaneous Performance ZT PSRR IS Open Loop Transimpedance Power Supply Rejection Ratio Supply Current Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Applications Section for information on temperature de-rating of this device." Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX)– TA) / θJA. All numbers apply for packages soldered directly onto a PC Board. Note 4: The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Application Section for more details. Note 5: Human Body Model, applicable std. MIL-STD-883, Method 30157. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). FieldInduced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 6: Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application Information for more details. Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 8: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Note 9: Negative current implies current flowing out of the device. Note 10: IBI is referred to a differential output offset voltage by the following relationship: VOD(offset) = IBI*2RF Note 11: Exceeding limits could result in excessive device current. Note 12: Linearity Guardband is defined for an output sinusoid (f = 75 MHz, VOD = 2 VPP). It is the difference between the VCLAMP level and the peak output voltage where the SFDR is decreased by 3 dB. Note 13: Clamp Overshoot Width is the duration of overshoot in a 100% overdrive condition. Note 14: This parameter is guaranteed by design and/or characterization and is not tested in production. The condition of VCLAMP = 3V is not intended for continuous operation; continuous operation with VCLAMP = 3V may incur permanent damage to the device. www.national.com 6 LMH6553 Connection Diagrams 8-Pin PSOP 30043708 Top View 8-Pin LLP 30043771 Top View Ordering Information Package 8-Pin PSOP Part Number LMH6553MR LMH6553MRE LMH6553MRX LMH6553SD 8-Pin LLP LMH6553SDE LMH6553SDX 6553 LMH6553MR Package Marking Transport Media 95 Units/Rails 250 Units Tape and Reel 2.5k Units Tape and Reel 1k Units Tape and Reel 250 Units Tape and Reel 4.5k Units Tape and Reel SDA08C MRA08A NSC Drawing 7 www.national.com LMH6553 for single ended in, differential out, unless specified). Frequency Response vs. Gain Typical Performance Characteristics VS = ±5V (TA = 25°C, RF = RG = 275Ω, RL = 200Ω, AV = 1, Frequency Response vs. Gain 30043747 30043734 Frequency Response vs. VOUT Frequency Response vs. VOUT 30043748 30043716 Frequency Response vs. Supply Voltage (RL = 200Ω) Frequency Response vs. Supply Voltage (RL = 1 kΩ) 30043762 30043763 www.national.com 8 LMH6553 Frequency Response vs. Capacitive Load Suggested RO vs. Capacitive Load 30043721 30043722 Frequency Response vs. Resistive Load Frequency Response vs. Resistive Load 30043759 30043760 Frequency Response vs. RF 1 VPP Pulse Response Single-Ended Input 30043726 30043761 9 www.national.com LMH6553 2 VPP Pulse Response Single-Ended Input 4 VPP Pulse Response Single-Ended Input 30043727 30043725 Pulse Response with 0% and 100% Overdrive Pulse Response with 0% and 100% Overdrive 30043774 30043775 Overdrive Recovery with VS = ±5V Overdrive Recovery with VS = ±2.5V 30043757 30043758 www.national.com 10 LMH6553 Output Common Mode Pulse Response Distortion vs. Frequency Single-Ended Input (RL=800Ω) 30043724 30043729 Distortion vs. Supply Voltage (fc=20Mhz, RL=800Ω) Distortion vs. Supply Voltage (fc=75Mhz, RL=800Ω) 30043743 30043737 Distortion vs. VCM (fc=20Mhz, RL=800Ω) Distortion vs. VCM (fc=75Mhz, RL=800Ω) 30043738 30043767 11 www.national.com LMH6553 Distortion vs. Frequency Single-Ended Input (RL=200Ω) Distortion vs. Supply Voltage (fc=20Mhz, RL=200Ω) 30043781 30043782 Distortion vs. Supply Voltage (fc=75Mhz, RL=200Ω) Distortion vs. VCM (fc=20Mhz, RL=200Ω) 30043783 30043784 Distortion vs. VCM (fc=75Mhz, RL=200Ω) Maximum VOUT vs. IOUT 30043730 30043785 www.national.com 12 LMH6553 Minimum VOUT vs. IOUT Closed Loop Output Impedance 30043731 30043717 Closed Loop Output Impedance Open Loop Transimpedance 30043718 30043741 Open Loop Transimpedance PSRR 30043742 30043719 13 www.national.com LMH6553 PSRR CMRR 30043720 30043733 Balance Error Noise Figure 30043713 30043745 Noise Figure Differential S-Parameter Magnitude vs. Frequency 30043746 30043755 www.national.com 14 LMH6553 Differential S-Parameter Phase vs. Frequency 3rd Order Intermodulation Products vs. VOUT 30043756 30043751 3rd Order Intermodulation Products vs. VOUT 3rd Order Intermodulation Products vs. Center Frequency 30043752 30043777 3rd Order Intermodulation Products vs. Center Frequency 3rd Order Intermodulation Products vs. Center Frequency 30043765 30043778 15 www.national.com LMH6553 3rd Order Intermodulation Products vs. Center Frequency 3rd Order Intermodulation Products vs. VCLAMP 30043779 30043780 www.national.com 16 LMH6553 Application Information The LMH6553, a fully differential current feedback amplifier with integrated output common mode control and output limiting clamp, is designed to provide protection of following input stages. The common mode feedback circuit sets the output common mode voltage independent of the input common mode, as well as forcing the outputs to be equal in magnitude and opposite in phase, even when only one of the inputs is driven as in single ended to differential conversion. The proprietary current feedback architecture of the LMH6553 offers gain and bandwidth independence even at high values of gain, simply with the appropriate choice of RF1 and RF2. Generally RF1 is set equal to RF2, and RG1 equal to RG2, so that the gain is set by the ratio RF/RG. Matching of these resistors greatly affects CMRR, DC offset error, and output balance. Resistors with 0.1% tolerances are recommended for optimal performance, and the amplifier is internally compensated to operate with optimum gain flatness with values of RF between 250Ω and 350Ω depending on package selection, PCB layout, and load resistance. The output common mode voltage is set by the VCM pin with a fixed gain of 1 V/V. This pin should be driven by a low impedance source and should be bypassed to ground with a 0.1 µF ceramic capacitor. Any unwanted signal coupling into the VCM pin will be passed along to the outputs, reducing the performance of the amplifier. This pin must not be left floating. The LMH6553 can be operated with either a single 5V supply or split +5V and −5V supplies. Operation on a single 5V supply, depending on gain, is limited by the input common mode range; therefore, AC coupling may be required. For example, in a DC coupled input application on a single 5V supply, with a VCM of 1.5V, the input common voltage at a gain of 1 will be 0.75V which is outside the minimum 1.5V to 3.5V input common mode range of the amplifier. The minimum VCM for this application should be greater than 1.5V depending on output signal swing. Alternatively, AC coupling of the inputs in this example results in equal input and output common mode voltages, so a 1.5V input common mode would result. Split supplies allow much less restricted AC and DC coupled operation with optimum distortion performance. The LMH6553 has a VCLAMP input which allows control of the maximum amplifier output swing to prevent overdriving of following stages such as sensitive ADC inputs and also provides fast recovery from transients that would otherwise saturate the signal path. RECOMMENDED FEEDBACK RESISTOR The LMH6553 is available in both an 8-pin LLP and PSOP package. The recommended feedback resistor, RF, for the LLP package is 275Ω and 325Ω for the PSOP to give a flat frequency response with minimal peaking. FULLY DIFFERENTIAL OPERATION The LMH6553 is ideal for a fully differential configuration. The circuit shown in Figure 1 is a typical fully differential application circuit as might be used to drive an analog to digital converter (ADC). In this circuit the closed loop gain AV = VOUT/ VIN = RF/RG, where the feedback is symmetric. The series output resistors, RO, are optional and help keep the amplifier stable when presented with a capacitive load. Refer to the Driving Capacitive Loads section for details. 30043770 FIGURE 1. Typical Application When driven from a differential source, the LMH6553 provides low distortion, excellent balance, and common mode rejection. This is true provided the resistors RF, RG and RO are well matched and strict symmetry is observed in board layout. 30043753 FIGURE 2. Differential S-Parameter Test Circuit The circuit configuration shown in Figure 2 was used to measure differential S parameters in a 50Ω environment at a gain of 1 V/V. Refer to the Differential S-Parameter vs. Frequency plots in the Typical Performance Characteristics section for measurement results. SINGLE-ENDED INPUT TO DIFFERENTIAL OUTPUT OPERATION In many applications, it is required to drive a differential input ADC from a single-ended source. Traditionally, transformers have been used to provide single to differential conversion, but these are inherently bandpass by nature and cannot be used for DC coupled applications. The LMH6553 provides excellent performance as a single-to-differential converter down to DC. Figure 3 shows a typical application circuit where an LMH6553 is used to produce a differential signal from a single ended source. 17 www.national.com LMH6553 30043754 FIGURE 4. Single Ended Input S-Parameter Test Circuit (50Ω System) 30043710 FIGURE 3. Single-Ended Input with Differential Output When using the LMH6553 in single-to-differential mode, the complementary output is forced to a phase inverted replica of the driven output by the common mode feedback circuit as opposed to being driven by its own complementary input. Consequently, as the driven input changes, the common mode feedback action results in a varying common mode voltage at the amplifier's inputs, proportional to the driving signal. Due to the non-ideal common mode rejection of the amplifier's input stage, a small common mode signal appears at the outputs which is superimposed on the differential output signal. The ratio of the change in output common mode voltage to output differential voltage is commonly referred to as output balance error. The output balance error response of the LMH6553 over frequency is shown in the Typical Performance Characteristics section. To match the input impedance of the circuit in Figure 3 to a specified source resistance, RS, requires that RT || RIN = RS. The equations governing RIN and AV for single-to-differential operation are also provided in Figure 3. These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain with the proper input termination. Component values for several common gain configurations in a 50Ω environment are given in Table 1. TABLE 1. Gain Component Values for 50Ω System LLP Package Gain 0 dB 6 dB 12 dB RF 275Ω 275Ω 275Ω RG 255Ω 127Ω 54.9Ω RT 59Ω 68.1Ω 107Ω RM 26.7Ω 28.7Ω 34Ω The circuit shown in Figure 4 was used to measure S-parameters for a single-to-differential configuration. The S-parameter plots in the Typical Performance Curves are taken using the recommended component values for 0 dB gain. SINGLE SUPPLY OPERATION Single supply operation is possible on supplies from 5V to 10V; however, as discussed earlier, AC input coupling is recommended for low supplies due to input common mode limitations. An example of an AC coupled, single supply, singleto-differential circuit is shown in Figure 5. Note that when AC coupling, both inputs need to be AC coupled irrespective of single-to-differential or differential-to-differential configuration. For higher supply voltages, DC coupling of the inputs may be possible provided that the output common mode DC level is set high enough so that the amplifier's inputs and outputs are within their specified operating ranges. TABLE 2. Gain Component Values for 50Ω System PSOP Package Gain 0 dB 6 dB 12 dB RF 325Ω 325Ω 325Ω RG 316Ω 150Ω 68.1Ω RT 56.2Ω 66.5Ω 110Ω RM 26.7Ω 28.7Ω 34.8Ω 30043709 FIGURE 5. AC Coupled for Single Supply Operation www.national.com 18 LMH6553 SPLIT SUPPLY OPERATION For optimum performance, split supply operation is recommended using +5V and −5V supplies; however, operation is possible on split supplies as low as +2.25V and −2.25V and as high as +6V and −6V. Provided the total supply voltage does not exceed the 4.5V to 12V operating specification, asymmetric supply operation is also possible and in some cases advantageous. For example, if 5V DC coupled operation is required for low power dissipation but the amplifier input common mode range prevents this operation, it is still possible with split supplies of (V+) and (V−). Where (V+) - (V−) = 5V and V+ and V− are selected to set the amplifier input common mode voltage to suit the application. CLAMP OPERATION The output clamp allows control of the maximum amplifier output swing to prevent overdriving of following stages such as sensitive ADC inputs and provide fast recovery from signal transients that would otherwise saturate the signal path. Figure 6 shows the relationship between VCLAMP and the +OUT and −OUT outputs. The example circuit shown has a single ended input and is set for a gain of 2 V/V. For proper operation VCM < VCLAMP < VCM + 2.0V and the upper single ended output voltage is limited to the voltage level set at the VCLAMP input. The output common mode control loop forces the lower single ended voltage to be limited to 2*VCM - VCLAMP. The maximum clamped single ended output swing is therefore equal to 2* (VCLAMP - V CM) and the maximum differential output swing is therefore equal to 4*(VCLAMP - VCM). In the example of Figure 6 with VCLAMP set to 2V and VCM set to 1.5V, the maximum single ended output is therefore 1 VPP centered at 1.5V and the maximum differential output is 2 VPP. This is shown for the case of a 2 VPP input sine wave which for a gain of 2 V/V in unclamped operation would provide single ended outputs at +OUT and -OUT of 2 VPP but is shown being clamp limited to 1 VPP. CLAMP PERFORMANCE Key clamp performance specifications are listed in the electrical characteristics section. Figure 7 illustrates the clamp overdrive recovery time which is defined as the difference in input to output propagation delay due to a step change at the input for a clamped output versus a normal linear unclamped, non-saturated output. 30043773 FIGURE 7. Clamp Overdrive Recovery Time MAXIMUM OUTPUT LEVEL The maximum unclamped output swing in normal operation is 4VPP single ended or 8 VPP differential due to the requirement that VCLAMP < VCM + 2.0V. For split supply operation of +5V and −5V, the maximum output voltage is limited by the output stage's ability to swing close to either supply (VOUT < ±3.7V). As shown in Figure 8, if VCLAMP is set > 3.7V, the amplifier output will saturate at the positive supply before the clamp can operate and similarly if 2*VCM - VCLAMP < −3.7V, the amplifier output will saturate at the negative supply. 30043772 FIGURE 6. Clamp Operation 30043776 FIGURE 8. Split Supply VOUT(MAX) and VOUT(MIN) Output Levels 19 www.national.com LMH6553 OUTPUT NOISE PERFORMANCE AND MEASUREMENT Unlike differential amplifiers based on voltage feedback architectures, noise sources internal to the LMH6553 refer to the inputs largely as current sources, hence the low input referred voltage noise and relatively higher input referred current noise. The output noise is therefore more strongly coupled to the value of the feedback resistor and not to the closed loop gain, as would be the case with a voltage feedback differential amplifier. This allows operation of the LMH6553 at much higher gain without incurring a substantial noise performance penalty, simply by choosing a suitable feedback resistor. Figure 9 shows a circuit configuration used to measure noise figure for the LMH6553 in a 50Ω system. An RF value of 275Ω is chosen for the PSOP package to minimize output noise while simultaneously allowing both high gain (9 V/V) and proper 50Ω input termination. Refer to the section titled Single-Ended Input Operation for calculation of resistor and gain values. Noise figure values at various frequencies are shown in the plot titled Noise Figure in the Typical Performance Characteristics section. 30043766 FIGURE 10. Driving a 14-bit ADC Figure 11 shows the SFDR and SNR performance vs. frequency for the LMH6553 and ADC14C105 combination circuit with the ADC input signal level at −1 dBFS. The ADC14C105 is a single channel 14-bit ADC with maximum sampling rate of 105 MSPS. The amplifier is configured to provide a gain of 2 V/V in single to differential mode. An external bandpass filter is inserted in series between the input signal source and the amplifier to reduce harmonics and noise from the signal generator. In order to properly match the input impedance seen at the LMH6553 amplifier inputs, RM is chosen to match ZS || RT for proper input balance. 30043750 FIGURE 9. Noise Figure Circuit Configuration DRIVING ANALOG TO DIGITAL CONVERTERS Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with large and often variable capacitive components. As well, there are usually current spikes associated with switched capacitor or sample and hold circuits. Figure 10 shows the LMH6553 driving the ADC14C105. The amplifier is configured to provide a gain of 2 V/V in a single-to-differential mode. The LMH6553 common mode voltage is set by the ADC14C105. The 0.1 µF capacitor, in series with the 49.9Ω resistor, is inserted to ground across the 68.1Ω resistor to balance the amplifier inputs. The circuit in Figure 10 has a 2nd order lowpass LC filter formed by the 620 nH inductors along with the 22 pF capacitor across the differential inputs of the ADC14C105. The filter has a pole frequency of about 50 MHz. The two 100Ω resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. For switched capacitor input ADCs, the input capacitance will vary based on the clock cycle, as the ADC switches between the sample and hold mode. See your particular ADC's datasheet for details. 30043768 FIGURE 11. LMH6553/ADC14C105 SFDR and SNR Performance vs. Frequency The amplifier and ADC should be located as close together as possible. Both devices require that the filter components be in close proximity to them. The amplifier needs to have minimal parasitic loading on it's outputs and the ADC is sensitive to high frequency noise that may couple in on its inputs. Some high performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2). The LMH6553 is capable of driving a variety of National Semiconductor Analog-to-Digital Converters. This is shown in Table 3, which offers a list of possible signal path ADC and amplifier combinations. The use of the LMH6553 to drive an ADC is determined by the application and the desired sampling process (Nyquist operation, sub-sampling or over-sampling). See application note AN-236 for more details on the sampling processes and application note AN-1393 'Using www.national.com 20 LMH6553 High Speed Differential Amplifiers to Drive ADCs. For more information regarding a particular ADC, refer to the particular ADC datasheet for details. TABLE 3. DIFFERENTIAL INPUT ADCs COMPATIBLE WITH LMH6553 DRIVER Product Number Max Sampling Rate (MSPS) 15 20 42 50 60 60 100 200 500 1000 1000 20 20 27 40 65 65 80 66 66 125 170 10 20 40 40 40 65 66 63 80 80 80 105 105 170 20 40 80 80 105 105 155 Resolution Channels ADC1173 ADC1175 ADC08351 ADC1175-50 ADC08060 ADC08L060 ADC08100 ADC08200 ADC08500 ADC081000 ADC08D1000 ADC10321 ADC10D020 ADC10030 ADC10040 ADC10065 ADC10DL065 ADC10080 ADC11DL066 ADC11L066 ADC11C125 ADC11C170 ADC12010 ADC12020 ADC12040 ADC12D040 ADC12DL040 ADC12DL065 ADC12DL066 ADC12L063 ADC12C080 ADC12DS080 ADC12L080 ADC12C105 ADC12DS105 ADC12C170 ADC14L020 ADC14L040 ADC14C080 ADC14DS080 ADC14C105 ADC14DS105 ADC14155 8 8 8 8 8 8 8 8 8 8 8 10 10 10 10 10 10 10 11 11 11 11 12 12 12 12 12 12 12 12 12 12 12 12 12 12 14 14 14 14 14 14 14 SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE DUAL SINGLE DUAL SINGLE DUAL SINGLE DUAL SINGLE DUAL SINGLE SINGLE SINGLE SINGLE SINGLE SINGLE DUAL DUAL DUAL DUAL SINGLE SINGLE DUAL SINGLE SINGLE DUAL SINGLE SINGLE SINGLE SINGLE DUAL SINGLE DUAL SINGLE DRIVING CAPACITIVE LOADS As noted previously, capacitive loads should be isolated from the amplifier outputs with small valued resistors. This is particularly the case when the load has a resistive component that is 500Ω or higher. A typical ADC has capacitive components of around 10 pF and the resistive component could be 1000Ω or higher. If driving a transmission line, such as 50Ω coaxial or 100Ω twisted pair, using matching resistors will be sufficient to isolate any subsequent capacitance. For other applications see the Suggested ROUT vs. Capacitive Load charts in the Typical Performance Characteristics section. BALANCED CABLE DRIVER With up to 8 VPP differential output voltage swing and 100 mA of linear drive current the LMH6553 makes an excellent cable driver as shown in Figure 12. The LMH6553 is also suitable for driving differential cables from a single ended source. 30043702 FIGURE 12. Fully Differential Cable Driver POWER SUPPLY BYPASSING The LMH6553 requires supply bypassing capacitors as shown in Figure 13 and Figure 14. The 0.01 µF and 0.1 µF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply pins. These capacitors should be star routed with a dedicated ground return plane or trace for best harmonic distortion performance. A small capacitor, ~0.01 µF, placed across the supply rails, and as close to the chip's supply pins as possible, can further improve HD2 performance. Narrow traces or small vias will reduce the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM and VCLAMP pins to ground. These inputs are high impedance and can provide a coupling path into the amplifier for external noise sources, possibly resulting in loss of dynamic range, degraded CMRR, degraded balance and higher distortion. 21 www.national.com LMH6553 3. Calculate the total RMS power: PT = PAMP + PD. The maximum power that the LMH6553 package can dissipate at a given temperature can be derived with the following equation: PMAX = (150° – TAMB)/ θJA, where TAMB = Ambient temperature (°C) and θJA = Thermal resistance, from junction to ambient, for a given package (°C/W). For the PSOP package θJA is 59°C/W; LLP package θJA is 58°C/W. NOTE: If VCM is not mid-rail, then there will be quiescent current flowing in the feedback network. This current should be included in the thermal calculations and added into the quiescent power dissipation of the amplifier. ESD PROTECTION The LMH6553 is protected against electrostatic discharge (ESD) on all pins. The LMH6553 will survive 4000V Human Body model and 350V Machine model events. Under normal operation the ESD diodes have no effect on circuit performance. The current that flows through the ESD diodes will either exit the chip through the supply pins or through the device, hence it is possible to power up a chip with a large signal applied to the input pins. BOARD LAYOUT The LMH6553 is a very high performance amplifier. In order to get maximum benefit from the differential circuit architecture, board layout and component selection are very critical. The circuit board should have a low inductance ground plane and well bypassed wide supply lines. External components should be leadless surface mount types. The feedback network and output matching resistors should be composed of short traces and precision resistors (0.1%). The output matching resistors should be placed within 3 or 4 mm of the amplifier as should the supply bypass capacitors. Refer to the section titled Power Supply Bypassing for recommendations on bypass circuit layout. Evaluation boards are available free of charge through the product folder on National’s web site. By design, the LMH6553 is relatively insensitive to parasitic capacitance at its inputs. Nonetheless, ground and power plane metal should be removed from beneath the amplifier and from beneath RF and RG for best performance at high frequency. With any differential signal path, symmetry is very important. Even small amounts of asymmetry can contribute to distortion and balance errors. EVALUATION BOARD National Semiconductor suggests the following evaluation boards to be used with the LMH6553: Device LMH6553MR LMH6553SD Package PSOP LLP Evaluation Board Ordering ID 55160019 LMH6553SDEVAL 30043701 FIGURE 13. Split Supply Bypassing Capacitors 30043712 FIGURE 14. Single Supply Bypassing Capacitors POWER DISSIPATION The LMH6553 is optimized for maximum speed and performance in the small form factor of the standard LLP package. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX of 150°C is never exceeded. Follow these steps to determine the maximum power dissipation for the LMH6553: 1. Calculate the quiescent (no-load) power: PAMP = ICC* VS, where VS = V+ - V−. (Be sure to include any current through the feedback network if VCM is not mid-rail.) 2. Calculate the RMS power dissipated in each of the output stages: PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms ((VS − V−OUT) * I−OUT) , where VOUT and IOUT are the voltage and the current measured at the output pins of the differential amplifier as if they were single ended amplifiers and VS is the total supply voltage. These evaluation boards can be shipped when a device sample request is placed with National Semiconductor. www.national.com 22 LMH6553 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin PSOP NS Package Number MRA08A 8-Pin LLP NS Package Number SDA08C 23 www.national.com LMH6553 900 MHz Fully Differential Amplifier With Output Limiting Clamp Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/AU Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero Solar Magic® Analog University® THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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