LMH6572MQX

LMH6572 Triple 2:1 High Speed Video Multiplexer June 2005 LMH6572 Triple 2:1 High Speed Video Multiplexer General Description The LMH™6572 is a high performance analog mulitplexer optimized for professional grade video and other high fidelity high bandwidth analog applications. The LMH6572 provides a 290MHz bandwidth at 2 VPP output signal levels. The 140 MHz of .1 dB bandwidth and a 1500 V/µs slew rate make this part suitable for High Definition Television (HDTV) and High Resolution Multimedia Video applications. The LMH6572 supports composite video applications with its 0.02% and 0.02˚ differential gain and phase errors for NTSC and PAL video signals while driving a single, back terminated 75Ω load. The LMH6572 can deliver 80 mA linear output current for driving multiple video load applications. The LMH6572 has an internal gain of 2 V/V (+6 dBv) for driving back terminated transmission lines at a net gain of 1 V/V (0 dBv). The LMH6572 is available in the SSOP package. Features n n n n n n n n n n 350 MHz, 250 mV −3 dB bandwidth 290 MHz, 2 VPP −3 dB bandwidth 10 ns channel switching time 90 dB channel to channel isolation @ 5 MHz 0.02%, 0.02˚ diff. gain, phase .1 dB gain flatness to 140 MHz 1400 V/µs slew rate Wide supply voltage range: 6V ( ± 3V) to 12V ( ± 6V) −78 dB HD2 @ 10 MHz −75 dB HD3 @ 10 MHz Applications n RGB video router n Multi-input video monitor n Fault tolerant data switch Connection Diagram 16-Pin SSOP Truth Table SEL 0 1 X EN 0 0 1 OUT CH 1 CH 0 Disable 20109605 Top View Ordering Information Package 16-Pin SSOP Part Number LMH6572MQ LMH6572MQX Package Marking LH6572MQ Transport Media 95 Units/Rail 2.5 Units Tape and Reel NSC Drawing MQA16 LMH™ is a trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS201096 www.national.com LMH6572 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance Human Body Model Machine Model Supply Voltage (V+ − V−) IOUT (Note 3) IInput Voltage Range Maximum Junction Temperature Storage Temperature Range (Note 4) 2000V 200V 13.2V 130 mA Soldering Information Infrared or Convection (20 sec) Wave Soldering (10 sec) 235˚C 260˚C Operating Ratings Operating Temperature Supply Voltage Range Thermal Resistance Package 16-Pin SSOP (Note 1) −40˚C 6V (θJA) 125˚C/W to to 85˚C 12V (θJC) 36˚C/W ± VS +150˚C (Note 4) −65˚C to +150˚C ± 5V Electrical Characteristics Unless otherwise specified, VS = ± 5V, RL = 100Ω . Symbol SSBW LSBW .1 dBBW DG DP TRS Parameter −3 dB Bandwidth –3 dB Bandwidth (Note 6) . 1 dB Bandwidth Differential Gain Differential Phase Conditions(Note 2) VOUT = 0.25 VPP VOUT = 2 VPP VOUT = 0.25 VPP RL = 150Ω, f=4.43 MHz RL = 150Ω, f=4.43 MHz 250 Min Typ 350 290 140 0.02 0.02 10 11 1.5 17 5 1200 1400 −78 −75 −80 5 5 2.0 No load, with respect to nominal gain of 2.00 V/V. RL = 50Ω, with respect to nominal gain of 2.00 V/V VIN = 0V Max Units MHz MHz MHz % deg ns ns ns ns % V/µs dBc dBc dBc nV pA/ V/V Frequency Domain Performance Time Domain Response Channel to Channel Switching Time Logic transition to 90% output Enable and Disable Times TRL TSS OS SR Distortion HD2 HD3 IMD VN ICN GAIN 2nd Harmonic Distortion 3 rd Logic transition to 90% or 10% output. 2V Step 2V Step 4V Step 4V Step 2 VPP , 10 MHz 2 VPP , 10 MHz 10 MHz, Two tones 2Vpp at output Rise and Fall Time Settling Time to 0.05% Overshoot Slew Rate(Note 6) Harmonic Distortion 3rd Order Intermodulation Products Voltage Current Voltage Gain Gain Error(Note 5) Equivalent Input Noise > 1 MHz, Input Referred > 1 MHz, Input Referred Static, DC Performance ± 0.3 ± 0.5 ± 0.7 % Gain Error VIO DVIO IBN DIBN PSRR Output Offset Voltage (Note 5) Average Drift Input Bias Current (Notes 7, 5) Average Drift Power Supply Rejection Ratio (Note 5) 0.3 1 27 % ± 14 ± 17.5 ± 2.8 ± 3.5 mV µV/˚C µA nA/˚C dB VIN = 0V −1.4 7 DC, Input referred 50 48 54 www.national.com 2 LMH6572 ± 5V Electrical Characteristics Unless otherwise specified, VS = ± 5V, RL = 100Ω . Symbol ICC Parameter Supply Current (Note 5) Supply Current Disabled(Note 5) VIH VIL IiL IiH Logic High Threshold(Note 5) Logic Low Threshold (Note 5) (Continued) Conditions(Note 2) No load No load Select & Enable Pins Select & Enable Pins Min 20 Typ 23 2.0 Max 25 28.5 2.2 2.3 0.8 Units mA mA V V µA µA 2.0 −1 112 100 650 620 150 Logic Pin Input Current Low(Note 7) Logic Input = 0V Logic Pin Input Current High(Note 7) Internal Feedback and Gain Set resistor Values Disabled Output Resistance Input Resistance Input Capacitance Output Resistance Output Voltage Range No load RL = 100Ω Input Voltage Range Linear Output Current (Notes 5, 7) Short Circuit Current Channel to Channel Crosstalk Channel to Channel Crosstalk All Hostile Crosstalk VIN = 0V, VIN = ± 2V, Output shorted to ground VIN = 2 VPP @5 MHz VIN = 2 VPP @ 100 MHZ In A, C. Out B, VIN = 2 VPP @ 5 MHz Internal Feedback and Gain Set resistors in series to ground. Logic Input = 2.0V ± 2.5 ± 10 200 210 940 1010 1.88 Miscellaneous Performance RF RODIS RIN+ CIN ROUT VO VOL CMIR IO ISC XTLK XTLK XTLK 800 1.6 100 0.9 0.26 Ω kΩ kΩ pF Ω V V V mA mA dBc dBc dBc 1.3 ± 3.83 ± 3.80 ± 3.52 ± 3.5 ±2 +70 -40 ± 3.9 ± 3.53 ± 2.5 ± 80 ± 230 −90 −54 −95 ± 3.3V Electrical Characteristics Unless otherwise specified, VS = ± 3.3V, RL = 100Ω. Symbol SSBW LSBW .1 dBBW GFP DG DP TRS TSS OS SR Distortion HD2 2nd Harmonic Distortion 2 VPP, 10MHz −70 dBc Parameter −3 dB Bandwidth −3 dB Bandwidth .1 dB Bandwidth Peaking Differential Gain Differential Phase Rise and Fall Time Settling Time to 0.05% Overshoot Slew Rate Conditions(Note 2) VOUT = 0.25 VPP VOUT = 2.0 VPP VOUT = 0.5 VPP DC to 200 MHz RL = 150Ω, f=4.43 MHz RL = 150Ω, f=4.43 MHz 2V Step 2V Step 2V Step 2V Step Min Typ 360 270 80 0.3 0.02 0.03 2.0 15 5 1000 Max Units MHz MHz MHz dB % deg ns ns % V/µs Frequency Domain Performance Time Domain Response 3 www.national.com LMH6572 ± 3.3V Electrical Characteristics Unless otherwise specified, VS = ± 3.3V, RL = 100Ω. Symbol HD3 IMD GAIN VIO DVIO IBN DIBN PSRR ICC VIH VIL RIN+ CIN ROUT VO VOL CMIR IO ISC XTLK Input Voltage Range Linear Output Current Short Circuit Current Channel to Channel Crosstalk 3 rd (Continued) Parameter 3rd Harmonic Distortion Order Intermodulation Products Conditions(Note 2) 2 VPP, 10MHz 10 MHz, Two tones 2Vpp at output Min Typ −74 −79 2.0 Max Units dBc dBc V/V mV µV/˚C µA nA/˚C dB mA Static, DC Performance Voltage Gain Output Offset Voltage Average Drift Input Bias Current (Note 7) Average Drift Power Supply Rejection Ratio Supply Current Logic High Threshold Logic Low Threshold Input Resistance Input Capacitance Output Resistance Output Voltage Range No load RL = 100Ω VIN = 0V VIN = ± 1V, Output shorted to ground 5 MHz DC, Input Referred RL = ∞ Select & Enable Pins Select & Enable Pins 0.4 100 0.9 0.27 VIN = 0V VIN = 0V 1 36 2 24 54 20 1.3 V V kΩ pF Ω V V V mA mA dBc Miscellaneous Performance ± 2.5 ± 2.2 ± 1.2 ± 60 ± 150 −90 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. See Applications Section for information on temperature de-rating of this device. Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted. Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Application Section for more details. A short circuit condition should be limited to 5 seconds or less. Note 4: Human Body Model 1.5 kΩ in series with 100 pF. Machine Model 0Ω In series with 200 pF Note 5: Parameters guaranteed by electrical testing at 25˚ C. Note 6: Parameters guaranteed by design. Note 7: Positive Value is current into device. www.national.com 4 LMH6572 Typical Performance Characteristics Frequency Response vs. VOUT Unless otherwise specified, Vs = ± 5V, RL = 100Ω. Frequency Response vs. VOUT 20109602 20109601 Frequency Response vs. Capacitive Load Suggested RS vs. Capacitive Load Load= 1kΩ i CL 20109613 20109604 Harmonic Distortion vs. Output Voltage Harmonic Distortion vs. Output Voltage 20109611 20109612 5 www.national.com LMH6572 Typical Performance Characteristics Unless otherwise specified, Vs = ±5V, RL = 100Ω. Harmonic Distortion vs. Frequency (Continued) Harmonic Distortion vs. Frequency 20109603 20109610 Harmonic Distortion vs. Supply Voltage Channel Switching Time 20109616 20109621 Disable Time Pulse Response 20109626 20109625 www.national.com 6 LMH6572 Typical Performance Characteristics Unless otherwise specified, Vs = ±5V, RL = 100Ω. Crosstalk PSRR (Continued) 20109614 20109607 PSRR Closed Loop Output Impedance 20109606 20109609 Closed Loop Output Impedance 20109608 7 www.national.com LMH6572 Application Notes GENERAL INFORMATION The LMH6572 is a high-speed triple 2:1 multiplexer, optimized for very high speed and low distortion. With a fixed gain of 2 and excellent AC performance, the LMH6572 is ideally suited for switching high resolution, presentation grade video signals. The LMH6572 has no internal ground reference. Single or split supply configurations are both possible. The LMH6572 features very high speed channel switching and disable times. When disabled the LMH6572 output is high impedance, making multiplexer expansion possible by combining multiple devices. SINGLE SUPPLY OPERATION The LMH6572 uses mid-supply referenced circuits for the select and disable pins. In order to use the LMH6572 in single supply configuration, it is necessary to use a circuit similar to Figure 2. In this configuration the logical inputs are compatible with high breakdown open collector TTL, or open drain CMOS logic. In addition, the default logic state is reversed since there is a pull-up resistor on those pins. Single supply operation also requires the input to be biased to within the common mode input range of roughly ± 2V from the mid-supply point. 20109623 20109622 FIGURE 2. Single Supply Application GAIN ACCURACY The gain accuracy of the LMH6572 is accurate to ± 0.5% (0.3% typical) and stable over temperature. The internal gain setting resistors, RF and RG, match very well; however, over process and temperature their absolute value will change. EXPANDING THE MULTIPLEXER It is possible to build higher density multiplexers by paralleling several LMH6572s. Figure 3 shows a 4:1 RGB MUX using two LMH6572s: FIGURE 1. Typical Application VIDEO PERFORMANCE The LMH6572 has been designed to provide excellent performance with production quality video signals in a wide variety of formats such as HDTV and High Resolution VGA. Best performance will be obtained with back-terminated loads. The back termination reduces reflections from the transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier output stage.Figure 1 shows a typical configuration for driving a 75Ω cable. The output buffer is configured for a gain of 2, so using back terminated loads will give a net gain of 1. www.national.com 8 LMH6572 Application Notes (Continued) 20109618 FIGURE 3. RGB MUX USING TWO LMH6572’s If it is important in the end application to make sure that no two inputs are presented to the output at the same time, an optional delay block can be added prior to the ENABLE (EN) pin of each device, as shown. Figure 4 shows one possible approach to this delay circuit. The delay circuit shown will delay ENABLE’s H to L transitions (R1 and C1 decay) but will not delay its L to H transition. a triple 8:1 MUX. With the internal resistors valued at approximately 800Ω, the gain error is about -0.57 dB, or about −6%. 20109619 FIGURE 4. Delay Circuit Implementation R2 should be kept small compared to R1 in order to not reduce the ENABLE voltage and to produce little or no delay to theENABLE L to H transition. With the ENABLE pin putting the output stage into a high impedance state, several LMH6572’s can be tied together to form a larger input MUX. However, there is a slight loading effect on the active output caused by the off-channel feedback and gain set resistors, as shown in Figure 5. Figure 5 is assuming there are 4 LMH6572 devices tied together to form 9 20109617 FIGURE 5. Multiplexer Input Expansion by Combining Outputs An alternate approach would be to tie the outputs directly together and let all devices share a common back termination resistor in order to alleviate the gain error issue above. www.national.com LMH6572 Application Notes (Continued) The drawback in this case is the increased capacitive load presented to the output of each LMH6572 due to the offstate capacitance of the LMH6572. Other Applications The LMH6572 may be utilized in systems that involve a single RGB channel as well whenever there is a need to switch between different “flavors” of a single RGB input. Here are some examples: 1. RGB positive polarity, negative polarity switch 2. RGB full resolution, high-pass filter switch In each of these applications, the same RGB input occupies one set of inputs to the LMH6572 and the other “flavor” would be tied to the other input set. DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor. Figure 6 shows the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. Figure 7gives a recommended value for selecting a series output resistor for mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the frequency response. This gives a good compromise between settling time and bandwidth. For applications where maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values. 20109604 FIGURE 7. Recommended ROUT vs. Capacitive Load 20109613 FIGURE 8. Frequency Response vs. Capacitive Load 20109624 FIGURE 6. Decoupling Capacitive Loads LAYOUT CONSIDERATIONS Whenever questions about layout arise, use the LMH730151 evaluation board as a guide. To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins. For long signal paths controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device; however, the smaller ceramic capacitors should be placed as close to the device as possible. In Figure 1 and Figure 2, the capacitor between V+ and V− is optional, but is recommended for best second harmonic distortion. Another way to enhance performance is to use pairs of .01 µF and .1 µF ceramic capacitors for each supply bypass. POWER DISSIPATION The LMH6572 is optimized for maximum speed and performance in the small form factor of the standard SSOP package. To achieve its high level of performance, the LMH6572 www.national.com 10 LMH6572 Other Applications (Continued) consumes 23 mA of quiescent current, which cannot be neglected when considering the total package power dissipation limit. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation. Follow these steps to determine the Maximum power dissipation for the LMH6572: 1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS), where VS = V+ - V−. Calculate the RMS power dissipated in the output stage: PD (rms) = rms ((VS - VOUT) * IOUT), where VOUT and IOUT are the voltage across and the current through the external load and VS is the total supply voltage. 3. Calculate the total RMS power: PT = PAMP + PD. The maximum power that the LMH6572 package can dissipate at a given temperature can be derived with the following equation: PMAX = (150˚ – TAMB)/ θJA, where TAMB = Ambient Temperature (˚C) and θJA = Thermal Resistance from junction to ambient for a given package (˚C/W). For the SSOP package θJA is 125˚C/W. ESD PROTECTION The LMH6572 is protected against electrostatic discharge (ESD) on all pins. The LMH6572 will survive 2000V Human Body model and 200V Machine model events. Under normal 2. operation the ESD diodes have no effect on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6572 is driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to power up a chip with a large signal applied to the input pins. Shorting the power pins to each other will prevent the chip from being powered up through the input. EVALUATION BOARDS National Semiconductor provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. Many of the datasheet plots were measured with these boards. Device LMH6572 Package TSSOP Evaluation Board Part Number LMH730151 An evaluation board can be shipped when a device sample request is placed with National Semiconductor. 11 www.national.com LMH6572 Triple 2:1 High Speed Video Multiplexer Physical Dimensions inches (millimeters) unless otherwise noted 16-Pin SSOP NS Package Number MQA16 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. Leadfree products are RoHS compliant. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.