LMH6585VV

LMH6584/LMH6585 32x16 400 MHz Analog Crosspoint Switches, Gain of 1, Gain of 2 PRELIMINARY April 2, 2008 LMH6584/LMH6585 32x16 400 MHz Analog Crosspoint Switches, Gain of 1, Gain of 2 General Description The family of products is joined by the LMH6584 and the LMH6585 high speed, non-blocking, analog, crosspoint switches. The LMH6584/LMH6585 are designed for high speed, DC coupled, analog signals such as high resolution video (UXGA and higher). The LMH6584/LMH6585 have 32 inputs and 16 outputs. The non-blocking architecture allows an output to be connected to any input, including an input that is already selected. With fully buffered inputs the LMH6584/ LMH6585 can be impedance matched to nearly any source impedance. The buffered outputs of the LMH6584/LMH6585 can drive up to two back terminated video loads (75Ω load). The outputs and inputs also feature high impedance inactive states allowing high performance input and output expansion for array sizes such as 32 x 32 or 64 x 16 by combining two devices. The LMH6584/LMH6585 are controlled with a 4 pin serial interface. Both single serial mode and addressed chain modes are available. The LMH6584/LMH6585 come in 144-pin LQFP packages. They also have diagonally symmetrical pin assignments to facilitate double sided board layouts and easy pin connections for expansion. LMH® Features ■ ■ ■ ■ ■ ■ ■ ■ ■ 32 inputs and 16 outputs 144-pin LQFP package −3 dB bandwidth (VOUT = 2 VPP, RL = 150Ω) 400 MHz Fast slew rate 1200 V/μs Channel to channel crosstalk (10/100 MHz) −52/ −43 dBc Easy to use serial programming 4 wire bus Two programming modes Serial & addressed modes Symmetrical pinout facilitates expansion. Output current ±50 mA Applications ■ ■ ■ ■ ■ ■ ■ ■ Studio monitoring/production video systems Conference room multimedia video systems KVM (keyboard video mouse) systems Security/surveillance systems Multi antenna diversity radio Video test equipment Medical imaging Wide-band routers & switches Block Diagram 30045011 LMH® is a registered trademark of National Semiconductor Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 300450 www.national.com LMH6584/LMH6585 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Machine Model VS IIN (Input Pins) IOUT Input Voltage Range Maximum Junction Temperature 2000V 200V ±6V ±20 mA (Note 3) V− to V+ +150°C (Note 5) Storage Temperature Range Soldering Information Infrared or Convection (20 sec.) Wave Soldering (10 sec.) −65°C to +150°C 235°C 260°C Operating Ratings Temperature Range (Note 4) Supply Voltage Range Thermal Resistance 64–Pin Exposed Pad TQFP (Note 1) −40°C to +85°C ±3V to ±5.5V θJA 22°C/W θJC 5°C/W ±3.3V Electrical Characteristics Unless otherwise specified, typical conditions are: TA = 25°C, VS = ±3.3V, RL = 100Ω. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 8) Typ (Note 7) 350 350 375 375 375 375 50 MHz % deg ns ns % V/µs ns −70 −75 12 22 −43 −60 1.00 2.00 ±3 (Note 10) Non-Inverting (Note 9) Non-Inverting (Note 10) −5 mV µV/°C µA nA/°C dBc dBc nV/ pA/ ns Channel to channel, f = 100 MHz f = 100 MHz LMH6584 LMH6585 VOS TCVOS IB TCIB Input Offset Voltage Input Offset Voltage Temperature Drift Input Bias Current Input Bias Current Average Drift dBc dBc MHz Max (Note 8) Units Frequency Domain Performance SSBW LSBW −3 dB Bandwidth LMH6584, VOUT = 0.25 VPP LMH6585V, VOUT = 0.5 VPP LMH6584, VOUT = 1VPP, RL = 1 kΩ LMH6585, VOUT = 2VPP, RL = 1 kΩ LMH6584, VOUT = 1VPP, RL = 150Ω LMH6585, VOUT = 2VPP, RL = 150Ω GF DG DP tr tf OS SR ts HD2 HD3 en in XTLK ISOL AVOL 0.1 dB Gain Flatness Differential Gain Differential Phase Rise Time Fall Time Overshoot Slew Rate Settling Time 2nd Harmonic Distortion 3rd Harmonic Distortion Input Referred Voltage Noise Input Referred Current Noise Switching Time Crosstalk Off Isolation Open Loop Voltage Gain VOUT = 2 VPP, RL = 150Ω RL = 150Ω, 3.58 MHz/4.43 MHz RL = 150Ω, 3.58 MHz/4.43 MHz 2V Step, 10% to 90% 2V Step, 10% to 90% 2V Step 4 VPP, 40% to 60% (Note 6) 2V Step, VOUT within 0.5% LMH6584, 1 VPP, 10 MHz 1 VPP, 10 MHz >1 MHz >1 MHz Time Domain Response Distortion And Noise Response Static, DC Performance www.national.com 2 LMH6584/LMH6585 Symbol VOUT Parameter Output Voltage Range Conditions RL = 100Ω, LMH6584 RL = ∞, LMH6584(Note 11) RL = 100Ω, LMH6585 RL = ∞, LMH6585 Min (Note 8) Typ (Note 7) ±1.6 ±1.6 ±2.1 ±2.2 45 Max (Note 8) Units V PSRR ICC IEE Power Supply Rejection Ratio Positive Supply Current Negative Supply Current Tri State Supply Current RL = ∞ RL = ∞ RST Pin > 2.0V Non-Inverting Non-Inverting Closed Loop, Enabled Disabled, LMH6584 Disabled, LMH6585 dB mA mA mA kΩ pF mΩ kΩ V mA V 0.8 V V V ns ns 200 194 40 100 3 300 50 1.3 ±0.8 Miscellaneous Performance RIN CIN RO Input Resistance Input Capacitance Output Resistance Enabled Output Resistance Disabled Output Resistance Disabled CMVR IO VIH VIL VOH VOL TS TH Input Common Mode Voltage Range Output Current Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Setup Time Hold Time (Note 5) >2.2 1 MHz >1 MHz Channel to Channel, f = 100 MHz Channel to Channel, f = 10 MHz f = 100 MHz LMH6584 LMH6585 Input Referred (Note 10) Non-Inverting (Note 9) Non-Inverting (Note 10) RL = 100Ω, LMH5484 RL = ∞, LMH6584 RL = 100Ω, LMH6585 RL = ∞, LMH6585 ±3.1 ±3.2 ±3.6 ±3.9 45 −80 −80 220 200 44 100 1 300 50 1.3 ±3.1 Sourcing, VO = 0 V 2.0 0.8 >2.4 2.0V Non-Inverting Non-Inverting Closed Loop, Enabled Disabled, Resistance to Ground, LMH6584 Disabled, Resistance to Ground, LMH6585 dB dB dB mA mA mA kΩ pF mΩ kΩ Miscellaneous Performance RIN CIN RO Input Resistance Input Capacitance Output Resistance Enabled Output Resistance Disabled CMVR IO VIH VIL VOH VOL Input Common Mode Voltage Range Output Current Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low V mA V V V V ±60 Digital Control www.national.com LMH6584/LMH6585 Symbol TS TH Setup Time Hold Time Parameter Conditions Min (Note 8) Typ (Note 7) 8 8 Max (Note 8) Units ns ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations. Note 4: The maximum power dissipation is a function of TJ(MAX)and θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. Note 5: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the electrical tables under conditions different than those tested. Note 6: Slew Rate is the average of the rising and falling edges. Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 8: Room Temperature limits are 100% production tested at 25°C. Device self heating results in TJ ≥ TA, however, test time is insufficient for TJto reach steady state conditions. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Note 9: Negative input current implies current flowing out of the device. Note 10: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Note 11: This parameter is guaranteed by design and/or characterization and is not tested in production. Ordering Information Package 144-Pin LQFP Part Number LMH6584VV LMH6585VV Package Marking LMH6584VV LMH6585VV Transport Media 60 Units/Tray NSC Drawing VNG144C 5 www.national.com LMH6584/LMH6585 Block and Connection Diagram 144-Pin LQFP 30045002 Top View www.national.com 6 LMH6584/LMH6585 Typical Performance Characteristics LMH6584 Unless otherwise specified, typical conditions are: TA = 25°C, AV = +1, VS = ±5V, RL = 150Ω. Boldface limits apply at the temperature extremes. 1 VPP Frequency Response 1 VPP Frequency Response 30045048 30045049 Small Signal Bandwidth Small Signal Bandwidth 30045024 30045025 Group Delay Group Delay Broadcast 30045041 30045054 7 www.national.com LMH6584/LMH6585 Second Order Distortion (HD2) vs. Frequency Third Order Distortion (HD3) vs. Frequency 30045026 30045028 Second Order Distortion vs. Frequency Third Order Distortion vs. Frequency 30045027 30045029 Output Swing Output Swing 30045030 30045031 www.national.com 8 LMH6584/LMH6585 Output Swing over Temperature Output Swing over Temperature 30045032 30045033 Pulse Response Pulse Response 30045013 30045014 9 www.national.com LMH6584/LMH6585 Typical Performance Characteristics LMH6585 Unless otherwise specified, typical conditions are: TA = 25°C, AV = +2, VS = ±5V, RL = 150Ω; Boldface limits apply at the temperature extremes. 2 VPP Frequency Response 2 VPP Frequency Response 30045055 30045056 Small Signal Frequency Response Small Signal Frequency Response 30045057 30045058 Group Delay Group Delay 30045059 30045060 www.national.com 10 LMH6584/LMH6585 Application Information INTRODUCTION The LMH6584/LMH6585 are high speed, fully buffered, non blocking, analog crosspoint switches. Having fully buffered inputs allow the LMH6584/LMH6585 to accept signals from low or high impedance sources without the worry of loading the signal source. The fully buffered outputs will drive 75Ω or 50Ω back terminated transmission lines with no external components other than the termination resistor. When disabled, the outputs are in a high impedance state. The LMH6584/ LMH6585 can have any input connected to any (or all) output (s). Conversely, a given output can have only one associated input. INPUT AND OUTPUT EXPANSION The LMH6584/LMH6585 have high impedance inactive states for both inputs and outputs allowing maximum flexibility for Crosspoint expansion. In addition the LMH6584/LMH6585 employ diagonal symmetry in pin assignments. The diagonal symmetry makes it easy to use direct pin to pin vias when the parts are mounted on opposite sides of a board. As an example two LMH6584/LMH6585 chips can be combined on one board to form either an 32 x 32 crosspoint or a 64 x 16 crosspoint. To make a 32 x 32 cross-point all 32 input pins would be tied together (Input 0 on side 1 to input 31 on side 2 and so on) while the 16 output pins on each chip would be left separate. To make the 64 x 16 crosspoint, the 16 outputs would be tied together while all 64 inputs would remain independent. In the 64 x 16 configuration it is important not to have two connected outputs active at the same time. With the 32 x 32 configuration, on the other hand, having two connected inputs active is a valid state. Crosspoint expansion as detailed above has the advantage that the signal path has only one crosspoint in it at a time. Expansion methods that have cascaded stages will suffer bandwidth loss far greater than the small loading effect of parallel expansion. Output expansion is very straight forward. Connecting the inputs of two crosspoint switches has a very minor impact on performance. Input expansion requires more planning. As show in Figure 1 and Figure 2 there are two ways to connect the outputs of the crosspoint switches. In Figure 2 the crosspoint switch outputs are connected directly together and share one termination resistor. This is the easiest configuration to implement and has only one drawback. Because the disabled output of the unused crosspoint (only one output can be active at a time) has a small amount of capacitance, the frequency response of the active crosspoint will show peaking. As illustrated in Figure 1 each crosspoint output can be given its own termination resistor. This results in a frequency response nearly identical to the non expansion case. There is one drawback for the gain of 2 crosspoint, and that is gain error. With a 75Ω termination resistor the 1250Ω resistance of the disabled crosspoint output will cause a gain error. In order to counteract this the termination resistors of both crosspoints should be adjusted to approximately 71Ω. This will provide very good matching, but the gain accuracy of the system will now be dependent on the process variations of the crosspoint resistors which have a variability of approximately ±20%. 30045042 FIGURE 1. Output Expansion 30045043 FIGURE 2. Input Expansion with Shared Termination Resistors 11 www.national.com LMH6584/LMH6585 In the example in Figure 4 the resistor RL is required to provide a load for the crosspoint output buffer. Without RLexcessive frequency response peaking is likely and settling times of transient signals will be poor. As the value of RL is reduced the bandwidth will also go down. The amplifier shown in the example is an LMH6703 this amplifier offers high speed and flat bandwidth. Another suitable amplifier is the LMH6702. The LMH6702 is a faster amplifier that can be used to generate high frequency peaking in order to equalize longer cable lengths. If board space is at a premium the LMH6739 or the LMH6734 are triple selectable gain buffers which require no external resistors. CROSSTALK When designing a large system such as a video router, crosstalk can be a very serious problem. Extensive testing in our lab has shown that most crosstalk is related to board layout rather than the crosspoint switch. There are many ways to reduce board related crosstalk. Using controlled impedance lines is an important step. Using well decoupled power and ground planes will help as well. When crosstalk does occur within the crosspoint switch itself it is often due to signals coupling into the power supply pins. Using appropriate supply bypassing will help to reduce this mode of coupling. Another suggestion is to place as much grounded copper as possible between input and output signal traces. Care must be taken, though, not to influence the signal trace impedances by placing shielding copper too closely. One other caveat to consider is that as shielding materials come closer to the signal trace the trace needs to be smaller to keep the impedance from falling too low. Using thin signal traces will result in unacceptable losses due to trace resistance. This effect becomes even more pronounced at higher frequencies due to the skin effect. The skin effect reduces the effective thickness of the trace as frequency increases. Resistive losses make crosstalk worse because as the desired signal is attenuated with higher frequencies crosstalk increases at higher frequencies. DIGITAL CONTROL Block Diagram 30045044 FIGURE 3. Input Expansion with Separate Termination Resistors DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Capacitive loads of 5 pF to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. As starting values, a capacitive load of 5 pF should have around 75 Ω of isolation resistance. A value of 120 pF would require around 12Ω. When driving transmission lines the 50Ω or 75Ω matching resistor normally provides enough isolation. USING OUTPUT BUFFERING TO ENHANCE RELIABILITY The LMH6584/LMH6585 crosspoint switch can offer enhanced reliability with the use of external buffers on the outputs. For this technique to provide maximum benefit a very high speed amplifier such as the LMH6703 should be used, as shown in Figure 4 . The advantage offered by using external buffers is to reduce thermal loading on the crosspoint switch. This reduced die temperature will increase the life of the crosspoint. Another advantage is enhanced ESD reliability. It is very difficult to build high speed devices that can withstand all possible ESD events. With external buffers the crosspoint switch is isolated from ESD events on the external system connectors. 30045011 FIGURE 5. Block Diagram The LMH6584/LMH6585 has internal control registers that store the programming states of the crosspoint switch. The logic is two staged to allow for maximum programming flexibility. The first stage of the control logic is tied directly to the crosspoint switching matrix. This logic consists of one register for each output that stores the on/off state and the address of 12 30045040 FIGURE 4. Buffered Output www.national.com LMH6584/LMH6585 which input to connect to. These registers are not directly accessible by the user. The second level of logic is another bank of registers identical to the first, but set up as shift registers. These registers are accessed by the user via the serial input bus. As described further below, there are two modes for programing the LMH6584/LMH6585, Serial Mode and Addressed Mode. The LMH6584/LMH6585 are programmed via a serial input bus with the support of four other digital control pins. The serial bus consists of a clock pin (CLK), a serial data in pin (DIN), and a serial data out pin (DOUT). The serial bus is gated by a chip select pin (CS). The chip select pin is active low. While the chip select pin is high all data on the serial input pin and clock pins is ignored. When the chip select pin is brought low the internal logic is set to begin receiving data by the first positive transition (0 to 1) of the clock signal. The chip select pin must be brought low at least 5 ns before the first rising edge of the clock signal. The first data bit is clocked in on the next negative transition (1 to 0) of the clock signal. All input data is read from the bus on the negative edge of the clock signal. Once the last valid data has been clocked in, the chip select pin must go high then the clock signal must make at least one more low to high transition. Otherwise invalid data will be clocked into the chip. The data clocked into the chip is not transferred to the crosspoint matrix until the CFG pin is pulsed high. This is the case regardless of the state of the MODE pin. The CFG pin is not dependent on the state of the chip select pin. If no new data is clocked into the chip subsequent pulses on the CFG pin will have no affect on device operation. The programming format of the incoming serial data is selected by the MODE pin. When the MODE pin is HIGH the crosspoint can be programmed one output at a time by entering a string of data that contains the address of the output that is going to be changed (Addressed Mode). When the MODE pin is LOW the crosspoint is in Serial Mode. In this mode the crosspoint accepts a 40 bit array of data that programs all of the outputs. In both modes the data fed into the chip does not change the chip operation until the configure pin is pulsed high. The configure and mode pins are independent of the chip select pin. THREE WIRE VS. FOUR WIRE CONTROL There are two ways to connect the serial data pins. The first way is to control all four pins separately, and the second op- tion is to connect the CFG and the CS pins together for a three wire interface. The benefit of the four wire interface is that the chip can be configured independently of the CS pin. This would be an advantage in a system with multiple crosspoint chips where all of them could be programmed ahead of time and then configured simultaneously. The four wire solution is also helpful in a system that has a free running clock on the CLK pin. In this case, the CS pin needs to be brought high after the last valid data bit to prevent invalid data from being clocked into the chip. The three wire option provides the advantage of one less pin to control at the expense of having less flexibility with the configure pin. One way around this loss of flexibility would be if the clock signal is generated by an FPGA or microcontroller where the clock signal can be stopped after the data is clocked in. In this case the Chip Select function is provided by the presence or absence of the clock signal. SERIAL PROGRAMMING MODE Serial programming mode is the mode selected by bringing the MODE pin low. In this mode a stream of 96-bits programs all 16 outputs of the crosspoint. The data is fed to the chip as shown in the Serial Mode Data Frame tables below (four tables are shown to illustrate the pattern). The tables are arranged such that the first bit clocked into the crosspoint register is labeled bit number 0. The register labeled Load Register in the block diagram is a shift register. If the chip select pin is left low after the valid data is shifted into the chip and if the clock signal keeps running then additional data will be shifted into the register, and the desired data will be shifted out. Also illustrated are the timing relationships for the digital pins in the Timing Diagram for Serial Mode shown below. It is important to note that all the pin timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS) must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to synchronize to allow data to be accepted on the next falling edge. After the final data bit has been clocked in, the chip select pin must go high, then the clock signal must make at least one more low to high transition. As shown in the timing diagram, the chip select pin state should always occur while the clock signal is low. The configure (CFG) pin timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers. 13 www.national.com LMH6584/LMH6585 30045009 Timing Diagram for Serial Mode Serial Mode Data Frame (First Two Words) Output 0 Input Address LSB 0 Off = Output 1 On = 0 MSB 1 2 3 4 Off = 1 5 Input Address LSB 6 7 8 9 MSB 10 On = 0 Off = 1 11 TRI-STATE®, Bit 0 is first bit clocked into device. Serial Mode Data Frame (Continued) Output 2 Input Address LSB 12 13 14 15 MSB 16 On = 0 Off = 1 17 Output 3 Input Address LSB 18 19 20 21 MSB 22 On = 0 Off = 1 23 Serial Mode Data Frame (Continued) Output 12 Input Address LSB 72 73 74 75 MSB 76 On = 0 Off = 1 77 Output 13 Input Address LSB 78 79 80 81 MSB 82 On = 0 Off = 1 83 Serial Mode Data Frame (Last Two Words) Output 14 Input Address LSB 84 85 86 87 MSB 88 On = 0 Off = 1 89 Output 15 Input Address LSB 90 91 92 93 MSB 94 On = 0 Off = 1 95 Bit 39 is last bit clocked into device. www.national.com 14 LMH6584/LMH6585 ADDRESSED PROGRAMMING MODE Addressed programming mode makes it possible to change only one output register at a time. To utilize this mode the mode pin must be High. All other pins function the same as in serial programming mode except that the word clocked in is 8 bits and is directed only at the output specified. In addressed mode the data format is shown in the table titled Addressed Mode Word Format. Also illustrated are the timing relationships for the digital pins in the Timing Diagram for Addressed Mode. It is important to note that all the pin timing relationships are important, not just the data and clock pins. One example is that the Chip Select pin (CS) must transition low before the first rising edge of the clock signal. This allows the internal timing circuits to synchronize to allow data to be accepted on the next falling edge. After the final data bit has been clocked in, the chip select pin must go high, then the clock signal must make at least one more low to high transition. As shown in the timing diagram, the Chip Select pin state should always occur while the clock signal is low. The configure (CFG) pin timing is not so critical, but it does need to be kept low until all data has been shifted into the crosspoint registers. 30045010 Timing Diagram for Addressed Mode Addressed Mode Word Format Output Address LSB MSB Input Address LSB MSB TRISTATE 1 = TRISTATE 0 = On 9 0 1 2 3 4 5 6 7 8 Bit 0 is first bit clocked into device. 15 www.national.com LMH6584/LMH6585 DAISY CHAIN OPTION IN SERIAL MODE The LMH6584/LMH6585 support daisy chaining of the serial data stream between multiple chips. This feature is available only in the Serial Programming Mode. To use this feature serial data is clocked into the first chip DIN pin, and the next chip DIN pin is connected to the DOUT pin of the first chip. Both chips may share a Chip Select signal, or the second chip can be enabled separately. When the Chip Select pin goes low on both chips a double length word is clocked into the first chip. As the first word is clocking into the first chip, the second chip is receiving the data that was originally in the shift register of the first chip (invalid data). When a full 96 bits have been clocked into the first chip the next clock cycle begins moving the first frame of the new configuration data into the second chip. With a full 192 clock cycles both chips have valid data and the Chip Select pin of both chips should be brought high to prevent the data from overshooting. A configure pulse will activate the new configuration on both chips simultaneously, or each chip can be configured separately. The mode, Chip Select, configure, and clock pins of both chips can be tied together and driven from the same sources. 30045012 Timing Diagram for Daisy Chain Operation SPECIAL CONTROL PINS should be budgeted 30 mW of power. For a typical application with one video load for each output this would be a total power The LMH6584/LMH6585 have two special control pins that of 2.5W. With a typical θJA of 22°C/W this will result in the function independent of the serial control bus. One of these silicon being 55°C over the ambient temperature. A more agpins is the reset (RST) pin. The RST pin is active high meangressive application would be two video loads per output ing that at a logic 1 level the chip is configured with all outputs which would result in 3W of power dissipation. This would redisabled and in a high impedance state. The RST pin prosult in a 66°C temperature rise. The QFP package thermal grams all the registers with input address 0 and all the outputs performance can be significantly enhanced with an external are turned off. In this configuration the device draws only 40 heat sink and by providing for moving air ventilation. Also, be mA. The reset pin can be used as a shutdown function to resure to calculate the increase in ambient temperature from all duce power consumption. The other special control pin is the devices operating in the system case. Because of the high broadcast (BCST) pin. The BCST pin is also active high and power output of this device, thermal management should be sets all the outputs to the on state connected to input 0. Both considered very early in the design process. Generous pasof these pins are level sensitive and require no clock signal. sive venting and vertical board orientation may avoid the need The two special control pins overwrite the contents of the for fan cooling provided a large heat sink is used. Also, the configuration register. LMH6584/LMH6585 can be operated with a ±3.3V power THERMAL MANAGEMENT supply. This will cut power dissipation substantially while only reducing bandwidth by about 10% (2 VPP output). The The LMH6584/LMH6585 are high performance device that LMH6584/LMH6585 are fully characterized and factory tested produces a significant amount of heat. With a ±5V supply, the at the ±3.3V power supply condition for applications where LMH6584/LMH6585 will dissipate approximately 2W of idling reduced power is desired. power with all outputs enabled. Idling power is calculated based on the typical supply current of 200 mA and a 10V The recommended heat sink is AAVD/Thermalloy part # supply voltage. This power dissipation will vary within the 375024B60024G. This heat sink is designed to be used with range of 1.8W to 2.2W due to process variations. In addition, solder anchors #125700D00000G. This heat sink is larger each equivalent video load (150Ω) connected to the outputs then the LMH6584/LMH6585 package in order to provide www.national.com 16 LMH6584/LMH6585 maximum heat dissipation, a smaller heat sink can be selected if forced air circulation will be used. With natural convection the heat sink will reduce the θJA from 22°C/W to approximately 11°C/W. Using a fan will increase the effectiveness of the heat sink considerably by reducing θJA to approximately 5°C/W. When doing thermal design it is important to note that everything from board layout to case material and case venting will impact the actual θJA of the total system. The θJA specified in the datasheet is for a typical board layout with external case enclosing the board. PRINTED CIRCUIT LAYOUT Generally, a good high frequency layout will keep power supply and ground traces away from the input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and possible circuit oscillations (see Application Note OA-15 for more information). If digital control lines must cross analog signal lines (particularly inputs) it is best if they cross perpendicularly. National Semiconductor suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization National Semiconductor offers an evaluation board which can be found on the LMH6584 and LMH6585 Product Folder. 30045053 FIGURE 6. Maximum Dissipation vs. Ambient Temperature 17 www.national.com LMH6584/LMH6585 Physical Dimensions inches (millimeters) unless otherwise noted 144-Pin LQFP NS Package Number VNG144C www.national.com 18 LMH6584/LMH6585 Notes 19 www.national.com LMH6584/LMH6585 32x16 400 MHz Analog Crosspoint Switches, Gain of 1, Gain of 2 Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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