LMH6704MF

LMH6704 650 MHz Selectable Gain Buffer with Disable September 2006 LMH6704 650 MHz Selectable Gain Buffer with Disable General Description The LMH™6704 is a very wideband, DC coupled selectable gain buffer designed specifically for wide dynamic range systems requiring exceptional signal fidelity. The LMH6704 includes on chip feedback and gain set resistors, simplifying PCB layout while providing user selectable gains of +1, +2 and −1 V/V. The LMH6704 provides a disable pin, which places the amplifier in a high output impedance, low power mode. The Disable pin may be allowed to float high. With a 650 MHz Small Signal Bandwidth (AV = +1), full power gain flatness to 200 MHz, and excellent Differential Gain and Phase, the LMH6704 is optimized for video applications. High resolution video systems will benefit from the LMH6704’s ability to drive multiple video loads at low levels of differential gain or differential phase distortion. The LMH6704 is constructed with National’s proprietary high speed complementary bipolar process using National’s proven current feedback circuit architectures. It is available in 8-Pin SOIC and 6-Pin SOT23 packages. Features n Wideband operation 650 MHz — AV = +1, VO = 0.5 VPP 450 MHz — AV = +2, VO = 0.5 VPP 400 MHz — AV = +2, VO = 2 VPP ± 90 mA n High output current n Very low distortion — 2nd/3rd harmonics (10 MHz, RL = 100Ω): −62/−78 — Differential gain/Differential phase: 0.02%/0.02˚ n Low noise 2.3nV/ n High slew rate 3000 V/µs n Supply current 11.5 mA Applications n n n n n n HDTV, NTSC & PAL video systems Video switching and distribution ADC driver DAC buffer RGB driver High speed multiplexer Connection Diagram 8-Pin SOIC 6-Pin SOT23 20103634 Top View 20103613 Top View Ordering Information Package 8-Pin SOIC 6-Pin SOT23 Part Number LMH6704MA LMH6704MAX LMH6704MF LMH6704MFX Package Marking LMH6704MA B07A Transport Media 95 Units Rail 2.5k Units Tape and Reel 1k Units Tape and Reel 3k Units Tape and Reel NSC Drawing M08A MF06A LMH™ is a trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS201036 www.national.com LMH6704 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 4) Human Body Model Machine Model Supply Voltage IOUT Common-Mode Input Voltage Maximum Junction Temperature Storage Temperature Range 2000V 200V 13.5V (Note 3) VS− to VS+ 150˚C −65˚C to 150˚C Soldering Information Infrared or Convection (20 sec.) Wave Soldering (10 sec.) Lead Temp. (soldering 10 sec.) 235˚C 260˚C 300˚C Operating Ratings (Note 1) Nominal Supply Voltage Temperature Range (Note 8) Thermal Resistance Package 8-Pin SOIC 6-Pin SOT23 (θJC) 75˚C/W 120˚C/W (θJA) 160˚C/W 187˚C/W ± 4V to ± 6V −40˚C to 85˚C Electrical Characteristics (Note 2) TA = +25˚C , AV = +2, VS = ± 5V, RL = 100Ω; unless specified. Symbol Parameter Conditions Min (Note 6) Typ (Note 6) 650 450 400 200 3000 0.9 10 −62 −52 −78 −65 −65 10.5 9.3 10.5 3 RL = 150Ω, f = 4.43 MHz RL = 150Ω, f = 4.43 MHz 1.98 1.96 −1 −2 2 35 Non-Inverting (Note 7) Inverting −5 5 .02 0.02 2.00 2.02 2.04 +1 +2 pA/ % deg V/V % mV µV/˚C AV = +2 AV = +1 AV = −1 INN DG DP AV Non-Inverting Input Noise Current Differential Gain Differential Phase Gain Gain Error VIO DVIO IBN IBI Input Offset Voltage Input Offset Voltage Average Drift Input Bias Current Input Bias Current MHz V/µs ns ns MHz Max (Note 6) Units Dynamic Performance SSBW SSBW LSBW GF0.1dB SR TRS/TRL ts HD2L HD2H HD3L HD3H IMD VN Two-Tone Intermodulation Output Noise Voltage 3rd Harmonic Distortion 0.1 dB Gain Bandwidth Slew Rate Rise and Fall Time (10% to 90%) Settling Time to 0.1% 2nd Harmonic Distortion -3 dB Bandwidth VOUT = 0.5 VPP, AV = +1 VOUT = 0.5 VPP VOUT = 2 VPP VOUT = 2 VPP VOUT = 4 VPP, 40% to 60% (Note 5) 2V Step 2V Step VOUT = 2.0 VPP, f = 10 MHz VOUT = 2.0 VPP, f = 40 MHz VOUT = 2.0 VPP, f = 10 MHz VOUT = 2.0 VPP, f = 40 MHz f = 10 MHz, POUT = 10 dBm/tone f = 100 kHz Distortion and Noise Response dBc dBc dBc nV/ Static, DC Performance ±7 ± 8.3 ± 15 ± 18 ± 22 ± 31 µA www.national.com 2 LMH6704 Electrical Characteristics (Note 2) Symbol CMIR PSRR VO Parameter Common Mode Input Range Power Supply Rejection Ratio Output Voltage Swing (Continued) TA = +25˚C , AV = +2, VS = ± 5V, RL = 100Ω; unless specified. Conditions VIO ≤ 15 mV DC RL = ∞ RL = 100Ω Min (Note 6) Typ (Note 6) Max (Note 6) Units V dB ± 1.9 48 47 ±2 52 IO IS Linear Output Current Supply Current (Enabled) Supply Current (Disabled) VOUT ≤ 80 mV DIS = 2V, RL = ∞ DIS = 0.8V, RL = ∞ ± 3.3 ± 3.18 ± 3.2 ± 3.12 ± 55 ± 3.5 ± 3.5 ± 90 11.5 0.25 12.5 13.7 0.9 0.925 563 V mA mA R F & RG ROUT RIN+ CIN+ TON TOFF VIH VIL IIH IIL IOZ Internal RF and RG Closed Loop Output Resistance Input Resistance Input Capacitance Enable Time Disable Time Output Glitch Enable Voltage Disable Voltage Disable Input Bias Current, High Disable Input Bias Current, Low Disabled Output Leakage Current DIS ≥ VIH DIS ≤ VIL DIS = V+, (Note 7) DIS = 0V (Note 7) AV = +1, VOUT = ± 1.8V DC 375 465 0.05 1 1 10 10 50 Ω Ω MΩ pF ns ns mVPP V Enable/Disable Performance (Disabled Low) 2.0 0.8 −1 0 −100 0.2 ± 50 −350 µA µA µA ± 25 ± 50 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Min/Max ratings are based on production testing unless otherwise specified. Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations. Note 4: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 5: Slew Rate is the average of the rising and falling edges. Note 6: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 7: Negative current implies current flowing out of the device. Note 8: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board. 3 www.national.com LMH6704 Typical Performance Characteristics Unless Specified). Small Signal Frequency Response vs. Gain (TA = 25˚C, VS = ± 5V, RL = 100Ω, AV = +2, VOUT = 0.5 VPP; Frequency Response vs. VOUT 20103614 20103615 Small Signal Frequency Response vs. RLOAD Large Signal Gain Flatness 20103616 20103617 Small Signal Frequency Response vs. Capacitive Load Series Output Isolation Resistance vs. Capacitive Load 20103618 20103619 www.national.com 4 LMH6704 Typical Performance Characteristics (TA = 25˚C, VS = ±5V, RL = 100Ω, AV = +2, VOUT = 0.5 VPP; Unless Specified). (Continued) Large Signal Pulse Response Small Signal Pulse Response 20103620 20103621 Harmonic Distortion vs. Frequency Harmonic Distortion vs. Load 20103622 20103623 Harmonic Distortion vs. Output Voltage DG/DP 20103624 20103633 5 www.national.com LMH6704 Typical Performance Characteristics (TA = 25˚C, VS = ±5V, RL = 100Ω, AV = +2, VOUT = 0.5 VPP; Unless Specified). (Continued) PSRR vs. Frequency DC Errors vs. Temperature (A Typical Unit, (Note 7)) 20103628 20103629 Disable Timing Disable Output Glitch 20103630 20103631 www.national.com 6 LMH6704 Application Information GENERAL INFORMATION The LMH6704 is a high speed current feedback Selectable Gain Buffer (SGB), optimized for very high speed and low distortion. With its internal feedback and gain-setting resistors the LMH6704 offers excellent AC performance while simplifying board layout and minimizing the affects of layout related parasitic components. The LMH6704 has no internal ground reference so single or split supply configurations are both equally useful. SETTING THE CLOSED LOOP GAIN The LMH6704 is a current feedback amplifier with on-chip RF = RG = 465Ω. As such it can be configured with an AV = +2, AV = +1, or an AV = −1 by connecting pins 3 and 4 as described in the chart below. 20103603 GAIN AV FIGURE 1. Recommended Gain of +2 Circuit −1 V/V +1 V/V +2 V/V Input Connections Non-Inverting (Pin 3) Inverting (Pin 4) Ground Input Signal Input Signal Input Signal NC (Open) Ground The gain accuracy of the LMH6704 is accurate and guaranteed over temperature to within ± 1%. The internal gain setting resistors, RFand RG, match very well. The LMH6704 architecture takes advantage of the fact that the internal gain setting resistors track each other well over a wide range of temperature and process variation to keep the overall gain constant, despite the fact that the individual resistors have nominal temperature drifts. Therefore, using external resistors in series with RG to change the gain will result in poor gain accuracy over temperature. 20103604 FIGURE 2. Recommended Gain of +1 Circuit 20103609 FIGURE 4. Alternate Unity Gain Configuration 20103605 FIGURE 3. Recommended Gain of −1 Circuit 7 www.national.com LMH6704 Application Information UNITY GAIN COMPENSATION (Continued) With a current feedback Selectable Gain Buffer like the LMH6704, the feedback resistor is a compromise between the value needed for stability at unity gain and the optimized value needed at a gain of two. In standard open-loop current feedback operational amplifiers the feedback resistor, RF, is external and its value can be adjusted to match the required gain. Since the feedback resistor is integrated in the LMH6704, it is not possible to adjust it’s value. However, we can employ the circuit shown in Figure 4. This circuit modifies the noise gain of the amplifier to eliminate the peaking associated with using the circuit shown in Figure 2. The frequency response is shown in Figure 5. The decreased peaking does come at a price as the output referred voltage noise density increases by a factor of 1.1. For example, if an AV = +2 configuration is used with a source impedance of 37.5Ω (parallel combination of 75Ω source and 75Ω termination impedances), where “IBN” is and the output referred voltage noise (exclud18.5pA/ ing non-inverting input noise current) can be found in Table 1 below. The total noise (EO) at the output can be calculated as: TABLE 1. Measured Output Noise Voltage Gain (AV) +2 +1 +1, alternate method shown in Figure 4 -1 Note: f ≥ 100 kHz Output Referred Voltage Noise (nV/ ), excluding non-inverting noise current 10.5 9.3 10.5 10.5 ENABLE/DISABLE 20103632 FIGURE 5. Unity Gain Frequency Response OUTPUT VOLTAGE NOISE Open-loop operational amplifiers specify three input referred noise parameters: input voltage noise, non-inverting input current noise, and inverting input current noise. These specifications are used to calculate the total voltage noise produced at the output of the amplifier. The LMH6704 is a closed loop amplifier with internal resistors, thus only the non-inverting input current noise flows through external components. All other noise sources are internal to the part. There are four possible values for the noise at the output depending on the gain configuration as shown in Table 1. For more information on calculating noise in current feedback amplifiers see Application Notes OA-12 and AN104 available at www.national.com. The total noise voltage at the output can be calculated using the following formula: 20103612 FIGURE 6. DIS Pin Simplified Schematic The LMH6704 has a TTL logic compatible disable function. Apply a logic low ( < .8V) to the DS pin and the LMH6704 is disabled. Apply a logic high ( > 2.0V), or let the pin float and the LMH6704 is enabled. Voltage, not current, at the Disable pin (DS) determines the enable/disable state. Care must be exercised to prevent the disable pin voltage from going more than .8V below the midpoint of the supply voltages (0V with split supplies, V+/2 with single supply biasing). Doing so could cause transistor Q1 to Zener resulting in damage to the disable circuit (See Figure 6 or the simplified internal schematic diagram). The core amplifier is unaffected by this, but the disable operation could become permanently slower as a result. Disabled, the LMH6704 inputs and output become high impedances. While disabled the LMH6704 quiescent current is 8 www.national.com LMH6704 Application Information (Continued) approximately 250 µA. Because of the pull up resistor on the disable circuit, the ICC and IEE currents (positive and negative supply currents respectively) are not balanced in the disabled state. The positive supply current (ICC) is approximately 350 µA while the negative supply current (IEE) is only 250 µA. The remaining IEE current of 100 µA flows through the disable pin. The disable function can be used to create analog switches or multiplexers. Implement a single analog switch with one LMH6704 positioned between an input and output. Create an analog multiplexer with several LMH6704’s. Use the circuit shown in for multiplexer applications because there is no RG to shunt signals to ground. EVALUATION BOARDS National Semiconductor provides the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization. Many of the datasheet plots were measured with these boards. Device LMH6704MA LMH6704MF Package SOIC-8 SOT23-6 Evaluation Board Part Number CLC730227 CLC730216 ance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller ceramic capacitors should be placed as close to the device as possible. In Figure 1, Figure 2, and Figure 3 CSS is optional, but is recommended for best second order harmonic distortion. Another option to using CSS is to use pairs of 0.01 µF and 0.1 µF ceramic capacitors for each supply bypass. An evaluation board is shipped upon request when a sample order is placed with National Semiconductor. 20103608 FIGURE 8. Typical Video Application VIDEO PERFORMANCE The LMH6704 has been designed to provide excellent performance with production quality video signals in a wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless with DG of 0.02% and DP of 0.02˚. Best performance will be obtained with back terminated loads. The back termination reduces reflections from the transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier output stage. Figure 8 shows a typical configuration for driving a 75Ω Cable. The amplifier is configured for a gain of two to make up for the 6 dB of loss in ROUT. POWER DISSIPATION Follow these steps to determine the Maximum power dissipation for the LMH6704: 1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS), where VS = V+ - V− Calculate the RMS power dissipated in the output stage: PD (rms) = rms ((VS - VOUT)*IOUT), where VOUT and IOUT are the voltage and current across the external load and VS is the total supply current 3. Calculate the total RMS power: PT = PAMP+PD The maximum power that the LMH6704, package can dissipate at a given temperature can be derived with the following equation: 2. 20103606 FIGURE 7. Decoupling Capacitive Loads DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor RISO. Figure 7 shows the use of a series output resistor, RISO, to stabilize the amplifier output under capacitive loading. Capacitive loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. The chart “Suggested RISO vs. Cap Load” gives a recommended value for selecting a series output resistor for mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the frequency response. This gives a good compromise between settling time and bandwidth. For applications where maximum frequency response is needed and some peaking is tolerable, the value of RISO can be reduced slightly from the recommended values. LAYOUT CONSIDERATIONS Whenever questions about layout arise, use the evaluation board as a guide. The CLC730216 is the evaluation board supplied with samples of the LMH6704. To reduce parasitic capacitances ground and power planes should be removed near the input and output pins. For long signal paths controlled impedance lines should be used, along with imped- 9 www.national.com LMH6704 Application Information (Continued) PMAX = (150˚ – TAMB)/ θJA, where TAMB = Ambient temperature (˚C) and θJA = Thermal resistance, from junction to ambient, for a given package (˚C/W). For the SOT23-6 package θJA is 187˚C/W. ESD PROTECTION The LMH6704 is protected against electrostatic discharge (ESD) on all pins. The LMH6704 will survive 2000V Human Body model and 200V Machine model events. Input and Output pins have ESD diodes to either supply pin (V+ and V−) which are reverse biased and essentially have no effect under most normal operating conditions. There are occasions, however, when the ESD diodes will be evident. If the LMH6704 is driven by a large signal while the device is powered down, the ESD diodes might enter forward operating region and conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to inadvertently power up the LMH6704 with a large signal applied to the input pins. Shorting the power pins to each other will prevent the chip from being powered up through the input. www.national.com 10 LMH6704 Physical Dimensions unless otherwise noted inches (millimeters) 8-Pin SOIC NS Package Number M08A 6-Pin SOT23 NS Package Number MF06A 11 www.national.com LMH6704 650 MHz Selectable Gain Buffer with Disable Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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