LMK03000C

LMK03000/LMK03000C/LMK03001/LMK03001C Precision Clock Conditioner with Integrated VCO ADVANCE INFORMATION November 2006 LMK03000/LMK03000C/LMK03001/LMK03001C Precision Clock Conditioner with Integrated VCO General Description The LMK03000/LMK03000C/LMK03001/LMK03001C precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, three LVDS, and five LVPECL clock output distribution blocks. The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through an Input Divider to feed the various clock distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioners come in a 48-pin LLP package and are footprint compatible with other clocking devices in the same family. Features ■ Integrated VCO and Integer-N PLL ■ Two performance grades (12 kHz to 20 MHz) ■ ■ ■ ■ ■ ■ ■ ■ — LMK03000/LMK03001: Less than 800 fs RMS — LMK03000C/LMK03001C: Less than 400 fs RMS Two VCO frequency plans — LMK03000/LMK03000C: 1185 to 1296 MHz — LMK03001/LMK03001C: 1470 to 1570 MHz Clock output frequency range of 1 to 785 MHz 3 LVDS and 5 LVPECL clock outputs Partially integrated loop filter Dedicated divider and delay blocks on each clock output Pin compatible family of clocking devices 3.15 to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) Target Applications ■ ■ ■ ■ ■ ■ ■ Data Converter Clocking SONET/SDH, DSLAM Networking Wireless Infrastructure Medical Test and Measurement Military / Aerospace Functional Block Diagram 20211401 © 2006 National Semiconductor Corporation 202114 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C Connection Diagram 48-Pin LLP Package 20211402 Pin Descriptions Pin # 1, 25 2 Pin Name GND Fout I/O O I I I I O O O O O I I O I O O O O Ground Internal VCO Frequency Output Power Supply MICROWIRE Clock Input MICROWIRE Data Input MICROWIRE Latch Enable Input No Connection to these pins LDO Bypass Global Output Enable Lock Detect and Test Output LVDS Clock Output 0 LVDS Clock Output 1 LVDS Clock Output 2 LVPECL Clock Output 3 Global Clock Output Synchronization Oscillator Clock Input; Must be AC coupled Charge Pump Output Bias Bypass LVPECL Clock Output 4 LVPECL Clock Output 5 LVPECL Clock Output 6 LVPECL Clock Output 7 Die Attach Pad is Ground Description Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, 3, 8, 13, 16, 19, 22, 26, Vcc7, Vcc8, Vcc9, Vcc10, Vcc11, Vcc12, 30, 31, 33, 37, 40, 43, 46 Vcc13, Vcc14 4 5 6 7, 34, 35 9, 10 11 12 14, 15 17, 18 20, 21 23, 24 27 28, 29 32 36 38, 39 41, 42 44, 45 47, 48 DAP CLKuWire DATAuWire LEuWire NC LDObyp1, LDObyp2 GOE LD CLKout0, CLKout0* CLKout1, CLKout1* CLKout2, CLKout2* CLKout3, CLKout3* SYNC* OSCin, OSCin* CPout Bias CLKout4, CLKout4* CLKout5, CLKout5* CLKout6, CLKout6* CLKout7, CLKout7* DAP www.national.com 2 LMK03000/LMK03000C/LMK03001/LMK03001C Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Power Supply Voltage Input Voltage Storage Temperature Range Lead Temperature (solder 4 s) Symbol VCC VIN TSTG TL Ratings -0.3 to 3.6 -0.3 to (VCC + 0.3) -65 to 150 +260 Units V V °C °C Recommended Operating Conditions Parameter Ambient Temperature Power Supply Voltage Symbol TA VCC Min -40 3.15 Typ 25 3.3 Max 85 3.45 Units °C V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only to the test conditions listed. Note 2: This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of >2 kV, a MM-ESD of >200 V, and a CDM-ESD of >1.2 kV. Electrical Characteristics (Vcc = 3.3 V, -40 °C ≤ TA ≤ 85 °C; Differential Inputs/Outputs; except as specified.) Symbol Parameter Conditions Current Consumption Entire device with one LVPECL and one LVDS output operating at 765 MHz in bypass mode (CLKoutX_MUX = Bypass) ICC Power Supply Current Divider Circuitry (CLKoutX_DIV = 4) Each clock output Delay Circuitry (CLKoutX_DLY = 2250 ps) Each clock output ICCPD Power Down Current Reference Oscillator Input Frequency Range Reference Oscillator Input Slew Rate Input voltage for OSCin and OSCin* Phase Detector Frequency VCPout = Vcc/2, PLL_CP_GAIN = 1x ISRCECPout Charge Pump Source Current VCPout = Vcc/2, PLL_CP_GAIN = 4x VCPout = Vcc/2, PLL_CP_GAIN = 16x VCPout = Vcc/2, PLL_CP_GAIN = 32x VCPout = Vcc/2, PLL_CP_GAIN = 1x ISINKCPout Charge Pump Sink Current VCPout = Vcc/2, PLL_CP_GAIN = 4x VCPout = Vcc/2, PLL_CP_GAIN = 16x VCPout = Vcc/2, PLL_CP_GAIN = 32x 100 400 1600 3200 -100 -400 -1600 -3200 μA µA (Note 3) AC coupled; Single ended PLL fCOMP 40 MHz POWERDOWN = 1 Reference Oscillator fOSCin SLEWOSCin VOSCin 1 0.5 0.2 1.6 200 MHz V/ns Vpp Min Typ Max Units 162 9 mA 10 1 mA 3 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C Symbol ICPoutTRI ICPout%MIS Parameter Charge Pump TRI-STATE Current Magnitude of Charge Pump Sink vs. Source Current Mismatch Conditions PLL (Continued) 0.5 V < VCPout < Vcc - 0.5 V VCPout = Vcc / 2 TA = 25°C 0.5 V < VCPout < Vcc - 0.5 V TA = 25°C Min Typ 2 3 Max 10 Units nA % Magnitude of Charge Pump ICPoutVTUNE Current vs. Charge Pump Voltage Variation ICPoutTEMP PN10kHz PN1Hz Magnitude of Charge Pump Current vs. Temperature Variation PLL 1/f Noise at 10 kHz Offset (Note 4) Normalized to 1 GHz Output Frequency Normalized Phase Noise Contribution (Note 5) 4 % 4 PLL_CP_GAIN = 1x PLL_CP_GAIN = 32x PLL_CP_GAIN = 1x PLL_CP_GAIN = 32x VCO LMK03000/LMK03000C LMK03001/LMK03001C After programming R15 for lock, no changes to output configuration are permitted to guarantee continuos lock. (Note 6) LMK03000/LMK03000C; TA = 25 °C LMK03001/LMK03001C; TA = 25 °C 3.3 2.7 7 to 9 1185 1470 -117 -122 -219 -224 1296 1570 % dBc/Hz dBc/Hz fFout VCO Tuning Range MHz |ΔTCL| Allowable Temperature Drift for Continuous Lock 125 °C pFout Output Power to a 50 Ω load driven by Fout dBm KVtune Fine Tuning Sensitivity LMK03000/LMK03000C (The lower sensitivity indicates the typical sensitivity at the lower end of the tuning LMK03001/LMK03001C range, the higher sensitivity at the higher end of the tuning range) LMK03000/LMK03001 12 kHz to 20 MHz bandwidth LMK03000C/LMK03001C 12 kHz to 20 MHz bandwidth 1 kHz Offset LMK03000C fFout = 1296 MHz (Note 7) 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 1 kHz Offset LMK03000C fFout = 1185 MHz (Note 7) 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 1 kHz Offset LMK03001C fFout = 1570 MHz (Note 7) 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 1 kHz Offset LMK03001C fFout = 1470 MHz (Note 7) 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 9 to 11 MHz/V < 800 < 400 TBD -91.4 -116.8 -137.8 -156.9 TBD -93.5 -118.5 -139.4 -158.4 TBD -89.6 -115.2 -136.5 -156.0 TBD -91.6 -116.0 -137.9 -156.2 fs fs JRMSFout Fout RMS Period Jitter L(f)Fout Fout Single Side Band Phase Noise dBc/Hz www.national.com 4 LMK03000/LMK03000C/LMK03001/LMK03001C Symbol Parameter Conditions CLKoutX_MUX = Bypass CLKoutX_MUX = Divided CLKoutX_DIV = 4 Min Typ Max Units Clock Distribution Section (Note 8) - LVDS Clock Outputs (CLKout0 to CLKout2) RL = 100 Ω Input Bus = 785 MHz Bandwidth = 12 kHz to 20 MHz 40 fs 150 JitterADD Additive RMS Jitter (Note 8) tSKEW VOD ΔVOD VOS ΔVOS ISA ISB ISAB CLKoutX to CLKoutY Differential Output Voltage Change in magnitude of VOD for complementary output states Output Offset Voltage Change in magnitude of VOS for complementary output states Clock Output Short Circuit Current single ended Clock Output Short Circuit Current differential Equal loading and identical channel configuration RL = 100 Ω RL = 100 Ω RL = 100 Ω RL = 100 Ω RL = 100 Ω Single ended outputs shorted to GND Complementary outputs tied together -30 250 -35 1.125 -35 -24 -12 ±4 350 30 450 35 ps mV mV V mV mA mA 1.25 1.375 35 24 12 Clock Distribution Section (Note 8) - LVPECL Clock Outputs (CLKout3 to CLKout7) RL = 100 Ω Input Bus = 785 MHz Integration Bandwidth = 12 kHz to 20 MHz CLKoutX_MUX = Bypass CLKoutX_MUX = Divided CLKoutX_DIV = 4 -30 40 fs 150 JitterADD Additive RMS Jitter (Note 8) tSKEW VOH VOL VOD VIH VIL IIH IIL VOH VOL VIH VIL IIH IIL CLKoutX to CLKoutY Equal loading and identical channel configuration Termination = 50 Ω to Vcc - 2 V ±3 Vcc 0.98 30 ps Output High Voltage Output Low Voltage Differential Output Voltage Digital LVTTL Interfaces (Note 9) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Output Voltage Low-Level Output Voltage High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current VIH = Vcc VIL = 0 -1.0 -1.0 VIH = Vcc VIL = 0 IOH = -500 µA IOL = -500 µA Digital MICROWIRE Interfaces (Note 10) 1.6 -1.0 -1.0 Vcc 0.4 2.0 Termination = 50 Ω to Vcc - 2 V 660 V V 965 Vcc 0.8 1.0 1.0 mV V V µA µA V 0.4 Vcc 0.4 1.0 1.0 V V V µA µA Vcc 1.8 810 5 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C Symbol tCS tCH tCWH tCWL tES tCES tEWH Parameter Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Enable Set Up Time Enable to Clock Set Up Time Enable Pulse Width High Conditions MICROWIRE Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing Min 25 8 25 25 25 25 25 Typ Max Units ns ns ns ns ns ns ns Note 3: For all frequencies the slew rate, SLEWOSCin, is measured between 20% and 80%. If only OSCin is being driven (OSCin* AC grounded), the slew rate is half, 0.25 V/ns. Note 4: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker (f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). Note 5: A specification in modeling PLL in-band phase noise is the Normalized Phase Noise Contribution, LPLL_flat(f), of the PLL and is defined as: PN1Hz = LPLL_flat(f) – 20log(N) – 10log(Fcomp). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and Fcomp is the comparison frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). To measure LPLL_flat(f) the offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and flicker noise. Note 6: Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction and stay in lock from the ambient temperature and programmed state at which the device was when register R15 was programmed. The action of programming the R15 register, even to the same value, activates a frequency calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R15 register to ensure that it stays in lock. Regardless of what temperature the part was initially programmed at, the ambient temperature can never drift outside the range of -40 °C ≤ TA ≤ 85 °C without violating specifications. For this specification to be valid the programmed state of the device must not change after R15 is programmed. Note 7: VCO phase noise is measured assuming the VCO is the dominant noise source due to a 75 Hz loop bandwidth. Over frequency, the phase noise typically varies by 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies by 1 to 2 dB, assuming the part is not reloaded. Re-programming R15 will run the frequency calibration routine for optimum phase noise. Note 8: The Clock Distribution Section includes all parts of the device except the PLL and VCO sections. Typical Additive Jitter specifications apply to the clock distribution section only and is in RMS form addition to the jitter from the VCO. Note 9: Applies to GOE, LD, and SYNC*. Note 10: Applies to uWireCLK, uWireDATA, and uWireLE. Serial Data Timing Diagram 20211403 Data bits set on the DATA signal are clocked into a shift register, MSB first, on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift register to the addressed register determined by the LSB bits. After the programming is complete the CLK, DATA, and LE signals should be returned to a low state. www.national.com 6 LMK03000/LMK03000C/LMK03001/LMK03001C Charge Pump Current Specification Definitions 20211431 I1 = Charge Pump Sink Current at VCPout = Vcc - ΔV I2 = Charge Pump Sink Current at VCPout = Vcc/2 I3 = Charge Pump Sink Current at VCPout = ΔV I4 = Charge Pump Source Current at VCPout = Vcc - ΔV I5 = Charge Pump Source Current at VCPout = Vcc/2 I6 = Charge Pump Source Current at VCPout = ΔV ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device. Charge Pump Output Current Magnitude Variation vs. Charge Pump Output Voltage 20211432 Charge Pump Sink Current vs. Charge Pump Output Source Current Mismatch 20211433 Charge Pump Output Current Magnitude Variation vs. Temperature 20211434 7 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C 1.0 Functional Description The LMK03000/LMK03000C/LMK03001/LMK03001C precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, three LVDS, and five LVPECL clock output distribution blocks. The LMK03000 and LMK03001 Standard Grade devices feature jitter performance of less than 800 fs RMS. The LMK03000C and LMK03001C Premium Grade devices each feature jitter performance of less than 400 fs RMS. The devices include internal 3rd and 4th order poles to simplify loop filter design and improve spurious performance. The 1st and 2nd order poles are off-chip to provide flexibility for the design of various loop filter bandwidths. Two VCO frequency plans are available for each performance grade. The LMK03000 and LMK03000C include a 1.24 GHz VCO. The LMK03001 and LMK03001C include a 1.52 GHz VCO. The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through an Input Divider to feed the various clock distribution blocks. Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components. The clock conditioners come in a 48-pin LLP package and are footprint compatible with other clocking devices in the same family. 1.1 BIAS PIN To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is important for low noise performance. 1.2 LDO BYPASS To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor. 1.3 OSCILLATOR INPUT PORT (OSCin, OSCin*) The purpose of OSCin is to provide the PLL with a reference signal. The OSCin port may be driven single endedly by AC grounding OSCin* with a 0.1 µF capacitor. 1.4 LOW NOISE, FULLY INTEGRATED VCO The LMK03000/LMK03000C/LMK03001/LMK03001C devices contain a fully integrated VCO. In order for proper operation the VCO uses a frequency calibration algorithm. The frequency calibration algorithm is activated any time that the R15 register is programmed. Once R15 is programmed the temperature may not drift more than the maximum allowable drift for continuous lock, ΔTCL, or else the VCO is not guaranteed to stay in lock. For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15 is programmed. 1.5 CLKout DELAYS Each individual clock output includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a 150 ps step size and range from 0 to 2250 ps of total delay. 1.6 LVDS/LVPECL OUTPUTS Each LVDS or LVPECL output may be disabled individually by programming the CLKoutX_EN bits. All the outputs may be disabled simultaneously by pulling the GOE pin low or programming EN_CLKout_Global to 0. 1.7 GLOBAL CLOCK OUTPUT SYNCHRONIZATION The SYNC* synchronizes the clock outputs. When SYNC* is held in a logic low state, the outputs are also held in a logic low state. When SYNC* goes high, the clock outputs are activated and will transition to a high state simultaneously. SYNC* must be held low for greater than one clock cycle of the Input Channel Bus. Once this low event has been registered, the outputs will not reflect the low state for four more cycles. Similarly once SYNC* becomes high, the outputs will not simultaneously transition high until four more Input Channel Bus clock cycles have passed. See the timing diagram below for further detail. SYNC* Timing Diagram 20211404 1.8 GLOBAL OUTPUT ENABLE AND LOCK DETECT Each clock output may be individually enabled. Each output enable control bit is gated with the Global Output Enable input pin (GOE) and the Global Output Enable bit (EN_CLKout_Global). The GOE pin provides an internal pull-up. If it is unterminated externally, the clock output states are determined by the Clock Output Enable bits (CLKoutX_EN). All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal or EN_CLKout_Global is set to 0. The Lock Detect (LD) signal can be connected to the GOE pin in which case all outputs are disabled automatically if the synthesizer is not locked. www.national.com 8 LMK03000/LMK03000C/LMK03001/LMK03001C 2.0 General Programming Information The LMK03000/LMK03000C/LMK03001/LMK03001C devices are programmed using sixteen 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0]. During programming LE is low, serial data is clocked in on the rising edge of clock (MSB first). When LE goes high, data is transferred to the register bank selected by the address field. Only registers R0 to R7 and R13 to R15 need to be programmed for proper device operation. For the frequency calibration algorithm to work properly OSCin must be driven by a valid signal when R15 is programmed. 9 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C 2.1 LMK03000/LMK03000C/LMK03001/LMK03001C REGISTER MAP 25 Data [27:0] A3 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A2 1 A1 0 A0 R0 Register CLKout7_EN CLKout6_EN CLKout5_EN CLKout4_EN CLKout3_EN CLKout2_EN CLKout1_EN CLKout0_EN 0 0 0 0 0 www.national.com 31 30 29 28 27 26 0 0 0 0 0 0 0 0 CLKout0 _MUX [1:0] CLKout0_DIV [7:0] CLKout0_DLY [3:0] 0 0 0 0 R1 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout1 _MUX [1:0] CLKout1_DIV [7:0] CLKout1_DLY [3:0] 0 0 0 1 R2 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout2 _MUX [1:0] CLKout2_DIV [7:0] CLKout2_DLY [3:0] 0 0 1 0 10 R3 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout3 _MUX [1:0] CLKout3_DIV [7:0] CLKout3 _DLY [3:0] 0 0 1 1 R4 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout4 _MUX [1:0] CLKout4_DIV [7:0] CLKout4 _DLY [3:0] 0 1 0 0 R5 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout5 _MUX [1:0] CLKout5_DIV [7:0] CLKout5 _DLY [3:0] 0 1 0 1 R6 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout6 _MUX [1:0] CLKout6_DIV [7:0] CLKout6 _DLY [3:0] 0 1 1 0 R7 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKout7 _MUX [1:0] CLKout7_DIV [7:0] CLKout7 _DLY [3:0] 0 1 1 1 R13 Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 0 OSCin_FREQ [7:0] 0 1 VCO_ R4_LF [2:0] 0 VCO_ R3_LF [2:0] VCO_ C3_C4_LF [3:0] 1 EN_Fout R15 EN_CLKout_Global POWERDOWN 0 R14 0 0 0 0 PLL_ MUX [3:0] PLL_R [11:0] 0 0 0 0 1 1 1 0 PLL_ CP_ GAIN [1:0] PLL_N [17:0] 0 INPUT_DIV [3:0] 0 0 0 1 1 1 1 LMK03000/LMK03000C/LMK03001/LMK03001C 11 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C 2.2 REGISTER R0 to R7 Registers R0 through R7 control the eight clock output pins. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. Aside from this, the functions of these bits are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 7. 2.2.1 CLKoutX_MUX[1:0] -- Clock Output Multiplexers These bits control the Clock Output Multiplexer for each pin. Changing between the different modes changes the blocks in the signal path and therefore incurs a delay relative to the bypass mode. The different MUX modes and associated delays are listed below. CLKoutX_MUX[1:0] 0 1 2 3 Mode Bypassed Divided Delayed Divided and Delayed Added Delay Relative to Bypass Mode 0 ps 100 ps 400 ps (In addition to the programmed delay) 500 ps (In addition to the programmed delay) 2.2.2 CLKoutX_DIV[7:0] -- Clock Output Dividers These bits control the clock output divider value. In order for these dividers to be active, the respective CLKoutX_MUX (See 2.2.1) bit must be set to either "Divided" or "Divided and Delayed" mode. After all the dividers are programed, the SYNC* pin must be used to ensure that all edges of the clock output pins are aligned (See 1.7). The Clock Output Dividers follow the Input Divider so the final clock divide for an output is Input Divider x Clock Output Divider. By adding the divider block to the output path a fixed delay of approximately 100 ps is incurred. The actual Clock Output Divide value is twice the binary value programmed as listed in the table below. CLKoutX_DIV[7:0] 0 0 0 0 0 0 . 1 0 0 0 0 0 0 . 1 0 0 0 0 0 0 . 1 0 0 0 0 0 0 . 1 0 0 0 0 0 0 . 1 0 0 0 0 1 1 . 1 0 0 1 1 0 0 . 1 0 1 0 1 0 1 . 1 Clock Output Divider value Invalid 2 4 6 8 10 ... 510 www.national.com 12 LMK03000/LMK03000C/LMK03001/LMK03001C 2.2.3 CLKoutX_DLY[3:0] -- Clock Output Delays These bits control the delay stages for each clock output pin. In order for these delays to be active, the respective CLKoutX_MUX (See 2.2.1) bit must be set to either "Delayed" or "Divided and Delayed" mode. By adding the delay block to the output path a fixed delay of approximately 400 ps is incurred in addition to the delay shown in the table below. CLKoutX_DLY[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2.2.4 CLKoutX_EN bit -- Clock Output Enables This bit controls whether each clock output is enabled or not. If the EN_CLKout_Global bit (See 2.4.4) is set to zero or if GOE pin is held low, all CLKoutX_EN bit states will be ignored and all clock outputs will be disabled. CLKoutX_EN bit Don't care Don't care 0 1 EN_CLKout_Global bit Don't care 0 Don't care 1 GOE pin 0 Don't care Don't care High Clock X Output State Disabled Disabled Disabled Enabled Delay (ps) 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950 2100 2250 13 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C 2.3 REGISTER R13 2.3.1 VCO_C3_C4_LF[3:0] -- Value for Internal Loop Filter Capacitors C3 and C4 These bits control the capacitor values for C3 and C4 in the internal loop filter. VCO_C3_C4_LF[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 to 15 2.3.2 VCO_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 These bits control the R3 resistor value in the internal loop filter. The recommended setting for VCO_R3_LF[2:0] = 0 for optimum phase noise and jitter. VCO_R3_LF[2:0] 0 1 2 3 4 5 to 7 2.3.3 VCO_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 These bits control the R4 resistor value in the internal loop filter. The recommended setting for VCO_R4_LF[2:0] = 0 for optimum phase noise and jitter. VCO_R4_LF[2:0] 0 1 2 3 4 5 to 7 R4 Value (kΩ) Low (< 100 Ω) 10 20 30 40 Invalid R3 Value (kΩ) Low (< 100 Ω) 10 20 30 40 Invalid Loop Filter Capacitors C3 (pF) 0 0 50 0 50 100 0 50 100 100 150 150 Invalid C4 (pF) 10 60 10 110 110 110 160 160 10 60 110 60 www.national.com 14 LMK03000/LMK03000C/LMK03001/LMK03001C 2.3.4 OSCin_FREQ[7:0] -- Oscillator Input Calibration Adjustment These bits are to be programmed to the OSCin frequency. If the OSCin frequency is not an integral multiple of 1 MHz, then round to the closest value. OSCin_FREQ[7:0] 1 2 ... 200 201 to 255 2.4 REGISTER R14 2.4.1 PLL_R[11:0] -- R Divider Value These bits program the PLL R Divider and are programmed in binary fashion. PLL_R[11:0] 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 1 . 1 0 1 0 . 1 PLL R Divide Value Invalid 1 2 ... 4095 OSCin Frequency 1 MHz 2 MHz ... 200 MHz Invalid 2.4.2 PLL_MUX[3:0] -- Multiplexer Control for LD Pin These bits set the output mode of the LD pin. The table below lists several different modes. PLL_MUX[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 to 15 2.4.3 POWERDOWN bit -- Device Power Down This bit can power down the device. Enabling this bit powers down the entire chip and all blocks, regardless of the state of any of the other bits or pins. POWERDOWN bit 0 1 Mode Normal Operation Entire Chip Powered Down Output Type Hi-Z Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull Open Drain NMOS Open Drain PMOS Push-Pull Push-Pull Push-Pull Push-Pull LD Pin Function Disabled Logic High Logic Low Digital Lock Detect (Active High) Digital Lock Detect (Active Low) Analog Lock Detect Analog Lock Detect Analog Lock Detect N Divider Output (Very Low Duty Cycle) N Divider Output/2 (50% Duty Cycle) R Divider Output (Very Low Duty Cycle) R Divider Output/2 (50% Duty Cycle) Invalid 15 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C 2.4.4 EN_CLKout_Global bit -- Global Clock Output Enable This bit overrides the individual CLKoutX_EN bits (See 2.2.4). When this bit is set to 0, all clock outputs are disabled, regardless of the state of any of the other bits or pins. EN_CLKout_Global bit 0 1 2.4.5 EN_Fout bit -- Fout port enable This bit enables the Fout pin. EN_Fout bit 0 1 2.5 Register R15 2.5.1 PLL_N[17:0] -- PLL N Divider These bits program the divide value for the PLL N Divider. The PLL N Divider follows the Input Divider and precedes the PLL phase detector. Since the Input Divider is also in the feedback path from the VCO to the PLL Phase Detector, the total N divide value, NTotal, is also influenced by the Input Divider value. NTotal = PLL N Divider * Input Divider. The VCO frequency is calculated as, fVCO = fOSCin * PLL N Divider * Input Divider / R. Since the PLL N divider is a pure binary counter, there are no illegal divide values for PLL_N[17:0]. PLL_N[17:0] 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 1 . 1 PLL N Divider Value Invalid 1 ... 262143 Fout Pin Status Disabled Enabled Clock Outputs All Disabled Normal Operation 2.5.2 INPUT_DIV[3:0] -- Input Divider These bits program the divide value for the Input Divider. The Input Divider follows the VCO output and precedes the clock distribution blocks. Since the Input Divider is in the feedback path from the VCO to the PLL phase detector the Input Divider contributes to the total N divide value, NTotal. NTotal = PLL N Divider * Input Divider. The Input Divider can not be bypassed. See 2.5.1 (PLL N Divider) for more information on setting the VCO frequency. INPUT_DIV[3:0] 0 0 0 0 0 0 0 0 1 1 . 1 0 0 0 0 1 1 1 1 0 0 . 1 0 0 1 1 0 0 1 1 0 0 . 1 0 1 0 1 0 1 0 1 0 1 . 1 Input Divider Value Invalid Invalid 2 3 4 5 6 7 8 Invalid ... Invalid www.national.com 16 LMK03000/LMK03000C/LMK03001/LMK03001C 2.5.3 PLL_CP_GAIN[1:0] -- PLL Charge Pump Gain These bits set the charge pump gain of the PLL. PLL_CP_GAIN[1:0] 0 1 2 3 Charge Pump Gain 1x 4x 16x 32x 17 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C 3.0 Application Information 3.1 System Level Diagram The following shows the LMK300xx in a typical application. In this setup the clock may be multiplied, reconditioned, and redistributed. The first and second pole of the loop filter are external. The third and fourth poles are integrated. 20211470 3.2 Bias Pin To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is important for low noise performance. 3.3 LDO bypass To properly use the device, bypass LDObyp1 (pin 9) with a 10 µF capacitor and LDObyp2 (pin 10) with a 0.1 µF capacitor. www.national.com 18 LMK03000/LMK03000C/LMK03001/LMK03001C 3.4 Loop Filter The internal charge pump is directly connected to the integrated loop filter components. The first and second pole of the loop filter are externally attached as shown in the diagram below. When the loop filter is designed, it must be stable over the entire frequency band, meaning that the changes in KVtune from the low to high band specification will not make the loop filter unstable. 20211471 19 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C Physical Dimensions inches (millimeters) unless otherwise noted Leadless Leadframe Package (Bottom View) 48 Pin LLP (SQA48A) Package Ordering Information Order Number LMK03000 LMK03000X LMK03001 LMK03001X LMK03000C LMK03000CX LMK03001C LMK03001CX Package Marking K03000 I K03000 I K03001 I K03001 I K03000CI K03000CI K03001CI K03001CI Packing 1000 Unit Tape and Reel 4000 Unit Tape and Reel 1000 Unit Tape and Reel 4000 Unit Tape and Reel 1000 Unit Tape and Reel 4000 Unit Tape and Reel 1000 Unit Tape and Reel 4000 Unit Tape and Reel VCO Version 1.24 GHz 1.24 GHz 1.52 GHz 1.52 GHz 1.24 GHz 1.24 GHz 1.52 GHz 1.52 GHz Performance Grade 800 fs 800 fs 800 fs 800 fs 400 fs 400 fs 400 fs 400 fs LVDS Outputs 3 3 3 3 3 3 3 3 LVPECL Outputs 5 5 5 5 5 5 5 5 www.national.com 20 LMK03000/LMK03000C/LMK03001/LMK03001C Notes 21 www.national.com LMK03000/LMK03000C/LMK03001/LMK03001C Precision Clock Conditioner with Integrated VCO Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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