LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
September 10, 2010
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
1.0 General Description
The LMK04000 family of precision clock conditioners provides low-noise jitter cleaning, clock multiplication and distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Using a cascaded PLLatinum™ architecture combined with an external crystal and varactor diode, the LMK04000 family provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance. The cascaded architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to either work with an external VCXO module or use the integrated crystal oscillator with an external crystal and a varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or crystal used in PLL1. The LMK04000 family features dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a programmable divider, a phase synchronization circuit, a programmable delay, and an LVDS, LVPECL, or LVCMOS output buffer. The default startup clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or microcontroller that programs the jitter cleaner during the system power up sequence.
2.0 Features
■ Cascaded PLLatinum PLL Architecture
— PLL1 ■ Phase detector rate of up to 40 MHz ■ Integrated Low-Noise Crystal Oscillator Circuit ■ Dual redundant input reference clock with LOS — PLL2 ■ Normalized [1 Hz] PLL noise floor of -224 dBc/Hz ■ Phase detector rate up to 100 MHz ■ Input frequency-doubler ■ Integrated Low-Noise VCO Ultra-Low RMS Jitter Performance — 150 fs RMS jitter (12 kHz – 20 MHz) — 200 fs RMS jitter (100 Hz – 20 MHz) LVPECL/2VPECL, LVDS, and LVCMOS outputs Support clock rates up to 1080 MHz Default Clock Output (CLKout2) at power up Five dedicated channel divider and delay blocks Pin compatible family of clocking devices Industrial Temperature Range: -40 to 85 °C 3.15 V to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
■ ■ ■ ■ ■ ■ ■ ■ ■
3.0 Target Applications
■ ■ ■ ■ ■ ■ ■
Data Converter Clocking Wireless Infrastructure Networking, SONET/SDH, DSLAM Medical Military / Aerospace Test and Measurement Video
30027140
PLLatinum™ is a trademark of National Semiconductor Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
300271
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LMK04000 Family
Device Configuration Information NSID LMK04000BISQ LMK04001BISQ LMK04002BISQ LMK04010BISQ LMK04011BISQ LMK04031BISQ LMK04033BISQ NSID LMK04000BISQ LMK04001BISQ LMK04002BISQ LMK04010BISQ LMK04011BISQ LMK04031BISQ LMK04033BISQ PROCESS BiCMOS BiCMOS BiCMOS BiCMOS BiCMOS BiCMOS BiCMOS CLKout0 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL OUTPUTS 3 3 3 5 5 2 2 CLKout1 LVCMOS x 2 LVCMOS x 2 LVCMOS x 2 2 2 CLKout2 LVCMOS x 2 LVCMOS x 2 LVCMOS x 2 2 2 CLKout3 LVDS OUTPUTS LVCMOS OUTPUTS 4 4 4 VCO 1185 to 1296 MHz 1430 to 1570 MHz 1600 to 1750 MHz 1185 to 1296 MHz 1430 to 1570 MHz 1430 to 1570 MHz 1840 to 2160 MHz CLKout4
2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL
2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL 2VPECL / LVPECL LVDS LVDS 2VPECL / LVPECL 2VPECL / LVPECL LVCMOS x 2 LVCMOS x 2 2VPECL / LVPECL 2VPECL / LVPECL LVDS LVDS
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LMK04000 Family
4.0 Functional Block Diagram
30027101
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LMK04000 Family
Table of Contents
1.0 General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Target Applications .......................................................................................................................... 1 4.0 Functional Block Diagram ................................................................................................................. 3 5.0 Connection Diagram ........................................................................................................................ 6 6.0 Pin Descriptions ............................................................................................................................. 7 7.0 Absolute Maximum Ratings .............................................................................................................. 9 8.0 Package Thermal Resistance ............................................................................................................ 9 9.0 Recommended Operating Conditions ................................................................................................ 9 10.0 Electrical Characteristics ............................................................................................................... 10 11.0 Serial Data Timing Diagram .......................................................................................................... 22 12.0 Charge Pump Current Specification Definitions ................................................................................ 22 12.1 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. CHARGE PUMP OUTPUT VOLTAGE ................................................................................................................................ 23 12.2 CHARGE PUMP SINK CURRENT VS. CHARGE PUMP OUTPUT SOURCE CURRENT MISMATCH .............................................................................................................................. 23 12.3 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. TEMPERATURE ................ 23 13.0 Typical Performance Characteristics .............................................................................................. 24 13.1 CLOCK OUTPUT AC CHARACTERISTICS ............................................................................. 24 14.0 Features ..................................................................................................................................... 26 14.1 SYSTEM ARCHITECTURE ................................................................................................... 26 14.2 REDUNDANT REFERENCE INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*) ................................... 26 14.3 PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS) ....................................................................... 26 14.4 INTEGRATED LOOP FILTER POLES ..................................................................................... 26 14.5 CLOCK DISTRIBUTION ....................................................................................................... 26 14.6 CLKout DIVIDE (CLKoutX_DIV, X = 0 to 4) .............................................................................. 26 14.7 CLKout DELAY (CLKoutX_DLY, X = 0 to 4) ............................................................................. 26 14.8 GLOBAL CLOCK OUTPUT SYNCHRONIZATION (SYNC*) ....................................................... 26 14.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT .................................................................... 26 15.0 Functional Description .................................................................................................................. 27 15.1 ARCHITECTURAL OVERVIEW .............................................................................................. 27 15.2 PHASE DETECTOR 1 (PD1) ................................................................................................. 27 15.3 PHASE DETECTOR 2 (PD2) ................................................................................................. 27 15.4 PLL2 FREQUENCY DOUBLER .............................................................................................. 27 15.5 INPUTS / OUTPUTS ............................................................................................................. 27 15.5.1 PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*) .......................................... 27 15.5.2 PLL2 OSCin / OSCin* Port ........................................................................................... 27 15.5.3 CPout1 / CPout2 ........................................................................................................ 27 15.5.4 Fout .......................................................................................................................... 27 15.5.5 Digital Lock Detect 1 Bypass ........................................................................................ 28 15.5.6 Bias .......................................................................................................................... 28 16.0 General Programming Information ................................................................................................. 29 16.1 RECOMMENDED PROGRAMMING SEQUENCE .................................................................... 29 16.2 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET .................................... 32 16.3 REGISTER R0 TO R4 ........................................................................................................... 33 16.3.1 CLKoutX_DIV: Clock Channel Divide Registers .............................................................. 33 16.3.2 EN_CLKoutX: Clock Channel Output Enable .................................................................. 33 16.3.3 CLKoutX_DLY: Clock Channel Phase Delay Adjustment .................................................. 33 16.3.4 CLKoutX/CLKoutX* LVCMOS Mode Control ................................................................... 33 16.3.5 CLKoutX/CLKoutX* LVPECL Mode Control .................................................................... 34 16.3.6 CLKoutX_MUX: Clock Output Mux ................................................................................ 34 16.4 REGISTERS 5, 6 .................................................................................................................. 34 16.5 REGISTER 7 ....................................................................................................................... 34 16.5.1 RESET bit ................................................................................................................. 34 16.6 REGISTERS 8, 9 .................................................................................................................. 34 16.7 REGISTER 10 ..................................................................................................................... 34 16.7.1 RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit ............................................... 34 16.8 REGISTER 11 ..................................................................................................................... 34 16.8.1 CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer Mode Control ...................................... 34 16.8.2 CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits .................. 35 16.8.3 CLKinX_LOS ............................................................................................................. 35 16.8.4 PLL1 Reference Clock LOS Timeout Control .................................................................. 35 16.8.5 LOS Output Type Control ............................................................................................ 35 16.9 REGISTER 12 ..................................................................................................................... 35
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LMK04000 Family
16.9.1 PLL1_N: PLL1_N Counter ........................................................................................... 16.9.2 PLL1_R: PLL1_R Counter ........................................................................................... 16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control (PLL1_CP_POL) ................................................................................................................ 16.10 REGISTER 13 .................................................................................................................... 16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable ......................................................... 16.10.2 EN_Fout: Fout Power Down Bit .................................................................................. 16.10.3 CLK Global Enable: Clock Global enable bit ................................................................. 16.10.4 POWERDOWN Bit -- Device Power Down .................................................................... 16.10.5 EN_PLL2 REF2X: PLL2 Frequency Doubler control bit .................................................. 16.10.6 PLL2 Internal Loop Filter Component Values ................................................................ 16.10.7 PLL1 CP TRI-STATE and PLL2 CP TRI-STATE ............................................................ 16.11 REGISTER 14 .................................................................................................................... 16.11.1 OSCin_FREQ: PLL2 Oscillator Input Frequency Register ............................................... 16.11.2 PLL2_R: PLL2_R Counter .......................................................................................... 16.11.3 PLL_MUX: LD Pin Selectable Output ........................................................................... 16.12 REGISTER 15 .................................................................................................................... 16.12.1 PLL2_N: PLL2_N Counter .......................................................................................... 16.12.2 PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control ................................... 16.12.3 VCO_DIV: PLL2 VCO Divide Register ......................................................................... 17.0 Application Information ................................................................................................................. 17.1 SYSTEM LEVEL DIAGRAM ................................................................................................... 17.2 LDO BYPASS AND BIAS PIN ................................................................................................ 17.3 LOOP FILTER ..................................................................................................................... 17.4 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS ..................................... 17.5 POWER SUPPLY CONDITIONING ........................................................................................ 17.6 THERMAL MANAGEMENT ................................................................................................... 17.7 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) ................................. 17.8 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) ..................................................... 17.8.1 Termination for DC Coupled Differential Operation .......................................................... 17.8.2 Termination for AC Coupled Differential Operation .......................................................... 17.8.3 Termination for Single-Ended Operation ........................................................................ 17.9 DRIVING CLKin AND OSCin INPUTS ..................................................................................... 17.9.1 Driving CLKin Pins with a Differential Source .................................................................. 17.9.2 Driving CLKin Pins with a Single-Ended Source .............................................................. 17.10 ADDITIONAL OUTPUTS WITH AN LMK04000 FAMILY DEVICE .............................................. 17.11 OUTPUT CLOCK PHASE NOISE PERFORMANCE VS. VCXO PHASE NOISE .......................... 18.0 Physical Dimensions .................................................................................................................... 19.0 Ordering Information ....................................................................................................................
35 36 36 36 36 36 36 36 36 36 37 37 37 37 37 38 38 38 38 39 39 40 40 43 43 43 44 47 47 47 48 49 49 49 49 49 53 53
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LMK04000 Family
5.0 Connection Diagram
48-Pin LLP Package
30027102
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LMK04000 Family
6.0 Pin Descriptions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name(s) GND Fout VCC1 CLKuWire DATAuWire LEuWire NC VCC2 LDObyp1 LDObyp2 GOE LD VCC3 CLKout0 CLKout0* DLD_BYP GND VCC4 VCC5 CLKin0 CLKin0* VCC6 CPout1 VCC7 CLKin1 CLKin1* SYNC* OSCin OSCin* VCC8 VCC9 CPout2 VCC10 CLKin0_LOS CLKin1_LOS Bias VCC11 CLKout1 CLKout1* VCC12 O O O O I O I I I I I O I I O O I O PWR ANLG ANLG CMOS CMOS PWR LVDS/LVPECL LVDS/LVPECL ANLG GND PWR PWR ANLG ANLG PWR ANLG PWR ANLG ANLG CMOS ANLG ANLG PWR PWR ANLG PWR LVCMOS LVCMOS ANLG PWR LVPECL/LVCMOS LVPECL/LVCMOS PWR
7
I/O O I I I
Type GND ANLG PWR CMOS CMOS CMOS
Description Ground (For Fout Buffer) VCO Frequency Output Port Power Supply for VCO Output Buffer Microwire Clock Input Microwire Data Input Microwire Latch Enable Input No Connection Power Supply for VCO LDO Bypass, bypassed to ground with 10 µF and 0.1 µF capacitor LDO Bypass, bypassed to ground with a 0.1 µF capacitor Global Output Enable Lock Detect and PLL multiplexer Output Power Supply for CLKout0 Clock Channel 0 Output Clock Channel 0* Output DLD Bypass, bypassed to ground with a 0.1 µF capacitor Ground (Digital) Power Supply for Digital Power Supply for CLKin buffers and PLL1 R-divider Reference Clock Input Port for PLL1 - AC or DC Coupled (Note 1) Reference Clock Input Port for PLL1 (complimentary) - AC or DC Coupled (Note 1) Power Supply for PLL1 Phase Detector and Charge Pump Charge Pump1 Output Power Supply for PLL1 N-Divider Reference Clock Input Port for PLL1 - AC or DC Coupled (Note 1) Reference Clock Input Port for PLL1 (complimentary) - AC or DC Coupled (Note 1) Global Clock Output Synchronization Reference oscillator Input for PLL2 - AC Coupled Reference oscillator Input for PLL2 - AC Coupled Power Supply for OSCin Buffer and PLL2 R-Divider Power Supply for PLL2 Phase Detector and Charge Pump Charge Pump2 Output Power Supply for VCO Divider and PLL2 N-Divider Status of CLKin0 reference clock input Status of CLKin1 reference clock input Bias Bypass. AC coupled with 1 µF capacitor to Vcc1 Power Supply for CLKout1 Clock Channel 1 Output Clock Channel 1* Output Power Supply for CLKout2
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LMK04000 Family
Pin Number 41 42 43 44 45 46 47 48 DAP
Name(s) CLKout2 CLKout2* VCC13 CLKout3 CLKout3* VCC14 CLKout4 CLKout4* DAP
I/O O O O O O O
Type LVPECL/LVCMOS LVPECL/LVCMOS PWR LVPECL LVPECL PWR LVDS/LVPECL LVDS/LVPECL
Description Clock Channel 2 Output Clock Channel 2* Output Power Supply for CLKout3 Clock Channel 3 Output Clock Channel 3* Output Power Supply for CLKout4 Clock Channel 4 Output Clock Channel 4* Output DIE ATTACH PAD, connect to GND
Note 1: The reference clock inputs may be either AC or DC coupled.
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LMK04000 Family
7.0 Absolute Maximum Ratings (Note 2, Note 3, Note 4)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Supply Voltage (Note 5) Input Voltage Storage Temperature Range Lead Temperature (solder 4 sec) Differential Input Current (CLKinX/X*, OSCin/ OSCin*) Symbol VCC VIN TSTG TL IIN Ratings -0.3 to 3.6 -0.3 to (VCC + 0.3) -65 to 150 +260 ±5 Units V V °C °C mA
Note 2: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only to the test conditions listed. Note 3: This device is a high performance RF integrated circuit with an ESD rating up to 8 KV Human Body Model, up to 300 V Machine Model and up to 1,250 V Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations. Note 4: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the operation sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Note 5: Never to exceed 3.6 V.
8.0 Package Thermal Resistance
Package 48-Lead LLP (Note 6) θJA 27.4° C/W θJ-PAD (Thermal Pad) 5.8° C/W
Note 6: Specification assumes 16 thermal vias connect the die attach pad to the embedded copper plane on the 4-layer JEDEC board. These vias play a key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.
9.0 Recommended Operating Conditions
Parameter Ambient Temperature Supply Voltage Symbol TA VCC Condition VCC = 3.3 V Min -40 3.15 Typical 25 3.3 Max 85 3.45 Unit °C V
9
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LMK04000 Family
10.0 Electrical Characteristics
(3.15 V ≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25 °C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.) Symbol ICC_PD Parameter Power Down Supply Current LMK04000, LMK04001, LMK04002 (Note 8) LMK04010, LMK04011 (Note 8) LMK04031, LMK04033 (Note 8) CLKin0/0* and CLKin1/1* Input Clock Specifications fCLKin SLEWCLKin Clock Input Frequency (Note 9) Slew Rate on CLKin (Note 10) Input Voltage Swing, single-ended input Input Voltage Swing, differential input DC offset voltage between CLKinX/CLKinX* |CLKinX-CLKinX*| Manual Select mode Auto-Switching mode 20% to 80% AC coupled to CLKinX; CLKinX* AC coupled to Ground (CLKinX_TYPE=0) CLKinX and CLKinX* are both driven, AC coupled. (CLKinX_TYPE=0) Each pin AC coupled (CLKinX_TYPE=0) 0.001 1 0.15 0.5 400 400 MHz V/ns 380 Conditions Current Consumption 1 435 mA mA Min Typ Max Units
ICC_CLKS
Supply Current with all clocks enabled, all delay bypassed, Fout disabled. (Note 7)
378 335
435 385
0.25
2.0
Vpp
VCLKin (Bipolar input buffer mode)
0.5
3.1
Vpp
VCLKin-offset (Bipolar input buffer mode)
44
mV
VCLKin (MOS input buffer mode)
AC coupled to CLKinX; Input Voltage Swing, singleCLKinX* AC coupled to Ground ended input (CLKinX_TYPE=1) Input Voltage Swing, differential input CLKinX and CLKinX* are both driven, AC coupled. (CLKinX_TYPE=1) DC coupled to CLKinX; CLKinX* AC coupled to Ground (CLKinX_TYPE=1) DC coupled to CLKinX; CLKinX* AC coupled to Ground (CLKinX_TYPE=1) DC offset voltage between CLKinX/CLKinX* |CLKinX-CLKinX*| Each pin AC coupled (CLKinX_TYPE=1)
0.25
2.0
Vpp
0.5
3.1
Vpp
VCLKin- VIH (MOS input buffer mode) VCLKin- VIL (MOS input buffer mode) VCLKin-offset (MOS input buffer mode)
Maximum input voltage
2.0
VCC
V
0.0
0.4
V
294
mV
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LMK04000 Family
Symbol
Parameter PLL1 Phase Detector Frequency
Conditions PLL1 Specifications
Min
Typ
Max
Units
fPD
40 VCPout1 = VCC/2, PLL1_CP_GAIN = 100b VCPout1 = VCC/2, PLL1_CP_GAIN = 101b VCPout1 = VCC/2, PLL1_CP_GAIN = 110b 25 50 100 400 NA NA 20 80 -25 -50 -100 -400 NA NA -20 -80 3 10
MHz
ICPout1 SOURCE
PLL1 Charge Pump Source Current (Note 11)
VCPout1 = VCC/2, PLL1_CP_GAIN = 111b PLL1_CP_GAIN = 000b PLL1_CP_GAIN = 001b VCPout1=VCC/2, PLL1_CP_GAIN = 010b VCPout1=VCC/2, PLL1_CP_GAIN = 011b VCPout1=VCC/2, PLL1_CP_GAIN = 100b VCPout1=VCC/2, PLL1_CP_GAIN = 101b VCPout1=VCC/2, PLL1_CP_GAIN = 110b
µA
ICPout1 SINK
PLL1 Charge Pump Sink Current (Note 11)
VCPout1=VCC/2, PLL1_CP_GAIN = 111b PLL1_CP_GAIN = 000b PLL1_CP_GAIN = 001b VCPout1=VCC/2, PLL1_CP_GAIN = 010b VCPout1=VCC/2, PLL1_CP_GAIN = 011b
µA
ICPout1 %MIS ICPout1VTUNE ICPout1 %TEMP PLL1 ICPout1 TRI
Charge Pump Sink / Source Mismatch Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation Charge Pump Current vs. Temperature Variation Charge Pump TRISTATE®Leakage Current
VCPout1 = VCC/2, T = 25 °C 0.5 V < VCPout1 < VCC - 0.5 V TA = 25 °C
%
4
%
4 0.5 V < VCPout < VCC - 0.5 V 5
% nA
PLL2 Reference Input (OSCin) Specifications fOSCin PLL2 Reference Input (Note 12) PLL2 Reference Clock minimum slew rate on OSCin Input Voltage for OSCin or OSCin* Differential voltage swing EN_PLL2_REF 2X = 0 (Note 13) EN_PLL2_REF 2X = 1 20% to 80% AC coupled; Single-ended (Unused pin AC coupled to GND) AC coupled 0.15 0.5 250 50 V/ns MHz
SLEWOSCin VOSCin (Single-ended) VOSCin (Differential)
0.2 0.4
2.0 3.1
Vpp Vpp
11
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LMK04000 Family
Symbol fXTAL ESR PXTAL CIN
Parameter Crystal Frequency Range Crystal Effective Series Resistance Crystal Power Dissipation (Note 14) Input Capacitance of LMK040xx OSCin port Phase Detector Frequency
Conditions
Min 6
Typ
Max 20 100
Units MHz Ohms µW pF
Crystal Oscillator Mode Specifications
6 MHz < FXTAL < 20 MHz Vectron VXB1 crystal, 12.288 MHz, RESR < 40 Ω -40 to +85 °C 200 6
PLL2 Phase Detector and Charge Pump Specifications fPD 100 VCPout2=VCC/2, PLL2_CP_GAIN = 00b PLL2 Charge Pump Source Current (Note 11) VCPout2=VCC/2, PLL2_CP_GAIN = 01b VCPout2=VCC/2, PLL2_CP_GAIN = 10b VCPout2=VCC/2, PLL2_CP_GAIN = 11b VCPout2=VCC/2, PLL2_CP_GAIN = 00b PLL2 Charge Pump Sink Current (Note 11) VCPout2=VCC/2, PLL2_CP_GAIN = 01b VCPout2=VCC/2, PLL2_CP_GAIN = 10b VCPout2=VCC/2, PLL2_CP_GAIN = 11b ICPout2%MIS ICPout2VTUNE ICPout2%TEMP ICPout2TRI PN10kHz Charge Pump Sink/Source Mismatch Magnitude of Charge Pump Current vs. Charge Pump Voltage Variation Charge Pump Current vs. Temperature Variation Charge Pump Leakage PLL 1/f Noise at 10 kHz offset (Note 15). Normalized to 1 GHz Output Frequency Normalized Phase Noise Contribution (Note 16) 0.5 V < VCPout2 < VCC - 0.5 V PLL2_CP_GAIN = 400 µA PLL2_CP_GAIN = 3200 µA PLL2_CP_GAIN = 400 µA PLL2_CP_GAIN = 3200 µA -117 -122 -219 -224 dBc/Hz VCPout2=VCC/2, TA = 25 °C 0.5 V < VCPout2 < VCC - 0.5 V TA = 25 °C 100 400 µA 1600 3200 -100 -400 µA -1600 -3200 3 10 % MHz
ICPoutSOURCE
ICPoutSINK
4
%
4 10
% nA
PN1Hz
dBc/Hz
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LMK04000 Family
Symbol
Parameter
Conditions Internal VCO Specifications LMK040x0
Min 1185 1430 1600 1840
Typ
Max 1296 1570 1750 2160
Units
fVCO
VCO Tuning Range
LMK040x1 LMK040x2 LMK040x3 LMK040x0, TA = 25 °C, singleended LMK040x1, TA = 25 °C, singleended
MHz
3 3 2 0 -5 7 to 9 8 to 11 9 to 14 MHz/V dBm
PVCO
VCO Output power to a 50 Ω load driven by Fout
LMK040x2, TA = 25 °C, singleended LMK040x3, TA = 25 °C, singleended 1840 MHz LMK040x3, TA = 25 °C, singleended 2160 MHz
KVCO
Fine Tuning Sensitivity (The range displayed in the typical column indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range). Allowable Temperature Drift for Continuous Lock (Note 17)
LMK040x0 LMK040x1 LMK040x2
LMK040x3
14 to 26
|ΔTCL|
After programming R15 for lock, no changes to output configuration are permitted to guarantee continuous lock
125
°C
13
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LMK04000 Family
Symbol
Parameter
Conditions Offset = 1 kHz
Min
Typ -66 -94 -119 -139 -158 -163 -64 -91 -117 -138 -157 -161 -61 -91 -117 -138 -158 -160 -58 -89 -115 -137 -157 -162 -63 -91 -115 -137 -156 -161 -61 -90 -114 -136 -155 -160 -58 -88 -113 -135 -155 -158 -54 -84 -110 -132 -154 -157
Max
Units
Internal VCO Open Loop Phase Noise and Jitter LMK040x0 fVCO = 1185 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 1 kHz LMK040x0 fVCO = 1296 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 1 kHz LMK040x1 fVCO = 1440 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 1 kHz LMK040x1 fVCO = 1560 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout L(f)Fout LMK040x2 fVCO = 1600 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 1 kHz LMK040x2 fVCO = 1750 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 1 kHz LMK040x3 fVCO = 1840 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 1 kHz LMK040x3 fVCO = 2160 MHz SSB Phase Noise PLL2 = Open Loop Measured at Fout Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
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LMK04000 Family
Symbol
Parameter
Conditions Offset = 1 kHz
Min
Typ -111 -119 -121 -133 -157 -162 -165 -110 -117 -120 -132 -156 -160 -163 -111 -118 -120 -132 -156 -162 -165 -107 -114 -117 -126 -152 -156 -160 105 110 100 105 95 100 105 110
Max
Units
Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO Offset = 10kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 40 MHz Offset = 1 kHz LMK040x1 (Note 19) fVCO = 1500 MHz SSB Phase Noise PLL2 = Closed Loop Measured at Fout L(f)Fout LMK040x2 (Note 20) fVCO = 1600 MHz SSB Phase Noise PLL2 = Closed Loop Measured at Fout Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 40 MHz Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 40 MHz Offset = 1 kHz LMK040x3 (Note 21) fVCO = 2000 MHz SSB Phase Noise PLL2 = Closed Loop Measured at Fout Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz Offset = 40 MHz LMK040x0 (Note 18) fVCO = 1200 MHz Integrated RMS Jitter LMK040x1 (Note 19) fVCO = 1500 MHz Integrated RMS Jitter LMK040x2 (Note 20) fVCO = 1600 MHz Integrated RMS Jitter LMK040x3 (Note 21) fVCO = 2000 MHz Integrated RMS Jitter BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz
LMK040x0 (Note 18) fVCO = 1200 MHz SSB Phase Noise PLL2 = Closed Loop Measured at Fout
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
JFout
fs
15
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LMK04000 Family
Symbol
Parameter LMK040x0 (Note 22) fCLKout = 250 MHz SSB Phase Noise Measured at Clock Outputs Value is average for all output types LMK040x1 (Note 23) fCLKout = 250 MHz SSB Phase Noise Measured at Clock Outputs Value is average for all output types LMK040x2 (Note 24) fCLKout = 250 MHz SSB Phase Noise Measured at Clock Outputs Value is average for all output types LMK040x3 (Note 25) fCLKout = 250 MHz SSB Phase Noise Measured at Clock Outputs Value Is average for all output types LMK040x0 (Note 22) fCLKout = 250 MHz Integrated RMS Jitter LMK040x1 (Note 23) fCLKout = 250 MHz Integrated RMS Jitter LMK040x2 (Note 24) fCLKout = 250 MHz Integrated RMS Jitter LMK040x3 (Note 25) fCLKout = 250 MHz Integrated RMS Jitter LMK040x0 (Note 22) fCLKout = 250 MHz Integrated RMS Jitter LMK040x1 (Note 23) fCLKout = 250 MHz Integrated RMS Jitter LMK040x2 (Note 24) fCLKout = 250 MHz Integrated RMS Jitter LMK040x3 (Note 25) fCLKout = 250 MHz Integrated RMS Jitter
Conditions Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz
Min
Typ -125 -130 -132 -148 -157 -126 -133 -136 -147 -156 -127 -133 -134 -145 -157 -125 -132 -135 -145 -156 130 135 115 120 130 135 125 130 140 145 110 115 130 135 120 125
Max
Units
CLKout's Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO
L(f)CLKout
dBc/Hz
JCLKout LVPECL/2VPECL/LVDS
fs
JCLKout LVCMOS
fs
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16
LMK04000 Family
Symbol
Parameter LMK040x0 (Note 26, Note 30) fCLKout = 250 MHz Integrated RMS Jitter LMK040x1 (Note 27, Note 30) fCLKout = 250 MHz Integrated RMS Jitter LMK040x2 (Note 28, Note 30) fCLKout = 250 MHz Integrated RMS Jitter LMK040x3 (Note 29, Note 30) fCLKout = 250 MHz Integrated RMS Jitter LMK040x1 (Note 27) fCLKout = 250 MHz Integrated RMS Jitter LMK040x3 (Note 29) fCLKout = 250 MHz Integrated RMS Jitter LMK040x0 (Note 26) fCLKout = 250 MHz Integrated RMS Jitter LMK040x1 (Note 27) fCLKout = 250 MHz Integrated RMS Jitter LMK040x2 (Note 28) fCLKout = 250 MHz Integrated RMS Jitter LMK040x3 (Note 29) fCLKout = 250 MHz Integrated RMS Jitter
Conditions BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz
Min
Typ 140 185 130 190 150 190 145 200 130 190 145 200 150 190 125 185 150 190 145 195
Max 200
Units
CLKout's Internal VCO Closed Loop Jitter Specifications using a Commercial Quality VCXO
200
JCLKout LVPECL/2VPECL
200
fs
200
JCLKout LVDS
fs
JCLKout LVCMOS
fs
17
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LMK04000 Family
Symbol
Parameter LMK040x0 (Note 31) fCLKout = 245.76 MHz Integrated RMS Jitter LMK040x1 (Note 32) fCLKout = 245.76 MHz Integrated RMS Jitter LMK040x2 (Note 33) fCLKout = 245.76 MHz Integrated RMS Jitter LMK040x3 (Note 34) fCLKout = 245.76 MHz Integrated RMS Jitter LMK040x0 (Note 31) fCLKout = 245.76 MHz Integrated RMS Jitter LMK040x1 (Note 32) fCLKout = 245.76 MHz Integrated RMS Jitter LMK040x2 (Note 33) fCLKout = 245.76 MHz Integrated RMS Jitter LMK040x3 (Note 34) fCLKout = 245.76 MHz Integrated RMS Jitter
Conditions BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz BW = 12 kHz to 20 MHz BW = 100 Hz to 20 MHz
Min
Typ 190 230 200 230 195 230 245 260 195 230 195 220 195 230 240 260
Max
Units
CLKout's Internal VCO Closed Loop Jitter Specifications using the Integrated Low Noise Crystal Oscillator Circuit
JCLKout LVPECL/2VPECL/LVDS
fs
JCLKout LVCMOS
fs
Symbol VIH VIL IIH IIL VIH VIL IIH IIL VOH VOL
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Output Voltage Low-Level Output Voltage
Conditions
Min 1.6
Typ
Max VCC 0.4 25 5.0 VCC 0.4 5.0 5.0
Units V V µA µA V V µA µA V
Digital Inputs (CLKuWire, DATAuWire, LEuWire)
VIH = VCC VIL = 0
-5 -5.0 1.6
Digital Inputs (GOE, SYNC*)
VIH = VCC VIL = 0 IOH = -500 µA IOL = 500 µA
-5.0 -40.0 VCC - 0.4
Digital Outputs (CLKinX_LOS, LD) 0.4 V
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18
LMK04000 Family
Symbol
Parameter
Conditions CLKout2, LM040x0
Min
Typ 50 62 68 81
Max
Units
Default Power On Reset Clock Output Frequency Default output clock frequency at device power on CLKout2, LM040x1 CLKout2, LM040x2 CLKout2, LM040x3 LVDS Clock Outputs (CLKoutX) fCLKout TSKEW VOD ΔVOD VOS ΔVOS ISA ISB ISAB Maximum Frequency (Note 35) CLKoutX to CLKoutY (Note 36) Differential Output Voltage Change in Magnitude of VOD for complementary output states Output Offset Voltage Change in VOS for complementary output states R = 100 Ω differential termination, AC coupled to receiver input, FCLK = 800 MHz, T = 25 °C RL = 100 Ω LVDS-LVDS, T = 25 °C, FCLK = 800 MHz, RL= 100 Ω 250 -50 1.125 1.25 350 1080 30 450 50 1.375 35 -24 -12 24 12 MHz ps mV mV V |mV| mA mA
fCLKout-startup
MHz
Output short circuit current - Single-ended output shorted to single ended GND, T = 25 °C Output short circuit current differential Maximum Frequency (Note 35) CLKoutX to CLKoutY (Note 36) LVPECL-to-LVPECL, T = 25 °C, FCLK = 800 MHz, each output terminated with 120 Ω to GND. FCLK = 100 MHz, T = 25 °C Termination = 50 Ω to VCC - 2 V Complimentary outputs tied together
LVPECL Clock Outputs (CLKoutX) (Note 37) fCLKout 1080 MHz
TSKEW
40
ps
VOH VOL VOD
Output High Voltage Output Low Voltage Output Voltage
VCC 0.93 VCC 1.82 660 890 965
V V mV
2VPECL Clock Outputs (CLKoutX) fCLKout Maximum Frequency (Note 35) CLKoutX to CLKoutY (Note 36) Output High Voltage Output Low Voltage Output Voltage 2VPECL-2VPECL, T=25 °C, FCLK = 800 MHz, each output terminated with 120 Ω to GND. FCLK = 100 MHz, T = 25 °C Termination = 50 Ω to VCC - 2 V 800 VCC 0.95 VCC 1.98 1030 1200 V V mV 1080 MHz
TSKEW
40
ps
VOH VOL VOD
19
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LMK04000 Family
Symbol fCLKout VOH VOL IOH IOL TSKEW
Parameter Maximum Frequency Output High Voltage Output Low Voltage Output High Current (Source) Output Low Current (Sink) Skew between any two LVCMOS outputs, same channel or different channel Output Duty Cycle Output Rise Time Output Fall Time
Conditions 5 pF Load 1 mA Load 1 mA Load VCC = 3.3 V, VO = 1.65 V VCC = 3.3 V, VO = 1.65 V RL = 50 Ω, CL = 10 pF, T = 25 °C, FCLK = 100 MHz. (Note 36) VCC/2 to VCC/2, FCLK = 100 MHz, T = 25 °C (Note 38) 20% to 80%, RL = 50 Ω, CL = 5 pF 80% to 20%, RL = 50 Ω, CL = 5 pF Mixed Clock Skew Same device, T = 25 °C, 250 MHz Same device, T = 25 °C, 250 MHz Same device, T = 25 °C, 250 MHz See Microwire Input Timing See Microwire Input Timing See Microwire Input Timing See Microwire Input Timing See Microwire Input Timing See Microwire Input Timing
Min 250 VCC - 0.1
Typ
Max
Units MHz V
LVCMOS Clock Outputs (CLKoutX)
0.1 28 28 100
V mA mA ps
DUTYCLK TR TF
45
50 400 400
55
% ps ps
LVPECL to LVDS skew TSKEW ChanX - ChanY LVDS to LVCMOS skew LVCMOS to LVPECL skew
-230 770 -540
ps ps ps
Microwire Interface Timing TCS TCH TCWH TCWL TES TEW Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Latch Enable Set Up Time Load Enable Pulse Width 25 8 25 25 25 25 ns ns ns ns ns ns
Note 7: Load conditions for output clocks: LVPECL: 50 Ω to VCC-2 V. 2VPECL: 50 Ω to VCC-2.36 V. LVDS: 100 Ω differential. LVCMOS: 10 pF. Note 8: Additional test conditions for ICC limits: All clock delays disabled, CLKoutX_DIV = 510, PLL1 and PLL2 locked. (See Table 31 for more information) Note 9: CLKin0 and CLKin1 maximum of 400 MHz is guaranteed by characterization, production tested at 200 MHz. Note 10: In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs. Note 11: This parameter is programmable Note 12: FOSCin maximum frequency guaranteed by characterization. Production tested at 200 MHz. Note 13: The EN_PLL2_REF2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path. Note 14: See Application Section discussion of Crystal Power Dissipation. Note 15: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, LPLL_flicker(f), which is dominant close to the carrier. Flicker noise has a 10 dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = LPLL_flicker(10 kHz) - 20log(Fout / 1 GHz), where LPLL_flicker (f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure LPLL_flicker(f) it is important to be on the 10 dB/decade slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat(f). Note 16: A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, LPLL_flat(f), is defined as: PN1HZ=LPLL_flat (f)-20log(N)-10log(fCOMP). LPLL_flat(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and fCOMP is the phase detector frequency of the synthesizer. LPLL_flat(f) contributes to the total noise, L(f). Note 17: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications.
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LMK04000 Family
Note 18: For LMK040x0, fVCO = 1200 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. Note 19: For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. Note 20: For LMK040x2, fVCO = 1600 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 8, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 252 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. Note 21: For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. Note 22: For LMK040x0, fVCO = 1250 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 251 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF. Note 23: For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 2. CLKout_DLY = OFF. Note 24: For LMK040x2, fVCO = 1750 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 354 kHz, PM = 73°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = Bypass. CLKout_DLY = OFF. Note 25: For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW = 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz. CLKoutX_DIV = 4. CLKout_DLY = OFF. Note 26: For LMK040x0, FVCO = 1250 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 5, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 254 kHz, PM = 81°. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. Note 27: For LMK040x1, FVCO = 1500 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 271 kHz, PM = 80°. CLKDIST parameters: CLKoutX_DIV = 2, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. Note 28: For LMK040x2, FVCO = 1750 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 7, N2 = 5, R2 = 2, FDET = 50 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 360 kHz, PM = 79°. CLKDIST parameters: CLKoutX_DIV = Bypass, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. Note 29: For LMK040x3, FVCO = 2000 MHz. PLL1 parameters: FDET = 1 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 100 MHz VCXO drives the OSCin input of PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, LBW = 445 kHz, PM = 76°. CLKDIST parameters: CLKoutX_DIV = 4, CLKout_DLY = OFF. VCXO phase noise: 100 Hz: -100 dBc/Hz; 1 kHz: -128 dBc/Hz; 10 kHz: -144 dBc/Hz; 100 kHz: -147 dBc/Hz. Note 30: Max jitter specification applies to CH3 (LVPECL) output and guaranteed by test in production. Note 31: For LMK040x0, FVCO = 1228.8 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Vectron crystal (model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 5, N2 = 10, EN_PLL2_REF2X = 1, FDET = 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 109 kHz, PM = 43°, CLKoutX_DIV = 2, CLKout_DLY = OFF. Note 32: For LMK040x1, FVCO = 1474.56 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Ecliptek crystal (model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 3, N2 = 20, EN_PLL2_REF2X = 1, FDET = 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 103 kHz, PM = 44°, CLKoutX_DIV = 2, CLKout_DLY = OFF. Note 33: For LMK040x2, FVCO = 1720.32 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Vectron crystal (model: VXB1-1127-12M288000) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 7, N2 = 10, EN_PLL2_REF2X = 1, FDET = 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 120 kHz, PM = 40°, CLKoutX_DIV = 2, CLKout_DLY = OFF. Note 34: For LMK040x3, FVCO = 1966.08 MHz. PLL1 parameters: FDET = 1.024 MHz, ICP1 = 100 µA, loop bandwidth = 20 Hz. A 12.288 MHz Ecliptek crystal (model: ECX-6465) and tuning circuitry is used with on-chip XO circuitry. PLL2 parameters: VCO_DIV = 4, N2 = 20, EN_PLL2_REF2X = 1, FDET = 24.576 MHz, ICP2 = 3.2 mA, C1 = 0 pF, C2 = 12 nF, R2 = 1.8 kΩ, R3 = 600 Ω, R4 = 10 kΩ, C3 = 150 pF, C4 = 60 pF, LBW = 91 kHz, PM = 47°, CLKoutX_DIV = 2, CLKout_DLY = OFF. Note 35: For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to ½ of a period, or, 0.5/FCLKoutX. Note 36: Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for delay mode. Note 37: LVPECL/2VPECL is programmable for all NSIDs. Note 38: Guaranteed by characterization.
21
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LMK04000 Family
11.0 Serial Data Timing Diagram
30027103
Register programming information on the DATAuWire pin is clocked into a shift register on each rising edge of the CLKuWire signal. On the rising edge of the LEuWire signal, the register is sent from the shift register to the register addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the CLKuWire, DATAuWire, and LEuWire signals should be returned to a low state. If the CLKuWire or DATAuWire lines are toggled while the VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this programming.
12.0 Charge Pump Current Specification Definitions
30027131
I1 = Charge Pump Sink Current at VCPout = VCC - ΔV I2 = Charge Pump Sink Current at VCPout = VCC/2 I3 = Charge Pump Sink Current at VCPout = ΔV I4 = Charge Pump Source Current at VCPout = VCC - ΔV I5 = Charge Pump Source Current at VCPout = VCC/2 I6 = Charge Pump Source Current at VCPout = ΔV
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LMK04000 Family
ΔV = Voltage offset from the positive and negative supply rails. Defined to be 0.5 V for this device. 12.1 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. CHARGE PUMP OUTPUT VOLTAGE
30027132
12.2 CHARGE PUMP SINK CURRENT VS. CHARGE PUMP OUTPUT SOURCE CURRENT MISMATCH
30027133
12.3 CHARGE PUMP OUTPUT CURRENT MAGNITUDE VARIATION VS. TEMPERATURE
30027134
23
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LMK04000 Family
13.0 Typical Performance Characteristics
13.1 CLOCK OUTPUT AC CHARACTERISTICS LVDS VOD vs. Frequency LVPECL VOD vs. Frequency
30027146
30027144
LVCMOS Vpp vs. Frequency
Typical Dynamic ICC, LVCMOS Driver, VCC = 3.3 V, Temp = 25 °C, CL= 5 pF
30027145 30027162
Clock Channel Delay Noise Floor vs. Frequency (Note 40)
Clock Output Noise Floor vs. Frequency (Note 39)
30027149
30027148
Note 39: To estimate this noise, only the output frequency is required. Divide value and input frequency are not relevant. Note 40: The noise of the delay block is independent of output type and only applies if the delay is enabled. The noise floor, due to the distribution section accounting for the delay noise, can be calculated as: Total Output Noise = 10 x log(10Output Buffer Noise/10 + 10Delay Noise Floor/10).
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LMK04000 Family
13.1 Clock Output AC Characteristics (continued) Typical LVDS Phase Noise, FCLK = 250 MHz, RMS Jitter = 192 fs (100 Hz to 20 MHz) (Note 41)
30027141
Typical LVPECL Phase Noise, FCLK = 250 MHz, RMS Jitter = 196 fs (100 Hz to 20 MHz) (Note 41)
30027142
Typical LVCMOS Phase Noise, FCLK = 250 MHz, RMS Jitter = 188 fs (100 Hz to 20 MHz) (Note 41)
30027143
Note 41: Reference clock = 10 MHz, PLL1_R = 10, PLL1_N = 100, PLL1_CP_GAIN = 100 µA, PLL1 Loop BW = 20 Hz, VCXO = 100 MHz Crystek CVPD-920-100, PLL2_R = 2, PLL2_N = 10, PLL2_CP_GAIN = 1600 µA, PLL2 Loop BW = 137 kHz, fVCO = 1500 MHz, VCO_DIV = 3, CLKoutX_DIV = 2, CLK_DLY = OFF.
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LMK04000 Family
14.0 Features
14.1 SYSTEM ARCHITECTURE The cascaded PLL architecture of the LMK040xx was chosen to provide the lowest jitter performance over the widest range of output frequencies and phase noise offset frequencies. The first stage PLL (PLL1) is used in conjunction with an external reference clock and an external VCXO to provide a frequency accurate, low phase noise reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated along its path or from other circuits. The “cleaned” reference clock frequency accuracy is combined with the low phase noise of an external VCXO to provide the reference input to PLL2. The low phase noise reference provided to PLL2 allows it to use wider loop bandwidths (50 kHz to 200 kHz). The chosen loop bandwidth for PLL2 should take best advantage of the superior high offset frequency phase noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO for PLL2. Ultra low jitter is achieved by allowing the external VCXO’s phase noise to dominate the final output phase noise at low offset frequencies and the internal VCO’s phase noise to dominate the final output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance. 14.2 REDUNDANT REFERENCE INPUTS (CLKin0/ CLKin0*, CLKin1/CLKin1*) The LMK040xx has two LVDS/LVPECL/LVCMOS compatible reference clock inputs for PLL1, CLKin0 and CLKin1. The selection of the preferred input may be fixed to either CLKin0 or CLKin1, or may be configured to employ one of two automatic switching modes when redundant clock signals are present. The PLL1 reference clock input buffers may also be individually configured as either a CMOS buffered input or a bipolar buffered input. 14.3 PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS) When either of the two auto-switching modes is selected for the reference clock input mode, the signal status of the selected reference clock input is indicated by the state of the CLKinX_LOS (loss-of-signal) output. These outputs may be configured as either CMOS (active HIGH on loss-of-signal), NMOS open-drain or PMOS open-drain. If PLL1 was originally locked and then both reference clocks go away, then the frequency accuracy of the LMK04000 device will be set by the absolute tuning range of the VCXO used on PLL1. The absolute tuning range of the VCXO can be determined by multiplying its' tuning constant by the charge pump voltage. 14.4 INTEGRATED LOOP FILTER POLES The LMK040xx features programmable 3rd and 4th order loop filter poles for PLL2. When enabled, internal resistors and capacitor values may be selected from a fixed range of values to achieve either 3rd or 4th order loop filter response. These programmable components compliment external components mounted near the chip. 14.5 CLOCK DISTRIBUTION The LMK040xx features a clock distribution block with a minimum of five outputs that are a mixture of LVPECL, 2VPECL, LVDS, and LVCMOS. The exact combination is determined by the part number. The 2VPECL is a National Semiconductor proprietary configuration that produces a 2 Vpp differential
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swing for compatibility with many data converters. More than five outputs may be available for device versions that offer dual LVCMOS outputs. 14.6 CLKout DIVIDE (CLKoutX_DIV, X = 0 to 4) Each individual clock distribution channel includes a channel divider. The range of divide values is 2 to 510, in steps of 2. “Bypass” mode operates as a divide-by-1. 14.7 CLKout DELAY (CLKoutX_DLY, X = 0 to 4) Each individual clock distribution channel includes a delay adjustment. Clock output delay registers (CLKoutX_DLY) support a nominal 150 ps step size and range from 0 to 2250 ps of total delay. 14.8 GLOBAL CLOCK OUTPUT SYNCHRONIZATION (SYNC*) The SYNC* input is used to synchronize the active clock outputs. When SYNC* is held in a logic low state, the outputs are also held in a logic low state. When SYNC* goes high, the clock outputs are activated and will transition to a high state simultaneously with one another. SYNC* must be held low for greater than one clock cycle of the Clock Distribution Path. After this low event has been registered, the outputs will not reflect the low state for four more cycles. Similarly after SYNC* becomes high, the outputs will simultaneously transition high after four Clock Distribution Path cycles have passed. See Figure 1 for further detail.
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FIGURE 1. Clock Output synchronization using the SYNC* pin 14.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT Each Clock Output Channel may be either enabled or put into a high impedance state via the Clock Output Enable control bit (one for each channel). Each output enable control bit is gated with the Global Output Enable input pin (GOE). The GOE pin provides an internal pull-up so that if it is un-terminated externally, then the clock output states are determined by the Clock Channel Output Enable Register bits. All clock outputs can be disabled simultaneously if the GOE pin is pulled low by an external signal. TABLE 1. Clock Output Control CLKoutX _EN bit 1 Don't care 0 1 EN_CLKout _Global bit 1 0 Don't care 1 GOE pin Low Don't care Don't care High / No Connect CLKoutX Output State Low Off Off Enabled
LMK04000 Family
The Lock Detect (LD) signal can be connected to the GOE pin in which case all outputs are disabled automatically if the synthesizer is not locked. See Section 16.3.2 EN_CLKoutX: Clock Channel Output Enable and also Section 17.1 SYSTEM LEVEL DIAGRAM for actual implementation details. The Lock Detect (LD) pin can be programmed to output a ‘High’ when both PLL1 and PLL2 are locked, or only when PLL1 is locked or only when PLL2 is locked.
through the PLL2_R counter. The maximum phase comparison frequency of the PLL2 phase detector is 100 MHz, so the input to the frequency doubler is limited to a maximum of 50 MHz. The frequency doubler feature allows the phase comparison frequency to be increased when a relative low frequency oscillator is driving the OSCin port. By doubling the PLL2 phase comparison frequency, the in-band PLL2 noise is reduced by about 3 dB. 15.5 INPUTS / OUTPUTS 15.5.1 PLL1 Reference Inputs (CLKin0 / CLKin0*, CLKin1 / CLKin1*) The reference clock inputs for PLL1 may be selected from either CLKin0 and CLKin1. The user has the capability to manually select one of the two inputs or to configure an automatic switching mode operation. A detailed description of this function is described in the uWire programming section of this data sheet. 15.5.2 PLL2 OSCin / OSCin* Port The feedback from the external oscillator being locked with PLL1 is injected to the PLL2 OSCin/OSCin* pins. This input may be driven with either a single- ended or differential signal. If operated in single ended mode, the unused input should be tied to GND with a 0.1 µF capacitor. Either AC or DC coupling is acceptable. Internal to the chip, this signal is routed to the PLL1_N Counter and to the reference input for PLL2. The internal circuitry of the OSCin port also supports the optional implementation of a crystal based oscillator circuit. A crystal, varactor diode and a small number of other external components may be used to implement the oscillator. The internal oscillator circuit is enabled by setting the EN_PLL2_XTAL bit. 15.5.3 CPout1 / CPout2 The CPout1 pin provides the charge pump current output to drive the loop filter for PLL1. This loop filter should be configured so that the total loop bandwidth for PLL1 is less than 200 Hz. When combined with an external oscillator that has low phase noise at offsets close to the carrier, PLL1 generates a reference for PLL2 that is frequency locked to the PLL1 reference clock but has the phase noise performance of the oscillator. The CPout2 pin provides the charge pump current output to drive the loop filter for PLL2. This loop filter should be configured so that the total loop bandwidth for PLL2 is in the range of 50 kHz to 200 kHz. See the section on uWire device control for a description of the charge pump current gain control. 15.5.4 Fout The buffered output of the internal VCO is available at the Fout pin. This is a single-ended output (sinusoid). Each time the PLL2_N counter value is updated via the uWire interface, an internal algorithm is triggered that optimizes the VCO performance.
15.0 Functional Description
15.1 ARCHITECTURAL OVERVIEW The LMK040xx chip consists of two high performance synthesizer blocks (Phase Locked Loop, internal VCO/VCO Divider, and loop filter), source selection, distribution system, and independent clock output channels. The Phase Frequency Detector in PLL1 compares the divided (R Divider 1) system clock signal from the selected CLKinX and CLKinX* input with the divided (N Divider 1) output of the external VCXO attached to the PLL2 OSCin port. The external loop filter for PLL1 should be narrow to provide an ultra clean reference clock from the external VCXO to the OSCin/OSCin* pins for PLL2. The Phase Frequency Detector in PLL2 then compares the divided (R Divider 2) reference signal from the PLL2 OSCin port with the divided (N Divider 2 and VCO Divider) output of the internal VCO. The bandwidth of the external loop filter for PLL2 should be designed to be wide enough to take advantage of the low in-band phase noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is passed through a common VCO divider block and placed on a distribution path for the clock distribution section. It is also routed to the PLL2_N counter. Each clock output channel allows the user to select a path with a programmable divider block, a phase synchronization circuit, a programmable delay, and LVDS/LVPECL/2VPECL/LVCMOS compatible output buffers. 15.2 PHASE DETECTOR 1 (PD1) Phase Detector 1 in PLL1 (PD1) can operate up to 40 MHz. Since a narrow loop bandwidth should be used for PLL1, the need to operate at high phase detector rate to lower the inband phase noise becomes unnecessary. 15.3 PHASE DETECTOR 2 (PD2) Phase Detector 2 in PLL2 (PD2) supports a maximum comparison rate of 100 MHz, though the actual maximum frequency at the input port (PLL2 OSCin/OSCin*) is 250 MHz. Operating at highest possible phase detector rate will ensure low in-band phase noise for PLL2 which in turn produces lower total jitter, as the in-band phase noise from the reference input and PLL are proportional to N2. 15.4 PLL2 FREQUENCY DOUBLER The PLL2 reference input at the OSCin port may be optionally routed through a frequency doubler function rather than
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LMK04000 Family
15.5.5 Digital Lock Detect 1 Bypass The VCO coarse tuning algorithm requires a stable OSCin clock (reference clock to PLL2) to frequency calibrate the internal VCO correctly. In order to ensure a stable OSCin clock, the first PLL must achieve lock status. A digital lock detect is used in PLL1 to monitor its lock status. After lock is achieved by PLL1, the coarse tuning circuitry is enabled and frequency calibration for the internal VCO begins.
The (DLD_BYP) pin is provided to allow an external bypass cap to be connected to the digital lock detect 1. This capacitor will eliminate potential glitches at initial startup of PLL1 due to unknown phase relationships between the Ncntr1 and Rcntr1. 15.5.6 Bias Proper bypassing of this pin by a 1 µF capacitor connected to VCC is important for low noise performance.
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LMK04000 Family
16.0 General Programming Information
LMK040xx devices are programmed using several 32-bit registers. Each register consists of a 4-bit address field and 28bit data field. The address field is formed by bits 0 through 3 (LSBs) and the data field is formed by bits 4 through 31 (MSBs). The contents of each register are clocked in MSB first (bit
31), and the LSB (bit 0) last. During programming, the LE signal should be held LOW. The serial data is clocked in on the rising edge of the CLK signal. After the LSB (bit 0) is clocked in the LE signal should be toggled LOW-to-HIGH-to-LOW to latch the contents into the register selected in the address field. Registers R0-R4, R7, and R8-R15 must be programmed in order to achieve proper device operation. Figure 2 illustrates the serial data timing sequence.
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FIGURE 2. uWire Timing Diagram To achieve proper frequency calibration, the OSCin port must be driven with a valid signal before programming Register 15. Changes to PLL2_R Counter or the OSCin port signal require Register 15 to be reloaded in order to activate the frequency calibration process. 16.1 RECOMMENDED PROGRAMMING SEQUENCE The recommended programming sequence involves programming R7 with the reset bit set to 1 (Reg. 7, bit 4) to ensure the device is in a default state. If R7 is programmed again, the reset bit should be set to 0. Registers are programmed in order with R15 being the last register programmed. An example programming sequence is shown below: • Program R7 with the RESET bit = 1 (b4 = 1). This ensures that the device is configured with default settings. When RESET = 1, all other R7 bits are ignored. - If R7 is programmed again during the initial configuration of the device, the RESET bit should be cleared (b4 = 0) Program R0 through R4 as necessary to configure the clock outputs as desired. These registers configure clock channel functions such as the channel multiplexer output selection, divide value, delay value, and enable/disable bit. • Program R5 and R6 with the default values shown in the register map on the following pages. • Program R7 with RESET = 0. • Program R8 through R10 with the default values shown in the register map on the following pages. • Program R11 to configure the reference clock inputs (CLKin0 and CLKin1). - type, LOS timeout, LOS type, and mode (manual or autoswitching) • Program R12 to configure PLL1. - Charge pump gain, polarity, R counter and N counter • Program R13 through R15 to configure PLL2 parameters, crystal mode options, and certain globally asserted functions. The following table provides the register map for device programming:
•
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LMK04000 Family
Register Map 25 Data [31:4] A3 24 23 22 21 20 19 18 17 16 1 5 9 8 7 6 5 4 3 2 A2 1 4 1 3 1 2 1 1 1 0 1 A1 0 A0
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EN_CLKout0
R0
EN_CLKout1
CLKout0_PECL_LVL CLKout1_PECL_LVL
R1
Register 0 1 0 0 0 0 CLKout0_ MUX CLKout0_DIV [7:0] CLKout0_DLY [3:0] 0 0 0 1 CLKout1_ MUX [1:0] CLKout1_DIV [7:0] CLKout1_DLY [3:0] 0 0
31
30
29
28
27
26
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
CLKout1B_STATE [1:0] CLKout2B_STATE [1:0] CLKout3B_STATE [1:0]
CLKout1A_STATE [1:0] CLKout2A_STATE [1:0] CLKout3A_STATE [1:0]
30
EN_CLKout2
CLKout2_PECL_LVL
R2
0
0
0
0
0
0
0
1
CLKout2_ MUX [1:0]
CLKout2_DIV [7:0]
CLKout2_DLY [3:0]
0
0
1
0
EN_CLKout3
CLKout3_PECL_LVL
R3
0
0
0
0
0
0
0
1
CLKout3_ MUX [1:0]
CLKout3_DIV [7:0]
CLKout3_DLY [3:0]
0
0
1
1
EN_CLKout4
CLKout4_PECL _LVL
R4
0
0
0
0
0
0
0
1
0
0
0
0
CLKout4_ MUX [1:0]
CLKout4_DIV [7:0]
CLKout4_DLY [3:0]
0
1
0
0
R5 0 RESET 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0
R6
R7
R8
R9
RC_DLD1_Start
R10
R11
Register 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 24 23 22 21 20 19 18 17 16 1 5 9 8 7 6 5 4 3 2 1 0 1 4 1 3 1 2 1 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 1
31
30
29
28
27
26
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CLKin_SEL [1:0]
LOS_TYPE [1:0]
LOS_TIMEOUT [1:0]
CLKin1_BUFTYPE
CLKin0_BUFTYPE
LMK04000 Family
31
PLL1_CP_POL PLL1_R Counter [11:0] EN_Fout EN_PLL2_REF2X PLL2 CP TRI-STATE PLL1 CP TRI-STATE POWER DOWN, default = 0 EN_CLKout_Global, default=1 EN_PLL2_XTAL 1 0 0 0 0 PLL_MUX [4:0] VCO_DIV [3:0]
R12
PLL1_CP_GAI N [2:0]
PLL1_N Counter [11:0]
1
1
0
0
PLL2_C3_C4_LF [3:0]
PLL2_R4_LF [2:0]
PLL2_R3_LF [2:0]
R13
0
0
0
0
1
0
1
1
0
1
R14
0
0
0
OSCin_FREQ [7:0]
PLL2_R Counter [11:0] PLL2_N Counter [17:0]
1 1
1 1
1 1
0 1
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R15
0
0
0
1
PLL2_CP _GAIN [1:0]
LMK04000 Family
16.2 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON/RESET Table 2 illustrates the default register settings programmed in silicon for the LMK040xx after power on or asserting the reset bit. TABLE 2. Default Device Register Settings after Power On/Reset Field Name Default Value (decimal) 0 Default State Field Description Register Bit Location (MSB:LSB) 23
CLKoutX_PECL_LVL
2VPECL disabled This bit sets LVPECL clock level. Valid R0 to R4 when the clock channel is configured as LVPECL/2VPECL; otherwise, not relevant. Inverted Non-Inverted OFF (Note 42) This field sets the state of output B of an LVCMOS Clock channel. This field sets the state of output A of an LVCMOS Clock channel. R1 to R3 R1 to R3
CLKoutXB_STATE CLKoutXA_STATE EN_CLKoutX Reserved Registers RC_DLD1_Start CLKin1_BUFTYPE CLKin0_BUFTYPE LOS_TIMEOUT LOS_TYPE CLKin_SEL PLL1 CP Polarity PLL1_CP_GAIN PLL1_R Counter PLL1_N Counter EN_PLL2_REF2X EN_PLL2_XTAL
0 1 0
22:21 20:19 16 NA 29 11 10 9:8 7:6 5:4 31 30:28 27:16 15:4 16 21
Clock Channel enable bit. Note: The state R0 to R4 of CLKout2 is ON by default. (Note 42) Forces the VCO tuning algorithm state machine to wait until PLL1 is locked. CLKin1 Input Buffer Type CLKin0 Input Buffer Type Selects Lower Reference Clock input frequency for LOS Detection. Selects LOS output type (Note 43) Selects Reference Clock source Selects the charge pump output polarity, i.e., the tuning slope of the external VCXO Sets the PLL1 Charge Pump Gain Sets divide value for PLL1_R Counter Sets divide value for PLL1_N Counter Enables or disables the OSCin frequency doubler path for the PLL2 reference input Enables or Disables internal circuits that support an external crystal driving the OSCin pins Enables or disables the VCO output buffer Global enable or disable for output clocks R5,R6,R8 R9,R10 R10 R11 R11 R11 R11 R11 R12 R12 R12 R12 R13 R13
1 1 1 1 3 0 1 6 1 1 0 0
Enabled MOS mode MOS mode 3 MHz (min.) CMOS CLKin0 Positive polarity 100 µA Divide = 1 Divide = 1 Disabled OFF
EN_Fout CLK Global Enable POWER DOWN PLL2 CP TRI-STATE PLL1 CP TRI-STATE OSCin_FREQ PLL_MUX PLL2_R Counter PLL2_CP_GAIN VCO_DIV PLL2_N Counter
0 1 0 0 0 200 31 1 2 2 1
OFF Enabled
R13 R13 R13 R13 R13 R14 R14 R14 R15 R15 R15
20 18 17 15 14 28:21 20:16 15:4 27:26 25:22 21:4
Disabled (device Device power down control is active) TRI-STATE disabled TRI-STATE disabled 200 MHz Reserved Divide = 1 1600 µA Divide = 2 Divide = 1 Enables or disables TRI-STATE for PLL2 Charge Pump Enables or disables TRI-STATE for PLL1 Charge Pump Source frequency driving OSCin port Selects output routed to LD pin Sets Divide value for PLL2_R Counter Sets PLL2 Charge Pump Gain Sets divide value for VCO output divider Sets PLL2_N Counter value
Note 42: These registers are reserved. The Power On/Reset values for these registers are shown in the register map and should not be changed during programming. Note 43: If the CLKin_SEL value is set to either [0,0] or [0,1], the LOS_TYPE field should be set to [0,0].
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LMK04000 Family
16.3 REGISTER R0 TO R4 Registers R0 through R4 control the five clock outputs. Register R0 controls CLKout0, Register R1 controls CLKout1, and so on. Aside from this, the functions of the bits in these registers are identical. The X in CLKoutX_MUX, CLKoutX_DIV, CLKoutX_DLY, and CLKoutX_EN denote the actual clock output which may be from 0 to 4. 16.3.1 CLKoutX_DIV: Clock Channel Divide Registers Each of the five clock output channels (0 though 4) has a dedicated 8-bit divider followed by a fixed divide by 2 that is used to generate even integer related versions of the distribution path clock frequency (VCO Divider output). If the VCO Divider value is even then the Channel Divider may be bypassed (See CLK Output Mux), giving an effective divisor of 1 while preserving a 50% duty cycle output waveform. TABLE 3. CLKoutX_DIV: Clock Channel Divide Values CLKoutX_DIV [ 7:0 ] b7 b6 b5 b4 b3 b2 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 -1 0 0 0 0 1 1 1 b1 0 0 1 1 0 0 1 b0 0 1 0 1 0 1 1 invalid 2 4 6 8 10 510 Total Divide Value
•
When the device is powered on, holding the GOE pin LOW will disable all clock outputs. The device can be programmed while the GOE is held LOW. The state of CLKout2 can be altered during device programming according to the user’s specific application needs. After device configuration is complete, the GOE pin should be set HIGH to enable the active clock channels.
16.3.3 CLKoutX_DLY: Clock Channel Phase Delay Adjustment Each output channel has an output delay register that can be used to introduce a lag relative to the distribution path frequency (VCO Divider output). These registers support a 150 ps stepsize and range from 0 to 2.25 ns of total delay. When the channel phase delay registers are enabled, a nominal fixed delay of 300 ps of delay is incurred in addition to the programmed delay. The Channel Phase Delay Adjustment Registers are 4 bits wide and are programmed as follows: TABLE 5. CLKoutX_DLY: Clock Channel Delay Control Bit Values CLKoutX_DLY [ 3:0 ] b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DELAY (ps) 0 150 300 450 600 750 900 1050 1200 1350 1500 1650 1800 1950 2100 2250
16.3.2 EN_CLKoutX: Clock Channel Output Enable Each Clock Output Channel may be either enabled or disabled via the Clock Output Enable control bits. Each output enable control bit is gated with the Global Output Enable input pin (GOE) and Global Output Enable bit (EN_CLKout_Global). The GOE pin provides an internal pull-up so that if it is unterminated externally, the clock output states are determined by the Clock Output Enable Register bits. All clock outputs can be set to the low state simultaneously if the GOE pin is pulled low by an external signal. If EN_CLKout_Global is programmed to 0 all outputs are turned off. If both GOE and EN_CLKout_Global are low the clock outputs are turned off. TABLE 4. EN_CLKoutX: Clock Channel Output Enable Control Bits BIT NAME EN_CLKout0 EN_CLKout1 EN_CLKout2 EN_CLKout3 EN_CLKout4 BIT = 1 ON ON ON ON ON BIT = 0 OFF OFF OFF OFF OFF All EN_CLKout X = OFF DEFAULT OFF OFF ON OFF OFF -
16.3.4 CLKoutX/CLKoutX* LVCMOS Mode Control For clock outputs that are configured as LVCMOS, the LVCMOS CLKoutX/CLKoutX* outputs can be independently configured by uWire CLKoutXA_STATE and CLKoutXB_STATE bits. The following choices are available for LVCMOS outputs: TABLE 6. CLKoutXA_STATE, CLKoutXB_STATE Control Bits for LVCMOS Modes CLKoutXA_STATE b1 0 0 1 1 b0 0 1 0 1 CLKoutXB_STATE b1 0 0 1 1 b0 0 1 0 1 Inverted Normal Low TRISTATE LVCMOS Modes
EN_CLKout_ According to Global individual channel settings
Note the default state of CLKout2 is ON after power on or RESET assertion. The nominal frequency is 62 MHz (LMK040x1) or 81 MHz (LMK040x3). This is based on a channel divide value of 12 and default VCO_DIV value of 2. If an active CLKout2 at power on is inappropriate for the user’s application, the following method can be employed to shut off CLKout2 during system initialization:
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LMK04000 Family
16.3.5 CLKoutX/CLKoutX* LVPECL Mode Control Clock outputs designated as LVPECL can be configured in one of two possible output levels. The default mode is the common LVPECL swing of 800 mVp-p single-ended (1.6 Vpp differential). A second mode, 2VPECL, can be enabled in which the swing is increased to 1000 mVp-p single-ended (2 Vp-p differential). TABLE 7. LVPECL Output Format Control CLKoutX_PECL_LVL 0 1 Output Format LVPECL (800 mVpp) 2VPECL (1000 mVpp)
TABLE 9. RC_DLD1_Start bit states RC_DLD 1_Start 1 0 Description The PLL2 VCO tuning algorithm trigger is delayed until PLL1 Digital Lock Detect is valid. The PLL2 VCO tuning algorithm runs immediately after any PLL2_N counter update, despite the state of PLL1 Digital Lock Detect.
16.3.6 CLKoutX_MUX: Clock Output Mux The output of each CLKoutX channel pair is controlled by its' channel multiplexer (mux). The mux can select between several signals: bypassed, divided only, divided and delayed, or delayed only. TABLE 8. CLKoutX_MUX: Clock Channel Multiplexer Control Bits CLKout_MUX [1:0] b1 0 0 1 1 b0 0 1 0 1 Bypassed Divided Delayed Divided and Delayed Clock Mode
If the user is unsure of the state of the reference clock input at startup of the LMK040xx device, setting RC_DLD1_Start = 0 will allow PLL2 to tune and lock the internal VCO to the oscillator attached to the OSCin port. This ensures that the active clock outputs will start up at frequencies close to their desired values. The error in clock output frequency will depend on the open loop accuracy of the oscillator driving the OSCin port. The frequency of an active clock output is normally given by:
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If the open loop frequency accuracy of the external oscillator (either a VCXO or crystal based oscillator) is "X" ppm, then the error in the output clock frequency (FCLK error) will be:
16.4 REGISTERS 5, 6 These registers are reserved. These register values should not be modified from the values shown in the register map. 16.5 REGISTER 7 16.5.1 RESET bit This bit is only in register R7. The use of this bit is optional and it should be set to '0' if not used. Setting this bit to a '1' forces all registers to their power on reset condition and therefore automatically clears this bit. 16.6 REGISTERS 8, 9 These registers are reserved. These register values should not be modified from the values shown in the register map. 16.7 REGISTER 10 16.7.1 RC_DLD1_Start: PLL1 Digital Lock Detect Run Control bit This bit is used to control the state machine for the PLL2 VCO tuning algorithm. The following table describes the function of this bit.
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Setting this bit to 0 does not prevent PLL1 from locking the external oscillator to the reference clock input after the latter input becomes valid. 16.8 REGISTER 11 16.8.1 CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer Mode Control The user may choose between one of two input buffer modes for the PLL1 reference clock inputs: either bipolar junction differential or MOS. Both CLKinX and CLKinX* input pins must be AC coupled when driven differentially. In single ended mode, the CLKinX* pin must be coupled to ground through a capacitor. The active CLKinX buffer mode is selected by the CLKinX_TYPE bits programmed via the uWire interface. TABLE 10. PLL1 CLKinX_BUFTYPE Mode Control Bits b1 0 0 1 1 b0 0 1 0 1 CLKin1_TYPE BJT Differential BJT Differential MOS MOS CLKin0_TYPE BJT Differential MOS BJT Differential MOS
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LMK04000 Family
16.8.2 CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits This register allows the user to set the reference clock input that is used to lock PLL1, or to select an auto-switching mode. The automatic switching modes are revertive or non-revertive. In either revertive or non-revertive mode, CLKin0 is the initial default reference source for the auto-switching mode. When revertive mode is active, the switching control logic will always select CLKin0 as the reference if it is active, otherwise it selects CLKin1. When non-revertive mode is active, the switching logic will only switch the reference input if the currently selected input fails. Table 11 illustrates the control modes. Modes [1,0] and [1,1] are the auto-switching modes. The behavior of both modes is tied to the state of the LOS signals for the respective reference clock inputs. If the reference clock inputs are active prior to configuration of the device, then the normal programming sequence described under Section 16.0 General Programming Information can be used without modification. If it cannot be guaranteed that the reference clocks are active prior to device programming, then the device programming sequence should be modified in order to ensure that CLKin0 is selected as the default. Under this scenario, the device should be programmed as described in "General Programming Information", with CLKin_SEL bits programmed to [0,0] in register R11. The other R11 fields for clock type and LOS timeout should be programmed with the appropriate values for the given application. After the reference clock inputs have started, register R11 should be programmed a second time with the CLKin_SEL field modified to the set the desired mode. The clock type field and LOS field values should remain the same. TABLE 11. CLKin_SEL: Reference Clock Selection Bits CLKin_SEL [1:0] b1 0 0 1 b0 0 1 0 Force CLKin0 / CLKin0* as PLL1 reference Force CLKin1 / CLKin1* as PLL1 reference Non-revertive. Auto-switching. CLKin0 is the default reference clock. If CLKin0 fails, CLKin1 is automatically selected if active. If CLKin0 restarts, CLKin1 remains as the selected reference clock unless it fails, then CLKin0 is reselected. Revertive. Auto-switching. CLKin0 is the preferred reference clock and is selected when active. Function
16.8.4 PLL1 Reference Clock LOS Timeout Control This register is used to tune the LOS timeout based upon the frequency of the reference clock input(s). The register value controls the timeout setting for both CLKin0 and CLKin1. The value programmed in the LOS_TIMEOUT register represents the minimum input frequency for which loss of signal can be detected. For example, if the reference input frequency is 12.288 MHz, then either register values (0,0) or (0,1) will result in valid loss of signal detection. If the reference input frequency is 1 MHz, then only the register value (0,0) will result in valid detection of signal loss. TABLE 12. Reference Clock LOS Timeout Control Bits b1 0 0 1 1 b0 0 1 0 1 Corresponding Minimum Input Frequency 1 MHz 3.0 MHz 13 MHz 32 MHz
16.8.5 LOS Output Type Control The output format of the LOS pins may be selected as active CMOS, open drain NMOS and open drain PMOS, as shown in the following table. TABLE 13. Loss of Signal (LOS) Output Pin Format Type LOS_TYPE [1:0] b1 0 0 1 1 b0 0 1 0 1 Reserved NMOS open drain PMOS open drain Active CMOS Functional Description
The LOS output signal is valid only when CLKin_SEL bits are set to either [1,0] or [1,1]. If the CLKin_SEL field is programmed to either of the fixed inputs, [0,0] or [0,1], the LOS_TYPE bits should be set to [0,0]. 16.9 REGISTER 12 16.9.1 PLL1_N: PLL1_N Counter The size of the PLL1_N counter is 12 bits. This counter will support a maximum divide ratio of 4095 and minimum divide ratio of 1. The 12 bit resolution is sufficient to support minimum phase detector frequency resolution of approximately 50 kHz when the VCXO frequency is 200 MHz. For a 200 MHz external VCXO, the minimum phase detector rate will be PDmin = 200 MHz/4095 = 48.84 kHz TABLE 14. PLL1_N Counter Values N [17:0] b11 b10 ... 0 0 0 1 0 0 0 1 b6 0 0 0 . 1 b5 0 0 0 . b4 0 0 0 . b3 0 0 0 . b2 0 0 0 . b1 0 0 1 . b0 0 1 0 . Not Valid 1 2 ... 4095 VALUE
1
1
16.8.3 CLKinX_LOS The CLKin0_LOS and CLKin1_LOS pins indicate the state of the respective PLL1 CLKinX reference input when the CLKin_SEL bits are set set to either [1,0] or [1,1]. The detection logic that determines the state of the reference inputs is sensitive to the frequency of the reference inputs and must be configured to operate with the appropriate frequency range of the reference inputs, as described in the next section.
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16.9.2 PLL1_R: PLL1_R Counter The size of the PLL1_R counter is 12 bits. This counter will support a maximum divide ratio of 4095 and minimum divide ratio of 1. TABLE 15. PLL1_R Counter Values R [11:0] b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 1 . 1 Not Valid 1 ... 4095 VALUE
TABLE 18. EN_PLL2_XTAL: External Crystal Option EN_PLL2_XTAL 0 1 Oscillator Amplifier State OFF ON
16.10.2 EN_Fout: Fout Power Down Bit The EN_Fout bit allows the Fout port to be enabled or disabled. By default EN_Fout = 0. 16.10.3 CLK Global Enable: Clock Global enable bit In addition to the external GOE pin, an internal Register 13 bit (b18) can be used to globally enable/disable the clock outputs via the uWire programming interface. The default value is 1. When CLK Global Enable = 1, the active output clocks are enabled. The active output clocks are disabled if this bit is 0. 16.10.4 POWERDOWN Bit -- Device Power Down This bit can power down the entire device. Enabling this bit powers down the entire device and all functional blocks, regardless of the state of any of the other bits or pins. TABLE 19. Power Down Bit Values POWERDOWN Bit 0 1 Mode Normal Operation Entire device powered down
16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control (PLL1_CP_POL) The Loop Band Width (LBW) on PLL1 should be narrow to suppress the noise from the system or input clocks at CLKinX/ CLKinX* port. This configuration allows the noise of the external VCXO to dominate at low offset frequencies. Given that the noise of the external VCXO is far superior than the noise of PLL1, this setting produces a very clean reference clock to PLL2 at the OSCin port. In order to achieve a LBW as low as 10 Hz at the supported VCXO frequency (1 MHz to 200 MHz), a range of charge pump currents in PLL1 is provided. The table below shows the available current gains. A small charge pump current is required to obtain a narrow LBW at high phase detector rate (small N value). TABLE 16. PLL1 Charge Pump Current Selections (PLL1_CP_GAIN) PLL1_CP_GAIN [2:0] b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 RESERVED RESERVED 20 80 25 50 100 400 PLL1 Charge Pump Current Magnitude (µA)
16.10.5 EN_PLL2 REF2X: PLL2 Frequency Doubler control bit When FOSCin is below 50 MHz, the PLL2 frequency doubler can be enabled by setting EN_PLL2_REF2X = 1. The default value is 0. When EN_PLL2_REF2X = 1, the signal at the OSCin port bypasses the PLL2_R counter and is passed through a frequency doubler circuit. The output of this circuit is then input to the PLL2 phase comparator block. This feature allows the phase comparison frequency to be increased for lower frequency OSCin sources (< 50 MHz), and can be used with either VXCOs or crystals. For instance, when using a pullable crystal of 12.288 MHz to drive the OSCin port, the PLL2 phase comparison frequency is 24.576 MHz when EN_PLL2_REF2X = 1. A higher PLL phase comparison frequency reduces PLL2 in-band phase noise and RMS jitter. The PLL in-band phase noise can be reduced by approximately 2 to 3 dB. The on-chip loop filter typically is enabled to reduce PLL2 reference spurs when EN_PLL2_REF2X is enabled. Suggested values in this case are: R3 = 600 Ω, C3 = 50 pF, R4 = 10 kΩ, C4 = 60 pF. 16.10.6 PLL2 Internal Loop Filter Component Values Internal loop filter components are available for PLL2, enabling the user to implement either 3rd or 4th order loop filters without requiring external components. The user may select from a fixed set of values for both the resistors and capacitors. Internal loop filter resistance values for R3 and R4 can be set individually according to Table 20 and Table 21.
The PLL1_CP_POL bit sets the PLL1 charge pump for operation with a positive or negative slope VCO/VCXO. A positive slope VCO/VCXO increases frequency with increased tuning voltage. A negative slope VCO/VCXO increases frequency with decreased tuning voltage. TABLE 17. PLL1 Charge Pump Polarity Control Bits (PLL1_CP_POL) PLL1_CP_POL 0 1 16.10 REGISTER 13 16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable If an external crystal is being used to implement a discrete VCXO, the internal feedback amplifier must be enabled in order to complete the oscillator circuit.
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DESCRIPTION Negative Slope VCO/VCXO Positive Slope VCO/VCXO
LMK04000 Family
TABLE 20. PLL2 Internal Loop Filter Resistor Values, PLL2_R3_LF PLL2_R3_LF [2:0] b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 < 600 Ω 10 kΩ 20 kΩ 30 kΩ 40 kΩ Invalid Invalid Invalid RESISTANCE
TABLE 23. PLL1 Charge Pump TRI-STATE bit values PLL1 CP TRI-STATE 1 0 Description PLL1 CPout1 is at TRISTATE PLL1 CPout1 is active
TABLE 24. PLL2 Charge Pump TRI-STATE bit values PLL2 CP TRI-STATE 1 0 16.11 REGISTER 14 16.11.1 OSCin_FREQ: PLL2 Oscillator Input Frequency Register The frequency of the PLL2 reference input to the PLL2 Phase Detector (OSCin/OSCin* port) must be programmed in order to support proper operation of the internal VCO tuning algorithm. This is an 8-bit register that sets the frequency to the nearest 1-MHz increment. TABLE 25. OSCin_FREQ Register Values OSCin_FREQ [7:0] b7 0 0 0 1 1 . 1 b6 0 0 0 . 1 1 . 1 b5 0 0 0 . 1 0 . 1 b4 0 0 0 . 1 0 . 1 b3 0 0 0 . 1 1 . 1 b2 0 0 0 . 0 0 . 1 b1 0 0 1 . 1 0 . 1 b0 0 1 0 . 0 1 . 1 Not Valid 1 MHz 2 MHz ... 250 MHz Not Valid . Not Valid VALUE Description PLL2 CPout2 is at TRISTATE PLL2 CPout2 is active
TABLE 21. PLL2 Internal Loop Filter Resistor Values, PLL2_R4_LF PLL2_R4_LF [2:0] b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 < 200 Ω 10 kΩ 20 kΩ 30 kΩ 40 kΩ Invalid Invalid Invalid RESISTANCE
Internal loop filter capacitors for C3 and C4 can be set individually according to the following table. TABLE 22. PLL2 Internal Loop Filter Capacitor Values PLL2_C3_C4_ LF [3:0] b3 b2 b1 b0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C3 = 0, C4 = 10 C3 = 0, C4 = 60 C3 = 50, C4 = 10 C3 = 0, C4 = 110 C3 = 50, C4 = 110 C3 = 100, C4 = 110 C3 = 0, C4 = 160 C3 = 50, C4 = 160 C3 = 100, C4 = 10 C3 = 100, C4 = 60 C3 = 150, C4 = 110 C3 = 150, C4 = 60 Reserved Reserved Reserved Reserved Loop Filter Capacitance (pF)
16.11.2 PLL2_R: PLL2_R Counter The PLL2 R Counter is 12 bits wide. It divides the PLL2 OSCin/OSCin* clock and is connected to the PLL2 Phase Detector. TABLE 26. PLL2_R: PLL2_R Counter Values R [11:0] b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 1 0 0 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 0 . 1 0 1 . 1 Not Valid 1 ... 4095 VALUE
16.10.7 PLL1 CP TRI-STATE and PLL2 CP TRI-STATE The charge pump output of either CPout1 or CPout2 may be placed in a TRI-STATE mode by setting the appropriate PLLx CP TRI-STATE bit.
16.11.3 PLL_MUX: LD Pin Selectable Output The signal appearing on the LD pin is programmable via the uWire interface and provides access to several internal signals which may be valuable for either status monitoring during normal operation or for debugging during the hardware development phase. This pin may be forced to either a HIGH or LOW state, and may also be configured as specified in Table 27.
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TABLE 27. PLL_MUX: LD Pin Selectable Outputs PLL_MUX [4:0] b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 HiZ Logic High Logic Low PLL2 Digital Lock Detect Active High PLL2 Digital Lock Detect Active Low PLL2 Analog Lock Detect Push Pull 1 LD Output
TABLE 28. PLL2_N: PLL2_N Counter Values N [17:0] b17 b16 0 0 0 0 0 0 1 ... ... b6 b5 b4 b3 b2 b1 b0 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 0 . 1 0 0 1 . 1 0 1 0 . 1 Not Valid 1 2 ... 262143 VALUE
0 PLL2 Analog Lock Detect Open Drain NMOS 1 PLL2 Analog Lock Detect Open Drain PMOS 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reserved PLL2_N Divider Output / 2 Reserved PLL2_R Divider Output / 2 Reserved Reserved PLL1 Digital Lock Detect Active LOW Reserved Reserved Reserved Reserved PLL1_N Divider Output / 2 Reserved PLL1_R Divider Output / 2 PLL1 and PLL2 Digital Lock Detect Inverted PLL1 and PLL2 Digital Lock Detect Reserved Reserved Reserved Reserved Reserved Reserved Reserved
16.12.2 PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control The PLL2 charge pump output current level is controlled with the PLL2_CP_GAIN register. The following table presents the charge pump current control values. TABLE 29. PLL2_CP_GAIN: PLL2 Charge Pump Current Selections PLL2_CP_GAIN [1:0] CP_TRI Charge Pump Current (µA) Hi-Z 100 400 1600 3200
b1 X 0 0 1 1
b0 X 0 1 0 1 1 0 0 0 0
0 PLL1 Digital Lock Detect Active HIGH
16.12.3 VCO_DIV: PLL2 VCO Divide Register A divider is provided on the output of the PLL2 VCO to enable a wide range of output clock frequencies. The output of this divider is placed on the input path for the clock distribution section, which feeds each of the individual clock channels. The divider provides integer divide ratios from 2 to 8. TABLE 30. VCO_DIV: PLL2 VCO Divider Values VCO_DIV [3:0] b3 0 0 0 0 0 0 0 0 1 b2 0 0 0 0 1 1 1 1 0 b1 0 0 1 1 0 0 1 1 0 b0 0 1 0 1 0 1 0 1 0 Divide Value Invalid Invalid 2 3 4 5 6 7 8
16.12 REGISTER 15 16.12.1 PLL2_N: PLL2_N Counter The PLL2_N Counter is 18 bits wide. It divides the output of the VCO Divider and is connected to the PLL2 Phase Detector. Each time the PLL2_N Counter value is updated via the uWire interface, an internal algorithm is triggered that optimizes the VCO performance.
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17.0 Application Information
17.1 SYSTEM LEVEL DIAGRAM The following diagram illustrates the typical interconnection of the LMK040xx in a clocking application.
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FIGURE 3. Typical Application
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17.1 System Level Diagram (continued) Figure 3 shows an LMK04000 family device with external circuitry. The primary reference clock input is at CLKin0/0*. A secondary reference clock is driving CLKin1/1*. Both clocks are depicted as AC coupled differential drivers. The VCXO attached to the OSCin/OSCin* port is configured as an AC coupled single-ended driver. Any of the input ports (CLKin0/0*, CLKin1/1*, or OSCin/OSCin*) may be configured as either differential or single-ended. These options are discussed later in the data sheet. The diagram shows an optional connection between the LD pin and GOE. With this arrangement, the LD pin can be programmed to output a lock detect signal that is active HIGH (see Table 27 for optional LD pin outputs). If lock is lost, the LD pin will transition to a LOW, pulling GOE low and causing all clock outputs to be disabled. This scheme should be used only if disabling the clock outputs is desirable when lock is lost. The loop filter for PLL2 consists of three external components that implement two lower order poles, plus optional internal integrated components if 3rd or 4th order poles are needed. The loop filter components for PLL1 must be external components. The VCO output buffer signal that appears at the Fout pin when enabled (EN_Fout = 1) should be AC coupled using a 100 pF capacitor. This output is a single-ended signal by default. If a differential signal is required, a 50 Ω balun may be connected to this pin to convert it to differential. The clock outputs are all AC coupled with 0.1 µF capacitors. CLKout1 and CLKout3 are depicted as LVPECL, with 120 Ω emitter resistors as source termination. However, the output format of the clock channels will vary by device part number, so the designer should use the appropriate source termination for each channel. Later sections of this data sheet illustrate alternative methods for AC coupling, DC coupling and terminating the clock outputs. 17.2 LDO BYPASS AND BIAS PIN The LDObyp1 and LDObyp2 pins should be connected to GND through external capacitors, as shown in the diagram. Furthermore, the Bias pin should be connected to VCC through a 1 µF capacitor in series. 17.3 LOOP FILTER Each PLL of the LMK04000 family requires a dedicated loop filter. The loop filter for PLL1 must be connected to the CPout1
pin. Figure 4 shows a simple 2-pole loop filter. The output of the filter drives an external VCXO module or discrete implementation of a VCXO using a crystal resonator. Higher order loop filters may be implemented using additional external R and C components. It is recommended the loop filter for PLL1 result in a total closed loop bandwidth in the range of 10 Hz to 200 Hz. The design of the loop filter is application specific and highly dependent on parameters such as the phase noise of the reference clock, VCXO phase noise, and phase detector frequency for PLL1. National’s Clock Conditioner Owner’s Manual covers this topic in detail and National’s Clock Design Tool can be used to simulate loop filter designs for both PLLs. These resources may be found: http://www.national.com/timing/. As shown in the diagram, the charge pump for PLL2 is directly connected to the optional internal loop filter components, which are normally used only if either a third or fourth pole is needed. The first and second poles are implemented with external components. The loop must be designed to be stable over the entire application-specific tuning range of the VCO. The designer should note the range of KVCO listed in the table of Electrical Characteristics and how this value can change over the expected range of VCO tuning frequencies. Because loop bandwidth is directly proportional to KVCO, the designer should model and simulate the loop at the expected extremes of the desired tuning range, using the appropriate values for KVCO. When designing with the integrated loop filter of the LMK04000 family, considerations for minimum resistor thermal noise often lead one to the decision to design for the minimum value for integrated resistors, R3 and R4. Both the integrated loop filter resistors and capacitors (C3 and C4) also restrict the maximum loop bandwidth. However, these integrated components do have the advantage that they are closer to the VCO and can therefore filter out some noise and spurs better than external components. For this reason, a common strategy is to minimize the internal loop filter resistors and then design for the largest internal capacitor values that permit a wide enough loop bandwidth. In situations where spurs requirements are very stringent and there is margin on phase noise, it might make sense to design for a loop filter with integrated resistor values larger than their minimum value.
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FIGURE 4. Loop Filter
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TABLE 31. Typical Current Consumption for Selected Functional Blocks Typical ICC (Temp = 25 °C, VCC = 3.3 V) (mA) Power Dissipated in LVPECL/ 2VPECL Emitter Resistors (mW) 50 25 150 250
Block
Condition
Power Dissipated in device (mW)
Entire device, core current REFMUX LOS Low Channel Internal Buffer High Channel Internal Buffer Divide circuitry per output Delay circuitry per output Fout Buffer LVDS Buffer
Single input clock (CLKIN_SEL = 0 or 1); LOS disabled; PLL1 and PLL2 locked; All CLKouts are off; No LVPECL emitter resistors connected Enable auto-switch mode (CLKIN_SEL = 2 or 3) Enable LOS (LOS_TYPE = 1, or 2, or 3) The low channel internal buffer is enabled when CLKout0 is enabled The high channel internal buffer is enabled when one of CLKout1 through CLKout4 is enabled Divider bypassed (CLKout_MUX = 0, 2) Divider enabled, divide = 2 (CLKout_MUX = 1, 3) Divider enabled, divide > 2 (CLKout_MUX = 1, 3) Delay bypassed (CLKout_MUX = 0, 1) Delay enabled, delay < 8 (CLKout_MUX = 2, 3) Delay enabled, delay > 7 (CLKout_MUX = 2, 3) EN_Fout = 1 LVDS buffer, enabled LVPECL/2VPECL buffer (enabled and with 120 Ω emitter resistors)
115 4.3 3.6 10 10 0 5.3 8.5 0 5.8 9.9 14.5 19.3 40 21.7 0 4.5 16 379.5 377.5
380 14 12 33 33 0 17 28 0 19 33 48 64 82 47 0 15 53 1102 996
LVPECL/ 2VPECL Buffer
LVPECL/2VPECL buffer (disabled and with 120 Ω emitter resistors) LVPECL/2VPECL (disabled and with no emitter resistors)
LVCMOS buffer static ICC, CL = 5 pF LVCMOS Buffer LVCMOS buffer dynamic ICC, CL = 5 pF, CLKout = 100 (Note 44) MHz Entire device LMK0400x (Note 45, Note 46) (Single input LMK0401x (Note 45, Note 46) clock LMK0403x (Note 45, Note 46) (CLKIN_SEL = 0 or 1); LOS disabled; PLL1 and PLL2 locked; Fout disabled; All CLKouts are on; No delay); Divide > 2 on each output.
337.1
1012
100
Note 44: Dynamic power dissipation of LVCMOS buffer varies with output frequency and can be found in the LVCMOS dynamic ICC vs frequency plot, as shown in Section 13.1 CLOCK OUTPUT AC CHARACTERISTICS. Total power dissipation of the LVCMOS buffer is the sum of static and dynamic power dissipation. CLKoutXa and CLKoutXb are each considered an LVCMOS buffer. Note 45: Assuming ThetaJ = 27.4 °C/W, the total power dissipated on chip must be less than 40/27.4 = 1450 mW to guarantee a junction temperature is less than 125 °C. Note 46: Worst case power dissipation can be estimated by multiplying typical power dissipation with a factor of 1.2.
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17.4 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS Due to the myriad of possible configurations the following table serves to provide enough information to allow the user to calculate estimated current consumption of the device. Unless otherwise noted VCC = 3.3 V, TA = 25 °C. From Table 31 the current consumption can be calculated in any configuration. For example, the current for the entire device with 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) output in bypassed mode can be calculated by adding up the following blocks: core current, clock buffer, one LVDS output buffer current, and one LVPECL output buffer current. There will also be one LVPECL output drawing emitter current, but some of the power from the current draw is dissipated in the external 120 Ω resistors which doesn't add to the power dissipation budget for the device. If delays or divides are switched in, then the additional current for these stages needs to be added as well. For power dissipated by the device, the total current entering the device is multiplied by the voltage at the device minus the power dissipated in any emitter resistors connected to any of the LVPECL outputs. If no emitter resistors are connected to the LVPECL outputs, this power will be 0 watts. For example, in the case of 1 LVDS (CLKout0) & 1 LVPECL (CLKout1) operating at 3.3 V, we calculate 3.3 V × (115 + 10 + 10 + 19.3 + 40) mA = 3.3 V × 194.3 mA = 641.2 mW. Because the LVPECL output (CLKout1) has the emitter resistors hooked up and the power dissipated by these resistors is 50 mW, the total device power dissipation is 641.2 mW - 50 mW = 591.2 mW. When the LVPECL output is active, ~1.7 V is the average voltage on each output as calculated from the LVPECL VOH & VOL typical specification. Therefore the power dissipated in each emitter resistor is approximately (1.7 V)2 / 120 Ω = 25 mW. When the LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the power dissipated in each emitter resistor is approximately (1.07 V)2 / 120 Ω = 9.5 mW. 17.5 POWER SUPPLY CONDITIONING The recommended technique for power supply management is to connect the power pins for the clock outputs (pins 13, 37, 40, 43, and 46) to a dedicated power plane and connect all other power pins on the device (pins 3, 8, 18, 19, 22, 24, 30, 31, and 33) to a second power plane. Note: the LMK04000 family has internal voltage regulators for the PLL and VCO blocks to provide noise immunity. 17.6 THERMAL MANAGEMENT Power consumption of the LMK04000 family of devices can be high enough to require attention to thermal management.
For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is, as an estimate, TA (ambient temperature) plus device power consumption times θJA should not exceed 125 °C. The package of the device has an exposed pad that provides the primary heat removal path as well as excellent electrical grounding to a printed circuit board. To maximize the removal of heat from the package a thermal land pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package. A recommended land and via pattern is shown in Figure 5. More information on soldering LLP packages can be obtained: http:// www.national.com/analog/packaging/.
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FIGURE 5. Recommended Land and Via Pattern To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the opposite side of the PCB from the device. This copper area may be plated or solder coated to prevent corrosion but should not have conformal coating (if possible), which could provide thermal insulation. The vias shown in Figure 5 should connect these top and bottom copper layers and to the ground layer. These vias act as “heat pipes” to carry the thermal energy away from the device side of the board to where it can be more effectively dissipated.
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FIGURE 6. Reference Design Circuit for Crystal Oscillator Option 17.7 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) The LMK04000 family features supporting circuitry for a discretely implemented oscillator driving the OSCin port pins. Figure 6 illustrates a reference design circuit for a crystal oscillator: This circuit topology represents a parallel resonant mode oscillator design. When selecting a crystal for parallel resonance, the total load capacitance, CL, must be specified. The load capacitance is the sum of the tuning capacitance (CTUNE), the capacitance seen looking into the OSCin port (CIN), and stray capacitance due to PCB parasitics (CSTRAY), and is given by: The nominal input capacitance (CIN) of the LMK04000 family OSCin pins is 6 pF. The stray capacitance (CSTRAY) of the PCB should be minimized by arranging the oscillator circuit layout to achieve trace lengths as short as possible and as narrow as possible trace width (50 Ω characteristic impedance is not required). As an example, assume that CSTRAY is 4 pF. The total load capacitance is nominally:
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CTUNE is provided by the varactor diode shown in Figure 6, Skyworks model SMV1249-074. A dual diode package with common cathode and provides the variable capacitance for tuning. The single diode capacitance ranges from approximately 31 pF at 0.3 V to 3.4 pF at 3 V. The capacitance range of the dual package (anode to anode) is approximately 15.5 pF at 3 V to 1.7 pF at 0.3 V. The desired value of VTUNE applied to the diode should be VCC/2, or 1.65 V for VCC = 3.3 V. The typical performance curve from the data sheet for the SMV1249-074 indicates that the capacitance at this voltage is approximately 6 pF (12 pF/2).
Consequently the load capacitance specification for the crystal in this case should be nominally 14 pF. The 2.2 nF capacitors shown in the circuit are coupling capacitors that block the DC tuning voltage applied by the 4.7 k and 10 k resistors. The value of these coupling capacitors should be large, relative to the value of CTUNE (CC1 = CC2 >> CTUNE), so that CTUNE becomes the dominant capacitance. For a specific value of CL, the corresponding resonant frequency (FL) of the parallel resonant mode circuit is:
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FS = Series resonant frequency C1 = Motional capacitance of the crystal
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CL = Load capacitance C0 = Shunt capacitance of the crystal, specified on the crystal datasheet
The normalized tuning range of the circuit is closely approximated by:
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CL1, CL2 = The endpoints of the circuit’s load capacitance range, assuming a variable capacitance element is one component of the load. FCL1, FCL2 = parallel resonant frequencies at the extremes of the circuit’s load capacitance range. A common range for the pullability ratio, C0/C1, is 250 to 280. The ratio of the load capacitance to the shunt capacitance is ~(n * 1000), n < 10. Hence, picking a crystal with a smaller
pullability ratio supports a wider tuning range because this allows the scale factors related to the load capacitance to dominate. Examples of the phase noise and jitter performance of the LMK04031 with a crystal oscillator are shown in Table 32. This table illustrates the clock output phase noise when a 12.288 MHz crystal is paired with PLL1.
TABLE 32. Example RMS Jitter and Clock Output Phase Noise for LMK04031 with a 12.288 MHz Crystal Driving OSCin (T = 25 °C, VCC = 3.3 V) (Note 47) RMS Jitter (ps) Integration Bandwidth Clock Output Type PLL2 PDF = 12.288 MHz (EN_PLL2_REF2X = 0) FCLK = 122.88 MHz 100 Hz – 20 MHz LVPECL LVCMOS LVDS 10 kHz – 20 MHz LVPECL LVCMOS LVDS Offset Clock Output Type 0.279 0.244 0.272 0.251 0.211 0.236 Phase Noise (dBc/Hz) PLL2 FPD = 12.288 MHz (EN_PLL2_REF2X = 0) FCLK = 122.88 MHz 100 Hz LVPECL LVCMOS LVDS 1 kHz LVPECL LVCMOS LVDS 10 kHz LVPECL LVCMOS LVDS 100 kHz LVPECL LVCMOS LVDS 1 MHz LVPECL LVCMOS LVDS 10 MHz LVPECL LVCMOS LVDS
Note 47: Performance data and crystal specifications contained in this section are based on Ecliptek model ECX-6465, 12.288 MHz.
PLL2 PDF = 24.576 MHz (EN_PLL2_REF2X = 1) FCLK = 122.88 MHz 0.300 0.218 0.245 0.284 0.193 0.217 PLL2 FPD = 24.576 MHz (EN_PLL2_REF2X = 1) FCLK = 122.88 MHz -106 -104 -106 -130 -127 -126 -131 -128 -131 -134 -134 -134 -154 -155 -154 -158 -159 -157
FCLK = 153.6 MHz 0.263 0.248 0.269 0.234 0.215 0.235
FCLK = 153.6 MHz -106 -103 -104 -124 -124 -123 -124 -125 -124 -133 -133 -132 -154 -155 -153 -158 -159 -158
-107 -105 -105 -126 -125 -126 -125 -127 -126 -134 -135 -134 -155 -157 -155 -158 -160 -158
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Example crystal specifications are presented in Table 33. TABLE 33. Example Crystal Specifications Parameter Nominal Frequency (MHz) Frequency Stability, T = 25 °C Operating temperature range Frequency Stability, -40 °C to +85 °C Load Capacitance Shunt Capacitance (C0) Motional Capacitance (C1) Equivalent Series Resistance Drive level C0/C1 ratio See Figure 7 for a representative tuning curve. Value 12.288 ± 10 ppm -40 °C to +85 °C ± 15 ppm 14 pF 5 pF Maximum 20 fF ± 30% 25 Ω Maximum 2 mWatts Maximum 225 typical, 250 Maximum The curve shows over the tuning voltage range of 0.17 VDC to 3.0 VDC, the frequency range is ± 163 ppm; or equivalently, a crystal frequency range of ± 2000 Hz. The measured tuning voltage at the nominal crystal frequency (12.288 MHz) is 1.4 V. Using the diode data sheet tuning characteristics, this voltage results in a tuning capacitance of approximately 6.5 pF. The tuning curve data can be used to calculate the gain of the oscillator (KVCO). The data used in the calculations is taken from the most linear portion of the curve, a region centered on the crossover point at the nominal frequency (12.288 MHz). For a well designed circuit, this is the most likely operating range. In this case, the tuning range used for the calculations is ± 1000 Hz (± 0.001 MHz), or ± 81.4 ppm. The simplest method is to calculate the ratio:
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FIGURE 7. Example Tuning Curve, 12.288 MHz Crystal The tuning curve achieved in the user's application may differ from the curve shown above due to differences in PCB layout and component selection. This data is measured on the bench with the crystal integrated with the LMK04000 family. Using a voltmeter to monitor the VTUNE node for the crystal, the PLL1 reference clock input frequency is swept in frequency and the resulting tuning voltage generated by PLL1 is measured at each frequency. At each value of the reference clock frequency, the lock state of PLL1 should be monitored to ensure that the tuning voltage applied to the crystal is valid.
ΔF2 and ΔF1 are in units of MHz. Using data from the curve this becomes:
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A second method uses the tuning data in units of ppm:
30027136
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FNOM is the nominal frequency of the crystal and is in units of MHz. Using the data, this becomes:
30027120 30027137
In order to ensure startup of the oscillator circuit, the equivalent series resistance (ESR) of the selected crystal should conform to the specifications listed in the table of Electrical Characteristics. It is also important to select a crystal with adequate power dissipation capability, or drive level. If the drive level supplied by the oscillator exceeds the maximum specified by the crystal manufacturer, the crystal will undergo excessive aging and possibly become damaged. Drive level is directly proportional to resonant frequency, capacitive load seen by the crystal, voltage and equivalent series resistance (ESR). For more complete coverage of crystal oscillator design, see Application Note AN-1939 at http:// www.national.com/analog/timing/clocking or http:// www.national.com/appnotes. 17.8 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) When terminating clock drivers keep in mind these guidelines for optimum phase noise and jitter performance: • Transmission line theory should be followed for good impedance matching to prevent reflections. • Clock drivers should be presented with the proper loads. For example: — LVDS drivers are current drivers and require a closed current loop. — LVPECL drivers are open emitters and require a DC path to ground. • Receivers should be presented with a signal biased to their specified DC bias level (common mode voltage) for proper operation. Some receivers have self-biasing inputs that automatically bias to the proper voltage level. In this case, the signal should normally be AC coupled. It is possible to drive a non-LVPECL or non-LVDS receiver with an LVDS or LVPECL driver as long as the above guidelines are followed. Check the datasheet of the receiver or input being driven to determine the best termination and coupling method to be sure that the receiver is biased at its optimum DC voltage (common mode voltage). For example, when driving the OSCin/OSCin* input of the LMK04000 family, OSCin/OSCin* should be AC coupled because OSCin/ OSCin* biases the signal to the proper DC level (See Figure 3) This is only slightly different from the AC coupled cases described in Section 17.9.2 Driving CLKin Pins with a SingleEnded Source because the DC blocking capacitors are placed between the termination and the OSCin/OSCin* pins, but the concept remains the same. The receiver (OSCin/OSCin*) sets the input to the optimum DC bias voltage (common mode voltage), not the driver. 17.8.1 Termination for DC Coupled Differential Operation For DC coupled operation of an LVDS driver, terminate with 100 Ω as close as possible to the LVDS receiver as shown in Figure 8.
FIGURE 8. Differential LVDS Operation, DC Coupling, No Biasing of the Receiver For DC coupled operation of an LVPECL driver, terminate with 50 Ω to VCC - 2 V as shown in Figure 9. Alternatively terminate with a Thevenin equivalent circuit (120 Ω resistor connected to VCC and an 82 Ω resistor connected to ground with the driver connected to the junction of the 120 Ω and 82 Ω resistors) as shown in Figure 10 for VCC = 3.3 V.
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FIGURE 9. Differential LVPECL Operation, DC Coupling
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FIGURE 10. Differential LVPECL Operation, DC Coupling, Thevenin Equivalent 17.8.2 Termination for AC Coupled Differential Operation AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important to ensure the receiver is biased to its ideal DC level. When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do this is with the termination circuitry in Figure 11.
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It is possible to use an LVPECL driver as one or two separate 800 mVpp signals. When using only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to properly terminated the unused driver. When DC coupling one of the LMK04000 family clock LVPECL drivers, the termination should be 50 Ω to VCC - 2 V as shown in Figure 14. The Thevenin equivalent circuit is also a valid termination as shown in Figure 15 for Vcc = 3.3 V.
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FIGURE 11. Differential LVDS Operation, AC Coupling, External Biasing at the Receiver Some LVDS receivers may have internal biasing on the inputs. In this case, the circuit shown in Figure 11 is modified by replacing the 50 Ω terminations to Vbias with a single 100 Ω resistor across the input pins of the receiver, as shown in Figure 12. When using AC coupling with LVDS outputs, there may be a startup delay observed in the clock output due to capacitor charging. The previous figures employ a 0.1 µF capacitor. This value may need to be adjusted to meet the startup requirements for a particular application.
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FIGURE 14. Single-Ended LVPECL Operation, DC Coupling
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FIGURE 12. LVDS Termination for a Self-Biased Receiver
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LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120 Ω emitter resistors close to the LVPECL driver to provide a DC path to ground as shown in Figure 13. For proper receiver operation, the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical DC bias voltage for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82 Ω resistor connected to VCC and a 120 Ω resistor connected to ground with the driver connected to the junction of the 82 Ω and 120 Ω resistors) is a valid termination as shown in Figure 13 for VCC = 3.3 V. Note this Thevenin circuit is different from the DC coupled example in Figure 10.
FIGURE 15. Single-Ended LVPECL Operation, DC Coupling, Thevenin Equivalent When AC coupling an LVPECL driver use a 120 Ω emitter resistor to provide a DC path to ground and ensure a 50 Ω termination with the proper DC bias level for the receiver. The typical DC bias voltage for LVPECL receivers is 2 V (See Section 17.9.2 Driving CLKin Pins with a Single-Ended Source). If the companion driver is not used it should be terminated with either a proper AC or DC termination. This latter example of AC coupling a single-ended LVPECL signal can be used to measure single-ended LVPECL performance using a spectrum analyzer or phase noise analyzer. When using most RF test equipment no DC bias point (0 VDC) is required for safe and proper operation. The internal 50 Ω termination of the test equipment correctly terminates the LVPECL driver being measured as shown in Figure 16.
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FIGURE 13. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent, External Biasing at the Receiver 17.8.3 Termination for Single-Ended Operation A balun can be used with either LVDS or LVPECL drivers to convert the balanced, differential signal into an unbalanced, single-ended signal.
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FIGURE 16. Single-Ended LVPECL Operation, AC Coupling
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17.9 DRIVING CLKin AND OSCin INPUTS 17.9.1 Driving CLKin Pins with a Differential Source Both CLKin ports can be driven by differential signals. It is recommended that the input mode be set to bipolar (CLKinX_TYPE = 0) when using differential reference clocks. The LMK04000 family internally biases the input pins so the differential interface should be AC coupled. The recommended circuits for driving the CLKin pins with either LVDS or LVPECL are shown in Figure 17 and Figure 18.
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FIGURE 20. CLKinX/X* Single-ended Termination If the CLKin pins are being driven with a single-ended LVCMOS/LVTTL source, either DC coupling or AC coupling may be used. If DC coupling is used, the CLKinX_TYPE should be set to MOS buffer mode (CLKinX_TYPE = 1) and the voltage swing of the source must meet the specifications for DC coupled, MOS-mode clock inputs given in the table of Electrical Characteristics. If AC coupling is used, the CLKinX_TYPE should be set to the bipolar buffer mode (CLKinX_TYPE = 0). The voltage swing at the input pins must meet the specifications for AC coupled, bipolar mode clock inputs given in the table of Electrical Characteristics. In this case, some attenuation of the clock input level may be required. A simple resistive divider circuit before the AC coupling capacitor is sufficient.
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FIGURE 17. CLKinX/X* Termination for an LVDS Reference Clock Source
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FIGURE 18. CLKinX/X* Termination for an LVPECL Reference Clock Source Finally, a reference clock source that produces a differential sinewave output can drive the CLKin pins using the following circuit. Note: the signal level must conform to the requirements for the CLKin pins listed in the Electrical Characteristics table.
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FIGURE 21. DC Coupled LVCMOS/LVTTL Reference Clock 17.10 ADDITIONAL OUTPUTS WITH AN LMK04000 FAMILY DEVICE The number of outputs on a LMK04000 family device can be expanded in many ways. The first method is to use the differential outputs as two single-ended outputs. For CMOS outputs, both the positive and negative outputs can be programmed to be in phase, or 180 degrees out of phase. LVDS/ LVPECL positive and negative outputs are always 180 degrees out of phase. LVDS single-ended is not recommended. In addition to this technique, the number of outputs can be expanded with a LMK01000 family device. To do this, one of the clock outputs of a LMK04000 can drive the LMK01000 device. For more information on phase synchronication with multiple devices, please refer to application note AN-1864: http://www.national.com/an/AN/AN-1864.pdf. 17.11 OUTPUT CLOCK PHASE NOISE PERFORMANCE VS. VCXO PHASE NOISE The jitter cleaning capability of the LMK04000 family is highly dependent on the phase noise performance of the VCXO (or crystal) that is integrated with PLL1. The VCXO is the reference for PLL2 which provides the clock for the output distribution path. Consequently, the designer must choose a VCXO (or crystal) that supports the required performance at the clock outputs. An example of the difference in performance that can be obtained from various VCXOs is illustrated in the following plots.
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FIGURE 19. CLKinX/X* Termination for a Differential Sinewave Reference Clock Source 17.9.2 Driving CLKin Pins with a Single-Ended Source The CLKin pins of the LMK04000 family can be driven using a single-ended reference clock source, for example, either a sinewave source or an LVCMOS/LVTTL source. Either AC coupling or DC coupling may be used. In the case of the sinewave source that is expecting a 50 Ω load, it is recommended that AC coupling be used as shown in the circuit below with a 50 Ω termination..
Note: The signal level must conform to the requirements for the CLKin pins listed in the Electrical Characteristics table. CLKinX_TYPE in Register 11 is recommended to be set to bipolar mode (CLKinX_TYPE = 0).
LMK04000 Family
Figure 22 compares the phase noise of two different VCXOs: VCXO “A” and VCXO “B”. Both VCXOs have a center frequency of 100 MHz. The figure of merit, RMS jitter, is mea-
sured over the bandwidth 100 Hz to 200 kHz. This is the most relevant integration bandwidth for the VCXO because it will have the most impact inside the loop bandwidth of PLL2.
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FIGURE 22. VCXO Phase Noise Comparison, 100 MHz This plot shows that VCXO “B” exhibits superior phase noise when compared to VCXO “A”. Both VCXOs offer excellent jitter performance from 100 Hz to 200 kHz. VCXO “A” exhibits RMS jitter of 151 femtoseconds (fs), while VCXO “B” has RMS jitter of 90 fs. Figures 23, 24, 25 present a side-by-side comparison of clock output phase noise at 250 MHz, organized by output format and associated VCXO. The total RMS jitter listed on the plots is integrated from 100 Hz to 20 MHz. Examining these plots, the clock output phase noise associated with VCXO “B” is superior in all cases. The average improvement in RMS jitter due to VCXO “B” is approximately 47 fs. The plots show the primary difference in clock output phase noise is in the band from 100 Hz to approximately 4 kHz. Across this range, the VCXO phase noise dominates that of the PLL, given the loop bandwidth of this design, which is 152 kHz. Above 4 kHz, the PLL noise dominates (inside the loop bandwidth), so it is basically the same for either VCXO. Comparing the jitter of two VCXOs in the 100 Hz to 4 kHz band, it can be shown that VCXO “A” exhibits jitter of 142 fs, and VCXO “B” exhibits jitter of 90 fs. The difference, 52 fs, accounts for the majority of the average difference in RMS jitter at the clock outputs when comparing VCXOs. The PLL configurations listed below were the same for both VCXOs/LMK040xx pair: • PLL1 loop filter components: C1 = 100 nF, C2 = 680 nF, R2 = 39 kΩ • PLL1 fPD = 1 MHz, CP gain = 100 µA, loop BW = 20 Hz • PLL2 loop filter components: C1 = 0, C2 = 12 nF, R2 = 1.8 kΩ • PLL2 fPD = 25 MHz, CP gain = 3200 µA, loop BW = 152 kHz
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FIGURE 23. LVDS Clock Output Phase Noise Comparison, 250 MHz
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FIGURE 24. LVPECL Clock Output Phase Noise Comparison, 250 MHz
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FIGURE 25. LVCMOS Clock Output Phase Noise Comparison, 250 MHz
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18.0 Physical Dimensions inches (millimeters) unless otherwise noted
Leadless Leadframe Package (Bottom View) 48 Pin LLP (SQA48A) Package
19.0 Ordering Information
Order Number LMK04000BISQX LMK04000BISQ LMK04000BISQE LMK04001BISQX LMK04001BISQ LMK04001BISQE LMK04002BISQX LMK04002BISQ LMK04002BISQE LMK04010BISQX LMK04010BISQ LMK04010BISQE LMK04011BISQX LMK04011BISQ LMK04011BISQE LMK04031BISQX LMK04031BISQ LMK04031BISQE LMK04033BISQX LMK04033BISQ LMK04033BISQE VCO Frequency Band 1.2 GHz 1.2 GHz 1.2 GHz 1.5 GHz 1.5 GHz 1.5 GHz 1.6 GHz 1.6 GHz 1.6 GHz 1.2 GHz 1.2 GHz 1.2 GHz 1.5 GHz 1.5 GHz 1.5 GHz 1.5 GHz 1.5 GHz 1.5 GHz 2.0 GHz 2.0 GHz 2.0 GHz Packing 2500 Unit Tape and Reel 1000 Unit Tape and Reel 250 Unit Tape and Reel 2500 Unit Tape and Reel 1000 Unit Tape and Reel 250 Unit Tape and Reel 2500 Unit Tape and Reel 1000 Unit Tape and Reel 250 Unit Tape and Reel 2500 Unit Tape and Reel 1000 Unit Tape and Reel 250 Unit Tape and Reel 2500 Unit Tape and Reel 1000 Unit Tape and Reel 250 Unit Tape and Reel 2500 Unit Tape and Reel 1000 Unit Tape and Reel 250 Unit Tape and Reel 2500 Unit Tape and Reel 1000 Unit Tape and Reel 250 Unit Tape and Reel Package Marking K04000BI K04000BI K04000BI K04001BI K04001BI K04001BI K04002BI K04002BI K04002BI K04010BI K04010BI K04010BI K04011BI K04011BI K04011BI K04031BI K04031BI K04031BI K04033BI K04033BI K04033BI
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LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
Notes
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