LMP90098

LMP90100/LMP90099/LMP90098/LMP90097 Sensor AFE System: Multi-Channel, Low Power 24Bit Sensor AFE with True Continuous Background Calibration LMP90100/LMP90099/ LMP90098/LMP90097 July 25, 2011 Sensor AFE System: Multi-Channel, Low Power 24-Bit Sensor AFE with True Continuous Background Calibration 1.0 General Description The LMP90100/LMP90099/LMP90098/LMP90097 are highly integrated, multi-channel, low power 24-bit Sensor AFEs. The devices features a precision, 24-bit Sigma Delta Analog-toDigital Converter (ADC) with a low-noise programmable gain amplifier and a fully differential high impedance analog input multiplexer. A true continuous background calibration feature allows calibration at all gains and output data rates without interrupting the signal path. The background calibration feature essentially eliminates gain and offset errors across temperature and time, providing measurement accuracy without sacrificing speed and power consumption. Another feature of the LMP90100/LMP90099/LMP90098/ LMP90097 is continuous background sensor diagnostics, allowing the detection of open and short circuit conditions and out-of-range signals, without requiring user intervention, resulting in enhanced system reliability. Two sets of independent external reference voltage pins allow multiple ratiometric measurements. In addition, two matched programmable current sources are available in the LMP90100/LMP90098 to excite external sensors such as resistive temperature detectors and bridge sensors. Furthermore, seven GPIO pins are provided for interfacing to external LEDs and switches to simplify control across an isolation barrier. Collectively, these features make the LMP90100/LMP90099/ LMP90098/LMP90097 complete analog front-ends for low power, precision sensor applications such as temperature, pressure, strain gauge, and industrial process control. The LMP90100/LMP90099/LMP90098/LMP90097 are guaranteed over the extended temperature range of -40°C to +125° C and are available in a 28-pin TSSOP package. ■ Low-Noise programmable gain (1x - 128x) ■ Continuous background open/short and out of range sensor diagnostics ■ 8 output data rates (ODR) with single-cycle settling ■ 2 matched excitation current sources from 100 µA to ■ ■ ■ ■ ■ ■ ■ ■ ■ 1000 µA (LMP90100/LMP90098) 4-DIFF / 7-SE inputs (LMP90100/LMP90099) 2-DIFF / 4-SE inputs (LMP90098/LMP90097) 7 General Purpose Input/Output pins Chopper-stabilized buffer for low offset SPI 4/3-wire with CRC data link error detection 50 Hz to 60 Hz line rejection at ODR ≤13.42 SPS Independent gain and ODR selection per channel Supported by Webench Sensor AFE Designer Automatic Channel Sequencer 3.0 Key Specifications ■ ENOB/NFR ■ Offset Error (typ) ■ Gain Error (typ) ■ Total Noise ■ Integral Non-Linearity (INL max) ■ Output Data Rates (ODR) ■ Analog Voltage, VA ■ Operating Temp Range ■ Package Up to 21.5/19 bits 8.4 nV 7 ppm < 10 µV-rms ±15 ppm of FSR 1.6775 SPS - 214.65 SPS +2.85V to +5.5V -40°C to 125°C 28-Pin TSSOP 2.0 Features ■ 24-Bit Low Power Sigma Delta ADC ■ True Continuous Background Calibration at all gains ■ In-Place System Calibration using Expected Value programming 4.0 Applications ■ Temperature and Pressure Transmitters ■ Strain Gauge Interface ■ Industrial Process Control 5.0 Typical Application 30139574 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation 301395 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 6.0 Block Diagram 30139575 FIGURE 1. Block Diagram • True Continuous Background Calibration The LMP90100/LMP90099/LMP90098/LMP90097 feature a 24 bit ΣΔ core with continuous background calibration to compensate for gain and offset errors in the ADC, virtually eliminating any drift with time and temperature. The calibration is performed in the background without user or ADC input interruption, making it unique in the industry and eliminating down time associated with field calibration required with other solutions. Having this continuous calibration improves performance over the entire life span of the end product. • Continuous Background Sensor Diagnostics Sensor diagnostics are also performed in the background, without interfering with signal path performance, allowing the detection of sensor shorts, opens, and out-of-range signals, which vastly improves system reliability. In addition, the fully flexible input multiplexer described below allows any input pin to be connected to any ADC input channel providing additional sensor path diagnostic capability. • Flexible Input MUX Channels The flexible input MUX allows interfacing to a wide range of sensors such as thermocouples, RTDs, thermistors, and bridge sensors. The LMP90100/LMP90099’s multiplexer supports 4 differential channels while the LMP90098/LMP90097 supports 2. Each effective input voltage that is digitized is VIN = VINx – VINy, where x and y are any input. In addition, the input multiplexer of the LMP90100/LMP90099 also supports 7 single-ended channels (LMP90098/LMP90097 supports 4), where the common ground is any one of the inputs. • Programmable Gain Amplifiers (FGA & PGA) The LMP90100/LMP90099/LMP90098/LMP90097 contain an internal 16x fixed gain amplifier (FGA) and a 1x, 2x, 4x, or 8x programmable gain amplifier (PGA). This allows accurate gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x through configuration of internal registers. Having an internal amplifier eliminates the need for external amplifiers that are costly, space consuming, and difficult to calibrate. • Excitation Current Sources (IB1 & IB2) - LMP90100/ LMP90098 Two matched internal excitation currents, IB1 and IB2, can be used for sourcing currents to a variety of sensors. The current range is from 100 µA to 1000 µA in steps of 100 µA. www.national.com 2 LMP90100/LMP90099/LMP90098/LMP90097 Table of Contents 1.0 General Description ......................................................................................................................... 1 2.0 Features ........................................................................................................................................ 1 3.0 Key Specifications ........................................................................................................................... 1 4.0 Applications .................................................................................................................................... 1 5.0 Typical Application ........................................................................................................................... 1 6.0 Block Diagram ................................................................................................................................ 2 7.0 Ordering Information ........................................................................................................................ 5 8.0 Connection Diagram ........................................................................................................................ 5 9.0 Pin Descriptions .............................................................................................................................. 6 10.0 Absolute Maximum Ratings ............................................................................................................. 7 11.0 Operating Ratings .......................................................................................................................... 7 12.0 Electrical Characteristics ................................................................................................................ 7 13.0 Timing Diagrams ......................................................................................................................... 12 14.0 Specific Definitions ...................................................................................................................... 15 15.0 Typical Performance Characteristics .............................................................................................. 16 16.0 Functional Description .................................................................................................................. 22 16.1 SIGNAL PATH ..................................................................................................................... 22 16.1.1 Reference Input (VREF) .............................................................................................. 22 16.1.2 Flexible Input MUX (VIN) ............................................................................................. 22 16.1.3 Selectable Gains (FGA & PGA) .................................................................................... 23 16.1.4 Buffer (BUFF) ............................................................................................................ 23 16.1.5 Internal/External CLK Selection .................................................................................... 23 16.1.6 Programmable ODRs .................................................................................................. 23 16.1.7 Digital Filter ............................................................................................................... 24 16.1.8 GPIO (D0–D6) ........................................................................................................... 27 16.2 CALIBRATION ..................................................................................................................... 27 16.2.1 Background Calibration ............................................................................................... 27 16.2.2 System Calibration ...................................................................................................... 28 FIGURE 15. Post-calibration Scaling Data-Flow Diagram ................................................... 29 16.3 CHANNELS SCAN MODE ..................................................................................................... 29 16.4 SENSOR INTERFACE .......................................................................................................... 30 16.4.1 IB1 & IB2 - Excitation Currents ..................................................................................... 30 16.4.2 Burnout Currents ........................................................................................................ 30 16.4.3 Sensor Diagnostic Flags .............................................................................................. 30 16.5 SERIAL DIGITAL INTERFACE ............................................................................................... 32 16.5.1 Register Address (ADDR) ............................................................................................ 32 16.5.2 Register Read/Write Protocol ....................................................................................... 32 16.5.3 Streaming .................................................................................................................. 32 16.5.4 CSB - Chip Select Bar ................................................................................................. 33 16.5.5 SPI Reset .................................................................................................................. 33 16.5.6 DRDYB - Data Ready Bar ............................................................................................ 33 16.5.7 Data Only Read Transaction ........................................................................................ 36 16.5.8 Cyclic Redundancy Check (CRC) ................................................................................. 37 16.6 POWER MANAGEMENT ...................................................................................................... 38 16.7 RESET and RESTART .......................................................................................................... 38 17.0 Applications Information ............................................................................................................... 39 17.1 QUICK START ..................................................................................................................... 39 17.2 CONNECTING THE SUPPLIES ............................................................................................. 39 17.2.1 VA and VIO ............................................................................................................... 39 17.2.2 VREF ........................................................................................................................ 39 17.3 ADC_DOUT CALCULATION .................................................................................................. 39 17.4 REGISTER READ/WRITE EXAMPLES ................................................................................... 40 17.4.1 Writing to Register Examples ....................................................................................... 40 17.4.2 Reading from Register Example ................................................................................... 41 17.5 STREAMING EXAMPLES ..................................................................................................... 42 17.5.1 Normal Streaming Example ......................................................................................... 42 17.5.2 Controlled Streaming Example ..................................................................................... 43 17.6 EXAMPLE APPLICATIONS ................................................................................................... 45 17.6.1 3–Wire RTD ............................................................................................................... 45 17.6.2 Thermocouple and IC Analog Temperature .................................................................... 47 18.0 Registers .................................................................................................................................... 48 18.1 REGISTER MAP .................................................................................................................. 48 18.2 POWER AND RESET REGISTERS ........................................................................................ 49 18.3 ADC REGISTERS ................................................................................................................ 51 3 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 18.4 CHANNEL CONFIGURATION REGISTERS ............................................................................ 18.5 CALIBRATION REGISTERS .................................................................................................. 18.6 SENSOR DIAGNOSTIC REGISTERS ..................................................................................... 18.7 SPI REGISTERS .................................................................................................................. 18.8 GPIO REGISTERS ............................................................................................................... 19.0 Physical Dimensions .................................................................................................................... 52 56 57 58 60 61 List of Figures FIGURE 1. Block Diagram ......................................................................................................................... 2 FIGURE 2. Timing Diagram ...................................................................................................................... 12 FIGURE 3. Simplified VIN Circuitry .............................................................................................................. 22 FIGURE 4. CLK Register Settings ............................................................................................................... 23 FIGURE 5. Digital Filter Response, 1.6775 SPS and 3.355 SPS .......................................................................... 24 FIGURE 6. Digital Filter Response, 6.71 SPS and 13.42 SPS .............................................................................. 24 FIGURE 7. Digital Filter Response at 13.42 SPS ............................................................................................. 25 FIGURE 8. Digital Filter Response, 26.83125 SPS and 53.6625 SPS .................................................................... 25 FIGURE 9. Digital Filter Response 107.325 SPS and 214.65 SPS ........................................................................ 26 FIGURE 10. Digital Filter Response for a 3.5717MHz versus 3.6864 MHz XTAL ...................................................... 26 FIGURE 11. GPIO Register Settings ............................................................................................................ 27 FIGURE 12. Types of Calibration ................................................................................................................ 27 FIGURE 13. BgcalMode2 Register Settings ................................................................................................... 28 FIGURE 14. System Calibration Data-Flow Diagram ......................................................................................... 28 FIGURE 15. Post-calibration Scaling Data-Flow Diagram ................................................................................... 29 FIGURE 16. Burnout Currents .................................................................................................................... 30 FIGURE 17. Burnout Currents Injection for ScanMode3 ..................................................................................... 30 FIGURE 18. Sensor Diagnostic Flags Diagram ............................................................................................... 31 FIGURE 19. Register Read/Write Protocol ..................................................................................................... 32 FIGURE 20. DRDYB Behavior for a Complete ADC_DOUT Reading ..................................................................... 33 FIGURE 21. DRDYB Behavior for an ADC_DOUT not Read ............................................................................... 33 FIGURE 22. DRDYB Behavior for an Incomplete ADC_DOUT Reading .................................................................. 34 FIGURE 23. DrdybCase1 Connection Diagram ............................................................................................... 34 FIGURE 24. Timing Protocol for DrdybCase1 ................................................................................................. 35 FIGURE 25. Timing Protocol for DrdybCase2 ................................................................................................. 35 FIGURE 26. DrdybCase3 Connection Diagram ............................................................................................... 36 FIGURE 27. Timing Protocol for DrdybCase3 ................................................................................................. 36 FIGURE 28. Timing Protocol for Reading SPI_CRC_DAT .................................................................................. 37 FIGURE 29. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every 1/ODR seconds ...... 37 FIGURE 30. Active, Power-Down, Stand-by State Diagram ................................................................................ 38 FIGURE 31. ADC_DOUT vs. VIN of a 24-Bit Resolution (VREF = 5.5V, Gain = 1). .................................................... 39 FIGURE 32. Register-Write Example 1 ......................................................................................................... 40 FIGURE 33. Register-Write Example 2 ......................................................................................................... 40 FIGURE 34. Register-Read Example ........................................................................................................... 41 FIGURE 35. Normal Streaming Example ....................................................................................................... 42 FIGURE 36. Setting up SPI_STREAMCN ...................................................................................................... 43 FIGURE 37. Controlled Streaming Example ................................................................................................... 44 FIGURE 38. Topology #1: 3-wire RTD Using 2 Current Sources ........................................................................... 45 FIGURE 39. Topology #2: 3-wire RTD Using 1 Current Source ............................................................................ 46 FIGURE 40. Thermocouple with CJC ........................................................................................................... 47 List of Tables TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V ................................. TABLE 2. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V .................................................... TABLE 3. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................. TABLE 4. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................................... TABLE 5. Data First Mode Transactions ........................................................................................................ 11 11 11 11 36 www.national.com 4 LMP90100/LMP90099/LMP90098/LMP90097 7.0 Ordering Information Product LMP90100 LMP90099 LMP90098 LMP90097 Order Code LMP90100MH/NOPB LMP90100MHE/NOPB LMP90100MHX/NOPB LMP90099MH/NOPB LMP90099MHE/NOPB LMP90099MHX/NOPB LMP90098MH/NOPB LMP90098MHE/NOPB LMP90098MHX/NOPB LMP90097MH/NOPB LMP90097MHE/NOPB LMP90097MHX/NOPB Channel Configuration 4 Differential / 7 Single-Ended 4 Differential / 7 Single-Ended 2 Differential / 4 Single-Ended 2 Differential / 4 Single-Ended Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Description 28-Lead TSSOP Package, Rail of 48 28-Lead TSSOP Package, Reel of 250 28-Lead TSSOP Package, Reel of 2500 28-Lead TSSOP Package, Rail of 48 28-Lead TSSOP Package, Reel of 250 28-Lead TSSOP Package, Reel of 2500 28-Lead TSSOP Package, Rail of 48 28-Lead TSSOP Package, Reel of 250 28-Lead TSSOP Package, Reel of 2500 28-Lead TSSOP Package, Rail of 48 28-Lead TSSOP Package, Reel of 250 28-Lead TSSOP Package, Reel of 2500 Current Sources Yes No Yes No 8.0 Connection Diagram 30139576 See Pin Descriptions for specific information regarding options LMP90099, LMP90098, and LMP90097. 5 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 9.0 Pin Descriptions Pin # 1 2-4 5-7 (LMP90100, LMP90099) 5-7 (LMP90098, LMP90097) 8 9 10 11 12 - 13 (LMP90100, LMP90098) 12 - 13 (LMP90099, LMP90097) 14 15 16 17 18 19 20 21 - 26 27 28 Pin Name VA VIN0 - VIN2 VIN3 - VIN5 Type Analog Supply Analog Input Analog Input Analog input pins Analog input pins Function Analog power supply pin VIN3 - VIN5 VREFP1 VREFN1 VIN6 / VREFP2 VIN7 / VREFN2 IB2 & IB1 No Connect Analog Input Analog Input Analog Input Analog Input Analog output No connect: must be left unconnected Positive reference input Negative reference input Analog input pin or VREFP2 input Analog input pin or VREFN2 input Excitation current sources for external RTDs IB2 & IB1 XOUT XIN / CLK GND CSB SCLK SDI SDO / DRDYB D0 - D5 D6 / DRDYB VIO No Connect Analog output Analog input Ground Digital Input Digital Input Digital Input Digital Output Digital IO Digital IO Digital Supply No connect: must be left unconnected External crystal oscillator connection External crystal oscillator connection or external clock input Power supply ground Chip select bar Serial clock Serial data input Serial data output and data ready bar General purpose input/output (GPIO) pins General purpose input/output pin or data ready bar Digtal input/output supply pin www.national.com 6 LMP90100/LMP90099/LMP90098/LMP90097 10.0 Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage, VA Digital I/O Supply Voltage, VIO Reference Voltage, VREF Voltage on Any Analog Input Pin to GND (Note 3) Voltage on Any Digital Input PIN to GND (Note 3) Voltage on SDO (Note 3) Input Current at Any Pin (Note 3) Output Current Source or Sink by SDO Total Package Input and Output Current ESD Susceptibility Human Body Model (HBM) -0.3V to 6.0V -0.3V to 6.0V -0.3V to VA+0.3V -0.3V to VA+0.3V -0.3V to VIO+0.3V -0.3V to VIO + 0.3V 5mA 3mA 20mA 2500V Machine Models (MM) 200V Charged Device Model (CDM) 1250V Junction Temperature (TJMAX) +150°C Storage Temperature Range –65°C to +150°C For soldering specifications: see product folder at www.national.com and www.national.com/ms/MS/MS-SOLDERING.pdf 11.0 Operating Ratings Analog Supply Voltage, VA Digital I/O Supply Voltage, VIO Full Scale Input Range, VIN Reference Voltage, VREF Temperature Range for Electrical Characteristics Operating Temperature Range Junction to Ambient Thermal Resistance (θJA) (Note 4) +2.85V to 5.5V +2.7V to 5.5V ±VREF / PGA +0.5V to VA TMIN = –40°C TMAX = +125°C –40°C ≤ TA ≤ +125°C 41°C/W 12.0 Electrical Characteristics Unless otherwise noted, the key for the condition is (VA = VIO = VREF) / ODR (SPS) / buffer / calibration / gain . Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. Symbol n ENOB / NFR ODR Parameter Resolution Effective Number of Bits and Noise Free Resolution Output Data Rates Gain INL Integral NonLinearity Total Noise FGA × PGA 3V / 214.65 / ON / ON / 1 3V & 5V / 214.65 / ON / ON / 16 3V / all / ON / ON / all. Shorted input. 5V / all / ON / OFF / all. Shorted input. 3V & 5V / all / ON or OFF / ON / all OE Offset Error 3V / 214.65 / ON / ON / 1 3V / 214.65 / ON / ON / 128 5V / 214.65 / ON / ON / 1 5V / 214.65 / ON / ON / 128 3V & 5V / 214.65 / ON or OFF / OFF / 1-8 3V & 5V / 214.65 / ON / ON / 1-8 Offset Drift Over Temp (Note 5) 3V & 5V / 214.65 / ON / OFF / 16 3V & 5V / 214.65 / ON / ON / 16 3V & 5V / 214.65 / ON / OFF / 128 3V & 5V / 214.65 / ON / ON / 128 Offset Drift over Time (Note 5) 5V / 214.65 / ON / OFF / 1, TA = 150°C 5V / 214.65 / ON / ON / 1, TA = 150°C 3V / all / ON / OFF / all. Shorted input. 5V / all / ON / OFF / all. Shorted input. 1.6675 1 -1 Conditions Min Typ 24 Table 1 Table 3 Table 1 Table 1 ± 0.5 ±1 Table 2 Table 4 Below Noise Floor (rms) 1.22 0.00838 1.79 0.0112 100 3 25 0.4 6 0.125 2360 100 9.52 0.70 8.25 0.63 214.6 128 +1 LSB LSB µV µV µV µV µV µV µV nV/°C nV/°C nV/°C nV/°C nV/°C nV/°C nV / 1000 hours nV / 1000 hours Max Units Bits Bits Bits SPS 7 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 Symbol Parameter Conditions 3V & 5V / 214.65 / ON / ON / 1 3V & 5V / 13.42 / ON / ON / 16 3V & 5V / 13.42 / ON / ON / 64 3V & 5V / 13.42 / ON / ON / 128 Min -80 Typ 7 50 50 100 0.5 5.9 1.6 Max 80 Units ppm ppm ppm ppm ppm/°C ppm / 1000 hours ppm / 1000 hours dB dB dB dB dB dB dB GE Gain Error Gain Drift over Temp (Note 5) Gain Drift over Time (Note 5) 3V & 5V / 214.65 / ON / ON / all 5V / 214.65 / ON / OFF / 1, TA = 150°C 5V / 214.65 / ON / ON / 1, TA = 150°C CONVERTER'S CHARACTERISTIC CMRR Input Common Mode Rejection Ratio Reference Common Mode Rejection PSRR Power Supply Rejection Ratio Normal Mode Rejection Ratio (Note 5) Cross-talk DC, 3V / 214.65 / ON / ON / 1 DC, 5V / 214.65 / OFF / OFF / 1 50/60 Hz, 5V / 214.65 / OFF / OFF / 1 VREF = 2.5V DC, 3V / 214.65 / ON / ON / 1 DC, 5V / 214.65 / ON / ON / 1 47 Hz to 63 Hz, 5V / 13.42 / OFF / OFF / 1 3V / 214.65 / OFF / OFF / 1 5V / 214.65 / OFF / OFF / 1 78 95 95 136 143 75 70 90 117 120 117 101 115 112 NMRR dB dB POWER SUPPLY CHARACTERISTICS VA VIO Analog Supply Voltage Digital Supply Voltage 3V / 13.42 / OFF / OFF / 1, ext. CLK 5V / 13.42 / OFF / OFF / 1, ext. CLK 3V / 13.42 / ON / OFF / 64, ext. CLK 5V / 13.42 / ON / OFF / 64, ext. CLK 3V / 214.65 / ON / OFF / 64, int. CLK 5V / 214.65 / ON / OFF / 64, int. CLK IVA Analog Supply Current 3V / 214.65 / OFF / OFF / 1, int. CLK 5V / 214.65 / OFF / OFF / 1, int. CLK Standby, 3V , int. CLK Standby, 3V , ext. CLK Standby, 5V, int. CLK Standby, 3V, ext. CLK Power-down, 3V, int/ext CLK Power-down, 5V, int/ext CLK 2.85 2.7 3.0 3.3 400 464 600 690 1547 1760 826 941 3 257 5 300 2.6 4.6 5 9 15 5.5 5.5 500 555 700 800 1700 2000 1000 1100 10 V V µA µA µA µA µA µA µA µA µA µA µA µA µA µA www.national.com 8 LMP90100/LMP90099/LMP90098/LMP90097 Symbol VREFP VREFN VREF ZREF IREF CREFP Parameter Positive Reference Negative Reference Differential Reference Reference Impedance Reference Input Conditions Min VREFN + 0.5 GND Typ Max VA VREFP - 0.5 VA Units V V V MOhm µA pF REFERENCE INPUT VREF = VREFP - VREFN 3V / 13.42 / OFF / OFF / 1 3V / 13.42 / ON or OFF / ON or OFF / all 0.5 10 ±2 6 Capacitance of the (Note 5), gain = 1 Positive Reference Capacitance of the Negative (Note 5), gain = 1 Reference Reference Leakage Current Power-down CREFN 6 pF ILREF 1 nA ANALOG INPUT Gain = 1-8, buffer ON VINP Positive Input Gain = 16 - 128, buffer ON Gain = 1-8, buffer OFF Gain = 1-8, buffer ON VINN VIN ZIN CINP CINN IIN Negative Input Differential Input Differential Input Impedance Gain = 16 - 128, buffer ON Gain = 1-8, buffer OFF VIN = VINP - VINN ODR = 13.42 SPS GND + 0.1 GND + 0.4 GND GND + 0.1 GND + 0.4 GND ±VREF / PGA 15.4 4 4 500 100 MOhm pF pF pA pA VA - 0.1 VA - 1.5 VA VA - 0.1 VA - 1.5 VA V V V V V V Capacitance of the 5V / 214.65 / OFF / OFF / 1 Positive Input Capacitance of the 5V / 214.65 / OFF / OFF / 1 Negative Input Input Leakage Current Logical "1" Input Voltage Logical "0" Input Voltage Digital Input Leakage Current Digital Input Hysteresis Logical "1" Output Voltage Logical "0" Output Voltage TRISTATE®Leakage Current TRI-STATE Capacitance (Note 5) Source 300 µA Sink 300 µA -10 3V & 5V / 13.42 / ON / OFF / 1-8 3V & 5V / 13.42 / ON / OFF / 16 - 128 DIGITAL INPUT CHARACTERISTICS at VA = VIO = VREF = 3.0V VIH VIL IIL VHYST 0.7 x VIO 0.3 x VIO +10 0.1 x VIO V V µA V DIGITAL OUTPUT CHARACTERISTICS at VA = VIO = VREF = 3.0V VOH VOL IOZH, IOZL COUT 2.6 0.4 V V -10 10 µA 5 pF 9 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 Symbol Parameter Conditions Min Typ 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 1000 Max Units EXCITATION CURRENT SOURCES CHARACTERISTICS (LMP90100/LMP90098 only) Excitation Current Source Output VA = VREF = 3V VA = VREF = 5V -7 -3.5 IB1, IB2 µA IB1/IB2 Tolerance 2.5 0.2 VA - 0.8 0.07 95 60 0.34 0.22 0.2 0.15 0.14 0.13 0.075 0.085 0.11 0.11 2 7 3.5 % % V %/V ppm/°C ppm/°C IB1/IB2 Output VA = 3.0V & 5.0V, Compliance Range IB1/IB2 = 100 µA to 1000 µA IB1/IB2 Regulation IBTC IB1/IB2 Drift VA = 5.0V, IB1/IB2 = 100 µA to 1000 µA VA = 3.0V VA = 5.0V 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 100 µA 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 200 µA 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 300 µA 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 400 µA 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 500 µA 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 600 µA 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 700 µA 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 800 µA 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 900 µA 3V & 5V / 214.65 / OFF / OFF / 1, IB1/IB2 = 1000 µA IBMTC IB1/IB2 Matching Drfit Internal Clock Frequency External Clock Frequency External Crystal Frequency SCLK Serial Clock (Note 5) Input Low Voltage Input High Voltage Frequency Start-up time 1.8 1.8 VA = 3.0V & 5.0V, IB1/IB2 = 100 µA to 1000 µA 1.53 1 0.85 0.8 0.7 0.7 0.65 0.6 0.55 0.45 % % % % % % % % % % ppm/°C IBMT IB1/IB2 Matching INTERNAL/EXTERNAL CLK CLKIN CLKEXT 893 3.5717 0 1 3.5717 7 10 7.2 7.2 kHz MHz V V MHz ms MHz www.national.com 10 LMP90100/LMP90099/LMP90098/LMP90097 TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V ODR (SPS) 1.6775 3.355 6.71 13.42 26.83125 53.6625 107.325 214.65 Gain 1 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 2 20.5 (18) 20 (17.5) 19.5 (17) 18.5 (16) 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 4 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) 8 19 (16.5) 18.5 (16) 18 (15.5) 17.5 (15) 19 (16.5) 18.5 (16) 18 (15.5) 17.5 (15) 16 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 32 19.5 (17) 19 (16.5) 18.5 (16) 18 (15.5) 19 (16.5) 18.5 (16) 18 (15.5) 17.5 (15) 64 19 (16.5) 18.5 (16) 17.5 (15) 17.5 (15) 18 (15.5) 17.5 (15) 17 (14.5) 17 (14.5) 128 18 (15.5) 17 (14.5) 17 (14.5) 16.5 (14) 17.5 (15) 17 (14.5) 16.5 (14) 16 (13.5) TABLE 2. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V ODR (SPS) 1.6775 3.355 6.71 13.42 26.83125 53.6625 107.325 214.65 3.08 4.56 6.15 8.60 3.35 4.81 6.74 9.52 Gain of the ADC 1 1.90 2.70 4.10 5.85 2.24 3.11 4.51 6.37 2 1.53 2.21 3.16 4.29 1.65 2.37 3.38 4.72 4 1.27 1.67 2.39 3.64 1.33 1.90 2.66 3.79 8 0.23 0.34 0.51 0.67 0.33 0.44 0.63 0.90 16 0.21 0.27 0.40 0.54 0.27 0.39 0.54 0.79 32 0.15 0.24 0.37 0.51 0.26 0.37 0.52 0.72 64 128 0.14 0.26 0.35 0.49 0.25 0.36 0.49 0.70 TABLE 3. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V SPS 1.6775 3.355 6.71 13.42 26.83125 53.6625 107.325 214.65 Gain of the ADC 1 21.5 (19) 21 (18.5) 20.5 (18) 20 (17.5) 21.5 (19) 21 (18.5) 20.5 (18) 20 (17.5) 2 21.5 (19) 21 (18.5) 20 (17.5) 19.5 (17) 21 (18.5) 20.5 (18) 20 (17.5) 19.5 (17) 4 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 8 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 16 21 (18.5) 20.5 (18) 20 (17.5) 20 (17.5) 21 (18.5) 20.5 (18) 20 (17.5) 19.5 (17) 32 20.5 (18) 20 (17.5) 19.5 (17) 19 (16.5) 20 (17.5) 19.5 (17) 19 (16.5) 18.5 (16) 64 19.5 (17) 19 (16.5) 19 (16.5) 18 (15.5) 19.5 (17) 18.5 (16) 18 (15.5) 17.5 (15) 128 18.5 (16) 18 (15.5) 17.5 (15) 17.5 (15) 18 (15.5) 17.5 (15) 17 (14.5) 16.5 (14) TABLE 4. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V SPS 1.6775 3.355 6.71 13.42 26.83125 53.6625 107.325 214.65 2.68 3.86 5.23 7.94 2.90 4.11 5.74 8.25 Gain of the ADC 1 1.65 2.36 3.49 5.01 1.86 2.60 3.72 5.31 2 1.24 1.78 2.47 3.74 1.34 1.90 2.72 3.82 4 1.00 1.47 2.09 2.94 1.08 1.50 2.11 2.97 8 0.22 0.34 0.44 0.61 0.29 0.39 0.56 0.79 16 0.19 0.27 0.34 0.50 0.24 0.35 0.48 0.68 32 0.17 0.22 0.30 0.45 0.23 0.32 0.46 0.64 64 128 0.16 0.22 0.32 0.43 0.23 0.31 0.44 0.63 11 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 13.0 Timing Diagrams Unless otherwise noted, specified limits apply for VA = VIO = 3.0V. Boldface limits apply for TMIN ≤ TA ≤ TMAX; the typical values apply for TA = +25°C. 30139501 FIGURE 2. Timing Diagram Symbol fSCLK tCH tCL Parameter SCLK High time SCLK Low time Conditions Min 0.4 / fSCLK 0.4 / fSCLK Typical 10 Max Units MHz ns ns 30139502 30139503 Symbol tCSSU tCSH Parameter CSB Setup time prior to an SCLK rising edge CSB Hold time after the last rising edge of SCLK Conditions Min 5 6 Typical Max Units ns ns www.national.com 12 LMP90100/LMP90099/LMP90098/LMP90097 30139504 30139505 Symbol tCLKR tCLKF tDISU tDIH Parameter SCLK Rise time SCLK Fall time SDI Setup time prior to an SCLK rising edge SDI Hold time after an SCLK rising edge Conditions Min Typical 1.15 1.15 Max Units ns ns ns ns 5 6 30139506 30139507 Symbol tDOA tDOH tDOD1 Parameter SDO Access time after an SCLK falling edge SDO Hold time after an SCLK falling edge SDO Disable time after the rising edge of CSB Conditions Min Typical Max 35 Units ns ns 5 5 ns 13 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 30139508 30139509 Symbol tDOD2 Parameter SDO Disable time after either edge of SCLK Conditions Min Typical Max 27 Units ns 30139511 30139510 Symbol tDOE tDOR tDOF tDRDYB Parameter SDO Enable time from the falling edge of the 8th SCLK SDO Rise time SDO Fall time Data Ready Bar pulse at every 1/ODR second, see Figure 21 (Note 5) (Note 5) Conditions Min Typical Max 35 Units ns ns ns µs µs 7 7 64 4 ODR ≤ 13.42 SPS 13.42 < ODR ≤ 214.65 SPS Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified Note 3: When the input voltage (VIN) exceeds the power supply (VIN < GND or VIN > VA), the current at that pin must be limited to 5mA and VIN has to be within the Absolute Maximum Rating for that pin. The 20 mA package input current rating limits the number of pins that can safely exceed the power supplies with current flow to four pins. Note 4: The maximum power dissipation is a function of TJ(MAX) AND θJA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ (MAX) - TA) / θJA. Note 5: This parameter is guaranteed by design and/or characterization and is not tested in production. www.national.com 14 LMP90100/LMP90099/LMP90098/LMP90097 14.0 Specific Definitions COMMON MODE REJECTION RATIO is a measure of how well in-phase signals common to both input pins are rejected. To calculate CMRR, the change in output offset is measured while the common mode input voltage is changed. CMRR = 20 LOG(ΔCommon Input / ΔOutput Offset) EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) – says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits. LMP90100’s ENOB is a DC ENOB spec, not the dynamic ENOB that is measured using FFT and SINAD. Its equation is as follows: NEGATIVE GAIN ERROR is the difference between the negative full-scale error and the offset error divided by (VREF / Gain). NOISE FREE RESOLUTION is a method of specifying the number of bits for a converter with noise. GAIN ERROR is the deviation from the ideal slope of the transfer function. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point fit method is used. INL for this product is specified over a limited range, per the Electrical Tables. NEGATIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to negative full scale and (-VREF + 1LSB). ODR Output Data Rate. OFFSET ERROR is the difference between the differential input voltage at which the output code transitions from code 0000h to 0001h and 1 LSB. POSITIVE FULL-SCALE ERROR is the difference between the differential input voltage at which the output code transitions to positive full scale and (VREF – 1LSB). POSITIVE GAIN ERROR is the difference between the positive full-scale error and the offset error divided by (VREF / Gain). POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well a change in the analog supply voltage is rejected. PSRR is calculated from the ratio of the change in offset error for a given change in supply voltage, expressed in dB. PSRR = 20 LOG (ΔVA / ΔOutput Offset) 15 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 15.0 Typical Performance Characteristics Noise Measurement without Calibration at Gain = 1 250 230 VOUT (μV) 210 190 170 VA = 3V 150 0 200 400 600 TIME (ms) 800 1000 30139515 Unless otherwise noted, specified limits apply for VA = VIO = VREF = 3.0V. The maximum and minimum values apply for TA = TMIN to TMAX; the typical values apply for TA = +25°C. Noise Measurement with Calibration at Gain = 1 50 30 VOUT (μV) 10 -10 -30 VA = 3V -50 0 200 400 600 TIME (ms) 800 1000 30139516 Histogram without Calibration at Gain = 1 Histogram with Calibration at Gain = 1 30139521 30139522 Noise Measurement without Calibration at Gain = 8 40 35 30 VOUT (μV) Noise Measurement with Calibration at Gain = 8 20 15 10 VOUT (μV) 5 0 -5 -10 -15 25 20 15 10 5 0 0 VA = 3V 200 400 600 TIME (ms) 800 1000 30139517 -20 0 VA = 3V 200 400 600 TIME (ms) 800 1000 30139518 www.national.com 16 LMP90100/LMP90099/LMP90098/LMP90097 Histogram without Calibration at Gain = 8 Histogram with Calibration at Gain = 8 30139523 30139524 Noise Measurement without Calibration at Gain = 128 4 3 2 VOUT (μV) Noise Measurement without Calibration at Gain = 128 4 3 2 VOUT (μV) 1 0 -1 -2 -3 1 0 -1 -2 -3 -4 0 VA = 3V 200 400 600 TIME (ms) 800 1000 30139519 -4 0 VA = 3V 200 400 600 TIME (ms) 800 1000 30139520 Histogram without Calibration at Gain = 128 Histogram with Calibration at Gain = 128 30139525 30139526 17 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 ENOB vs. Gain without Calibration at ODR = 13.42 SPS ENOB vs. Gain with Calibration at ODR = 13.42 SPS 30139528 30139534 Noise vs. Gain without Calibration at ODR = 13.42 SPS Noise vs. Gain with Calibration at ODR = 13.42 SPS 30139541 30139548 ENOB vs. Gain without Calibration at ODR = 214.65 SPS ENOB vs. Gain with Calibration at ODR = 214.65 SPS 30139535 30139540 www.national.com 18 LMP90100/LMP90099/LMP90098/LMP90097 Noise vs. Gain without Calibration at ODR = 214.65 SPS Noise vs. Gain with Calibration at ODR = 214.65 SPS 30139549 30139550 Offset Error vs. Temperature without Calibration at Gain = 1 Offset Error vs. Temperature with Calibration at Gain = 1 300 250 200 150 100 50 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 30139561 2.0 VA = 3V OFFSET VOLTAGE (μV) 1.5 OFFSET VOLTAGE (μV) VA = 5V VA = 3V 1.0 0.5 VA = 5V 0.0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 30139564 Offset Error vs. Temperature without Calibration at Gain = 8 Offset Error vs. Temperature with Calibration at Gain = 8 25 OFFSET VOLTAGE ( μV) 20 15 10 VA = 3V 5 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 30139562 0.4 OFFSET VOLTAGE (uV) 0.2 VA = 3V 0.0 VA = 5V VA = 5V -0.2 -0.4 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 30139565 19 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 Gain Error vs. Temperature without Calibration at Gain = 1 160 150 140 130 120 110 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 30139567 Gain Error vs. Temperature with Calibration at Gain = 1 40 GAIN ERROR (ppm) GAIN ERROR (ppm) VA = 5V 20 VA = 5V 0 VA = 3V -20 VA = 3V 0 20 40 60 80 100 120 TEMPERATURE (°C) 30139570 -40 -40 -20 Gain Error vs. Temperature without Calibration at Gain = 8 -100 -110 GAIN ERROR (ppm) -120 -130 -140 VA = 5V -150 -160 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 30139568 Gain Error vs. Temperature with Calibration at Gain = 8 -20 -40 -60 -80 -100 -120 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) 30139571 VA = 3V VA = 3V GAIN ERROR (ppm) VA = 5V Digital Filter Frequency Response 0 -20 -40 -60 -80 -100 -120 1 10 FREQUENCY (Hz) 100 30139551 Digital Filter Frequency Response 0 -20 -40 -60 -80 -100 -120 10 100 FREQUENCY (Hz) 1k 30139553 GAIN (dB) 1.7 SPS 3.4 SPS 6.7 SPS 13.4 SPS GAIN (dB) 26.83 SPS 53.66 SPS 107.33 SPS 214.65 SPS www.national.com 20 LMP90100/LMP90099/LMP90098/LMP90097 INL at Gain = 1 10 INL (ppm of FSR) 5 0 -5 VA = 5V, 13.4 SPS -5 -4 -3 -2 -1 0 1 VIN (V) 2 3 4 5 30139527 -10 21 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 16.0 Functional Description Throughout this datasheet, the LMP90100/LMP90099/ LMP90098/LMP90097 will be referred to as the LMP90xxx. The LMP90xxx is a low-power 24-Bit ΣΔ ADC with 4 fully differential / 7 single-ended analog channels for the LMP90100/ LMP90099 and 2 full differential / 4 single-ended for the LMP90098/LMP90097. Its serial data output is two’s complement format. The output data rate (ODR) ranges from 1.6775 SPS to 214.65 SPS. The serial communication for LMP90xxx is SPI, a synchronous serial interface that operates using 4 pins: chip select bar (CSB), serial clock (SCLK), serial data in (SDI), and serial data out / data ready bar (SDO/DRYDYB). True continuous built-in offset and gain background calibration is also available to improve measurement accuracy. Unlike other ADCs, the LMP90xxx’s background calibration can run without heavily impacting the input signal. This unique technique allows for positive as well as negative gain calibration and is available at all gain settings. The registers can be found in Section 18.0 Registers, and a detailed description of the LMP90xxx are provided in the following sections. 16.1 SIGNAL PATH 16.1.1 Reference Input (VREF) The differential reference voltage VREF (VREFP – VREFN) sets the range for VIN. The muxed VREF allows the user to choose between VREF1 or VREF2 for each channel. This selection can be made by programming the VREF_SEL bit in the CHx_INPUTCN registers (CHx_INPUTCN: VREF_SEL). The default mode is VREF1. If VREF2 is used, then VIN6 and VIN7 cannot be used as inputs because they share the same pin. Refer to Section 17.2.2 VREF for VREF applications information. 16.1.2 Flexible Input MUX (VIN) LMP90xxx provides a flexible input MUX as shown in Figure 3. The input that is digitized is VIN = VINP – VINN; where VINP and VINN can be any availablie input. The digitized input is also known as a channel, where CH = VIN = VINP – VINN. Thus, there are a maximum of 4 differential channels: CH0, CH1, CH2, and CH3 for the LMP90100/LMP90099. The LMP90098/LMP90097 has a maximum of 2 differential channels: CH0 and CH1 because it does not have access to the VIN3, VIN4, and VIN5 pins. LMP90xxx can also be configured single-endedly, where the common ground is any one of the inputs. There are a maximum of 7 single-ended channels: CH0, CH1, CH2, CH3, CH4, CH5, and CH6 for the LMP90100/LMP90099 and 4: CH0, CH1, CH2, CH3 for the LMP90098/LMP90097. The input MUX can be programmed in the CHx_INPUTCN registers. For example on the LMP90100, to program CH0 = VIN = VIN4 – VIN1, go to the CH0_INPUTCN register and set: 1. VINP = 0x4 2. VINN = 0x1 30139577 FIGURE 3. Simplified VIN Circuitry www.national.com 22 LMP90100/LMP90099/LMP90098/LMP90097 16.1.3 Selectable Gains (FGA & PGA) LMP90xxx provides two types of gain amplifiers: a fixed gain amplifier (FGA) and a programmable gain amplifier (PGA). FGA has a fixed gain of 16x or it can be bypassed, while the PGA has programmable gain settings of 1x, 2x, 4x, or 8x. Total gain is defined as FGA x PGA. Thus, LMP90xxx provides gain settings of 1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x with true continuous background calibration. The gain is channel specific, which means that one channel can have one gain, while another channel can have the same or a different gain. The gain can be selected by programming the CHx_CONFIG: GAIN_SEL bits. 16.1.4 Buffer (BUFF) There is an internal unity gain buffer that can be included or excluded from the signal path. Including the buffer provides a high input impedance but increases the power consumption. When gain ≥ 16, the buffer is automatically included in the signal path. When gain < 16, including or excluding the buffer from the signal path can be done by programming the CHX_CONFIG: BUF_EN bit. 16.1.5 Internal/External CLK Selection LMP90xxx allows two clock options: internal CLK or external CLK (crystal (XTAL) or clock source). There is an “External Clock Detection” mode, which detects the external XTAL if it is connected to XOUT and XIN. When operating in this mode, the LMP90xxx shuts off the internal clock to reduce power consumption. Below is a flow chart to help set the appropriate clock registers. 30139578 FIGURE 4. CLK Register Settings The recommended value for the external CLK is discussed in the next sections. 16.1.6 Programmable ODRs If using the internal CLK or external CLK of 3.5717 MHz, then the output date rates (ODR) can be selected (using the ODR_SEL bit) as: 1. 13.42/8 = 1.6775 SPS 2. 13.42/4 = 3.355 SPS 3. 13.42/2 = 6.71SPS 4. 13.42 SPS 5. 214.65/8 = 26.83125 SPS 6. 214.65/4 = 53.6625 SPS 7. 214.65/2 = 107.325 SPS 8. 214.65 SPS (default) If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the ODR will be different. If this is the 23 case, use the equation below to calculate the new ODR values. ODR_Base1 = (CLKEXT) / (266,240) ODR_Base2 = (CLKEXT) / (16,640) ODR1 = (ODR_Base1) / n, where n = 1,2,4,8 ODR2 = (ODR_Base2) / n, where n = 1,2,4,8 For example, a 3.6864 MHz XTAL or external clock has the following ODR values: ODR_Base1 = (3.6864 MHz) / (266,240) = 13.85 SPS ODR_Base2 = (3.6864 MHz) / (16,640) = 221.54 SPS ODR1 = (13.85 SPS) / n = 13.85, 6.92, 3.46, 1.73 SPS ODR2 = (221.54 SPS) / n = 221.54, 110.77, 55.38, 27.69 SPS www.national.com LMP90100/LMP90099/LMP90098/LMP90097 The ODR is channel specific, which means that one channel can have one ODR, while another channel can have the same or a different ODR. Note that these ODRs are meant for a single channel conversion; the ODR needs to be divided by n for n channels 16.1.7 Digital Filter scanning. For example, if the ADC were running at 214.65 SPS and four channels are being scanned, then the ODR per channel would be 214.65/4 = 53.6625 SPS. The LMP90xxx has a fourth order rotated sinc filter that is used to configure various ODRs and to reject power supply frequencies of 50Hz and 60Hz. The 50/60 Hz rejection is only effective when the device is operating at ODR ≤ 13.42 SPS. If the internal CLK or the external CLK of 3.5717 MHz is used, then the LMP90xxx will have the frequency response shown in Figure 5 to Figure 9. 0 1.6775 SPS 3.355 SPS -20 -40 GAIN (dB) -60 -80 -100 -120 0 12 24 36 48 60 FREQUENCY (Hz) 30139560 72 84 96 108 120 FIGURE 5. Digital Filter Response, 1.6775 SPS and 3.355 SPS 0 6.71 SPS 13.42 SPS -20 -40 GAIN (dB) -60 -80 -100 -120 0 12 24 36 48 60 FREQUENCY (Hz) 30139573 72 84 96 108 120 FIGURE 6. Digital Filter Response, 6.71 SPS and 13.42 SPS www.national.com 24 LMP90100/LMP90099/LMP90098/LMP90097 -60 13.42 SPS -70 -80 GAIN (dB) -90 -100 -110 -120 45 47 49 51 53 55 FREQUENCY (Hz) 30139544 57 59 61 63 65 FIGURE 7. Digital Filter Response at 13.42 SPS 0 26.83125 SPS 53.6625 SPS -40 GAIN (dB) -80 -120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (Hz) 30139586 FIGURE 8. Digital Filter Response, 26.83125 SPS and 53.6625 SPS 25 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 0 107.325 SPS 214.65 SPS -40 GAIN (dB) -80 -120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (Hz) 30139587 FIGURE 9. Digital Filter Response 107.325 SPS and 214.65 SPS If the internal CLK is not being used and the external CLK is not 3.5717 MHz, then the filter response would be the same as the response shown above, but the frequency will change according to the equation: fNEW = [(CLKEXT) / 256 ] x (fOLD / 13.952k) Using the equation above, an example of the filter response for a 3.5717 MHz XTAL versus a 3.6864 MHz XTAL can be seen in Figure 10. 0 -20 -40 GAIN (dB) -60 -80 -100 -120 -140 40 45 50 55 60 FREQUENCY (Hz) 65 70 30139556 Crystal = 3.5717 MHz Crystal = 3.6864 MHz FIGURE 10. Digital Filter Response for a 3.5717MHz versus 3.6864 MHz XTAL www.national.com 26 LMP90100/LMP90099/LMP90098/LMP90097 16.1.8 GPIO (D0–D6) Pins D0-D6 are general purpose input/output (GPIO) pins that can be used to control external LEDs or switches. Only a high or low value can be sourced to or read from each pin. Figure 11 shows a flowchart how these GPIOs can be programmed. 30139533 FIGURE 11. GPIO Register Settings 16.2 CALIBRATION As seen in Figure 12, there are two types of calibration: background calibration and system calibration. These calibrations are further described in the next sections. 30139579 FIGURE 12. Types of Calibration 16.2.1 Background Calibration Background calibration is the process of continuously determining and applying the offset and gain calibration coefficients to the output codes to minimize the LMP90xxx’s offset and gain errors. Background calibration is a feature built into the LMP90xxx and is automatically done by the hardware without interrupting the input signal. Four differential channels, CH0-CH3, each with its own gain and ODRs, can be calibrated to improve the accuracy. Types of Background Calibration: Figure 12 also shows that there are two types of background calibration: 1. Type 1: Correction - the process of continuously determining and applying the offset and gain calibration coefficients to the output codes to minimize the LMP90xxx’s offset and gain errors. This method keeps track of changes in the LMP90xxx's gain and offset errors due to changes in the operating condition such as voltage, temperature, or time. 2. Type 2: Estimation - the process of determining and continuously applying the last known offset and gain 27 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 calibration coefficients to the output codes to minimize the LMP90xxx’s offset and gain errors. The last known offset or gain calibration coefficients can come from two sources. The first source is the default coefficient which is pre-determined and burnt in the device’s non-volatile memory. The second source is from a previous calibration run of Type 1: Correction. The benefits of using type 2 calibration is a higher throughput, lower power consumption, and slightly better noise. The exact savings would depend on the number of channels being scanned, and the ODR and gain of each channel. Using Background Calibration: There are four modes of background calibration, which can be programmed using the BGCALCN bits. They are as follows: 1. BgcalMode0: Background Calibration OFF 2. BgcalMode1: Offset Correction / Gain Estimation 3. BgcalMode2: Offset Correction / Gain Correction Follow Figure 13 to set other appropriate registers when using this mode. 4. BgcalMode3: Offset Estimation / Gain Estimation 16.2.2 System Calibration The LMP90xxx provides some unique features to support easy system offset and system gain calibrations. The System Calibration Offset Registers (CHx_SCAL_OFFSET) hold the System Calibration Offset Coefficients in 24bit, two's complement binary format. The System Calibration Gain Registers (CHx_SCAL_GAIN) hold the System Calibration Gain Coefficient in 24-bit, 1.23, unsigned, fixed-point binary format. For each channel, the System Calibration Offset coefficient is subtracted from the conversion result prior to the division by the System Calibration Gain Coefficient. A data-flow diagram of these coefficients can be seen in Figure 14. 30139531 FIGURE 14. System Calibration Data-Flow Diagram There are four distinct sets of System Calibration Offset and System Calibration Gain Registers for use with CH0-CH3. CH4-CH6 reuse the registers of CH0-CH2, respectively. The LMP90xxx provides two system calibration modes that automatically fill the Offset and Gain coefficients for each channel. These modes are the System Calibration Offset Coefficient Determination mode and the System Calibration Gain Coefficient Determination mode. The System Calibration Offset Coefficient Determination mode must be entered prior to the System Calibration Gain Coefficient Determination mode, for each channel. The system zero-scale condition is a system input condition (sensor loading) for which zero (0x00_0000) system-calibrated output code is desired. It may not, however, cause a zero input voltage at the input of the ADC. The system reference-scale condition is usually the system full-scale condition in which the system's input (or sensor's loading) would be full-scale and the desired system-calibrated output code would be 0x80_0000 (unsigned 24-bit binary). However, system full-scale condition need not cause fullscale input voltage at the input of the ADC. The system reference-scale condition is not restricted to just the system full-scale condition. In fact, it can be any arbitrary fraction of full-scale (up to 1.25 times) and the desired systemcalibrated output code can be any appropriate value (up to 0xA00000). The CHx_SCAL_GAIN register must be written with the desired system-calibrated output code (default: 0x800000) before entering the System Calibration Gain Coefficient Determination mode. This helps in in-place system calibration. Below are the detailed procedures for using the System Calibration Offset Coefficient Determination and System Calibration Gain Coefficient Determination modes. System Calibration Offset Coefficient Determination mode 1. Apply system zero-scale condition to the channel (CH0/ CH1/CH2/CH3). 30139530 FIGURE 13. BgcalMode2 Register Settings If operating in BgcalMode2, four channels (with the same ODR) are being converted, and FGA_BGCAL = 0 (default), then the ODR is reduced by: 1. 0.19% of 1.6775 SPS 2. 0.39% of 3.355 SPS 3. 0.78% of 6.71 SPS 4. 1.54% of 13.42 SPS 5. 3.03% of 26.83125 SPS 6. 5.88% of 53.6625 SPS 7. 11.11% of 107.325 SPS 8. 20% of 214.65 SPS www.national.com 28 LMP90100/LMP90099/LMP90098/LMP90097 2. 3. 4. 5. Enter the System Calibration Offset Coefficient Determination mode by programming 0x1 in the SCALCN register. LMP90xxx starts a fresh conversion at the selected output data rate for the selected channel. At the end of the conversion, the CHx_SCAL_OFFSET register is filled-in with the System Calibration Offset coefficient. The System Calibration Offset Coefficient Determination mode is automatically exited. The computed calibration coefficient is accurate only to the effective resolution of the device and will probably contain some noise. The noise factor can be minimized by computing over many times, averaging (externally) and putting the resultant value back into the register. Alternatively, select the output data rate to be 26.83 sps or 1.67 sps. 30139542 FIGURE 15. Post-calibration Scaling Data-Flow Diagram System Calibration Gain Coefficient Determination mode 1. Repeat the System Calibration Offset Coefficient Determination mode to calibrate for the channel's system offset. 2. Apply the system reference-scale condition to the channel CH0/CH1/CH2/CH3. 3. In the CHx_SCAL_GAIN Register, program the expected (desired) system-calibrated output code for this condition in 24-bit unsigned format. 4. Enter the System Calibration Gain Coefficient Determination mode by programming 0x3 in the SCALCN register. 5. LMP90xxx starts a fresh conversion at the selected output data rate for the channel. At the end of the conversion, the CHx_SCAL_GAIN is filled-in (or overwritten) with the System Calibration Gain coefficient. 6. The System Calibration Gain Coefficient Determination mode is automatically exited. 7. The computed calibration coefficient is accurate only to the effective resolution of the device and will probably contain some noise. The noise factor can be minimized by computing over many times, averaging (externally) and putting the resultant value back into the register. Alternatively, select the output data rate to be 26.83 sps or 1.67 sps. Post-calibration Scaling LMP90xxx allows scaling (multiplication and shifting) for the System Calibrated result. This eases downstream processing, if any. Multiplication is done using the System Calibration Scaling Coefficient in the CHx_SCAL_SCALING register and shifting is done using the System Calibration Bits Selector in the CHx_SCAL_BITS_SELECTOR register. The System Calibration Bits Selector value should ideally be the logarithm (to the base 2) of the System Calibration Scaling Coefficient value. There are four distinct sets of System Calibration Scaling and System Calibration Bits Selector Registers for use with Channels 0-3. Channels 4-6 reuse the registers of Channels 0-2, respectively. A data-flow diagram of these coefficients can be seen in Figure 15 16.3 CHANNELS SCAN MODE There are four scan modes. These scan modes are selected using the CH_SCAN: CH_SCAN_SEL bit. The first scanned channel is FIRST_CH, and the last scanned channel is LAST_CH; they are both located in the CH_SCAN register. The CH_SCAN register is double buffered. That is, user inputs are stored in a slave buffer until the start of the next conversion during which time they are transferred to the master buffer. Once the slave buffer is written, subsequent updates are disregarded until a transfer to the master buffer happens. Hence, it may be appropriate to check the CH_SCAN_NRDY bit before programming the CH_SCAN register. ScanMode0: Single-Channel Continuous Conversion LMP90xxx continuously converts the selected FIRST_CH. Do not operate in this scan mode if gain ≥ 16 and the LMP90xxx is running in background calibration modes BgcalMode1 or BgcalMode2. If this is the case, then it is more suitable to operate the device in ScanMode2 instead. ScanMode1: Multiple-Channels Single Scan LMP90xxx converts one or more channels starting from FIRST_CH to LAST_CH, and then enters the stand-by state. ScanMode2: Multiple-Channels Continuous Scan LMP90xxx continuously converts one or more channels starting from FIRST_CH to LAST_CH, and then it repeats this process. ScanMode3: Multiple-Channels Continuous Scan with Burnout Currents This mode is the same as ScanMode2 except that the burnout current is provided in a serially scanned fashion (injected in a channel after it has undergone a conversion). Thus it avoids burnout current injection from interfering with the conversion result for the channel. The sensor diagnostic burnout currents are available for all four scan modes. The burnout current is further gated by the BURNOUT_EN bit for each channel. ScanMode3 is the only mode that scans multiple channels while injecting burnout currents without interfering with the signal. This is described in details in Section 16.4.2 Burnout Currents. 29 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 16.4 SENSOR INTERFACE LMP90100/LMP90098 contain two types of current sources: excitation currents (IB1 & IB2) and burnout currents. They are described in the next sections. 16.4.1 IB1 & IB2 - Excitation Currents IB1 and IB2 can be used for providing currents to external sensors, such as RTDs or bridge sensors. 100µA to 1000µA, in steps of 100µA, can be sourced by programming the ADC_AUXCN: RTD_CUR_SEL bits. Refer to Section 17.6.1 3–Wire RTD to see how IB1 and IB2 can be used to source a 3-wire RTD. 16.4.2 Burnout Currents As shown in Figure 16, the LMP90xxx contains two internal 10 µA burnout current sources, one sourcing current from VA to VINP, and the other sinking current from VINN to ground. These currents are used for sensor diagnostics and can be enabled for each channel using the CHx_INPUTCN: BURNOUT_EN bit. Burnout Current Injection: Burnout currents are injected differently depending on the channel scan mode selected. When BURNOUT_EN = 1 and the device is operating in ScanMode0, 1, or 2, the burnout currents are injected into all the channels for which the BURNOUT_EN bit is selected. This will cause problems and hence in this mode, more than one channel should not have its BURNOUT_EN bit selected. Also, the burnout current will interfere with the signal and introduce a fixed error depending on the particular external sensor. When BURNOUT_EN = 1 and the device is operating in ScanMode3, burnout currents are injected into the last sampled channel on a cyclical basis (Figure 17). In this mode, burnout currents injection is truly done in the background without affecting the accuracy of the on-going conversion. Operating in this mode is recommended. 30139581 FIGURE 17. Burnout Currents Injection for ScanMode3 16.4.3 Sensor Diagnostic Flags Burnout currents can be used to verify that an external sensor is still operational before attempting to make measurements on that channel. A non-operational sensor means that there is a possibility the connection between the sensor and the LMP90xxx is open circuited, short circuited, shorted to VA or GND, overloaded, or the reference may be absent. The sensor diagnostic flags diagram can be seen in Figure 18. 30139580 FIGURE 16. Burnout Currents www.national.com 30 LMP90100/LMP90099/LMP90098/LMP90097 30139582 FIGURE 18. Sensor Diagnostic Flags Diagram The sensor diagnostic flags are located in the SENDIAG_FLAGS register and are described in further details below. SHORT_THLD_FLAG: The short circuit threshold flag is used to report a short-circuit condition. It is set when the output voltage (VOUT) is within the absolute Vthreshold. Vthreshold can be programmed using the 8-bit SENDIAG_THLDH register concatenated with the 8-bit SENDIAG_THLDL register. For example, assume VREF = 5V, gain = 1, SENDIAG_THLDH = 0xFA, and SENDIAG_THLDL = 0x45. In this case, Dthreshold = 0xFA45 = 64069d, and Vthreshold can be calculated as: Vthreshold = [(Dthreshold)(2)(VREF)] / [(Gain)(224)] Vthreshold = [(64069)(2)(5V)] / [(1)(224)] Vthreshold = 38.2 mV When (-38.2mV) ≤ VOUT ≤ (38.2mV), then SHORT_THLD_FLAG = 1; otherwise, SHORT_THLD_FLAG = 0. RAILS_FLAG: The rails flag is used to detect if one of the sampled channels is within 50mV of the rails potential (VA or VSS). This can be further investigated to detect an open-circuit or short-circuit condition. If the sampled channel is near a rail, then RAILS_FLAG = 1; otherwise, RAILS_FLAG = 0. POR_AFT_LST_RD: If POR_AFT_LST_READ = 1, then there was a power-on reset since the last time the SENDIAG_FLAGS register was read. This flag's status is cleared when this bit is read, unless this bit is set again on account of another power-on-reset event in the intervening period. OFLO_FLAGS: OFLO_FLAGS is used to indicate whether the modulator is over-ranged or under-ranged. The following conditions are possible: 1. OFLO_FLAGS = 0x0: Normal Operation 2. OFLO_FLAGS = 0x1: The modulator was not overranged, but ADC_DOUT got clamped to 0x7f_ffff (positive fullscale) or 0x80_0000 (negative full scale). For example, if VREF = 5V, VIN = 2V, and gain = 128, then OFLO_FLAGS would be 01b. 3. OFLO_FLAGS = 0x2: The modulator was over-ranged towards +VREF. 4. OFLO_FLAGS = 0x3: The modulator was over-ranged towards −VREF. The condition of OFLO_FLAGS = 10b or 11b can be used in conjunction with the RAILS_FLAG to determine the fault condition. SAMPLED_CH: These three bits show the channel number for which the ADC_DOUT and SENDIAG_FLAGS are available. This does not necessarily indicate the current channel under conversion because the conversion frame and computation of results from the channels are pipelined. That is, while the conversion is going on for a particular channel, the results for the previous conversion (of the same or a different channel) are available. 31 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 16.5 SERIAL DIGITAL INTERFACE A synchronous 4-wire serial peripheral interface (SPI) provides access to the internal registers of LMP90xxx via CSB, SCLK, SDI, SDO/DRDYB. 16.5.1 Register Address (ADDR) All registers are memory-mapped. A register address (ADDR) is composed of an upper register address (URA) and lower register address (LRA) as shown in ADDR Map. For example, ADDR 0x3A has URA=0x3 and LRA=0xA. ADDR Map Bit Name [6:4] URA [3:0] LRA 16.5.2 Register Read/Write Protocol Figure 19 shows the protocol how to write to or read from a register. Transaction 1 sets up the upper register address (URA) where the user wants to start the register-write or registerread. Transaction 2 sets the lower register address (LRA) and includes the Data Byte(s), which contains the incoming data from the master or outgoing data from the LMP90xxx. Examples of register-reads or register-writes can be found in Section 17.4 REGISTER READ/WRITE EXAMPLES. 30139536 FIGURE 19. Register Read/Write Protocol 16.5.3 Streaming When writing/reading 3+ bytes, the user must operate the device in Normal Streaming mode or Controlled Streaming mode. In the Normal Streaming mode, which is the default mode, data runs continuously starting from ADDR until CSB deasserts. This mode is especially useful when programming all the configuration registers in a single transaction. See Section 17.5.1 Normal Streaming Example for an example of the Normal Streaming mode. In the Controlled Streaming mode, data runs continuously starting from ADDR until the data has run through all (STRM_RANGE + 1) registers. For example, if the starting ADDR is 0x1C, STRM_RANGE = 5, then data will be written to or read from the following ADDRs: 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21. Once the data reaches ADDR 0x21, LMP90xxx will wrap back to ADDR 0x1C and repeat this process until CSB deasserts. See Section 17.5.2 Controlled Streaming Example for an example of the Controlled Streaming mode. If streaming reaches ADDR 0x7F, then it will wrap back to ADDR 0x00. Furthermore, reading back the Upper Register Address after streaming will report the Upper Register Address at the start of streaming, not the Upper Register Address at the end of streaming. To stream, write 0x3 to INST2’s SZ bits as seen in Figure 19. To select the stream type, program the SPI_STREAMCN: STRM_TYPE bit. The STRM_RANGE can also be programmed in the same register. www.national.com 32 LMP90100/LMP90099/LMP90098/LMP90097 16.5.4 CSB - Chip Select Bar An SPI transaction begins when the master asserts (active low) CSB and ends when the master deasserts (active high) CSB. Each transaction might be separated by a subsequent one with a CSB deassertion, but this is optional. Once CSB is asserted, it must not pulse (deassert and assert again) during a (desired) transaction. CSB can be grounded in systems where LMP90xxx is the only SPI slave. This frees the software from handling the CSB. Care has to be taken to avoid any false edge on SCLK, and while operating in this mode, the streaming transaction should not be used because exiting from this mode can only be done through a CSB deassertion. 16.5.5 SPI Reset SPI Reset resets the SPI-Protocol State Machine by monitoring the SDI for at least 73 consecutive 1's at each SCLK rising edge. After an SPI Reset, SDI is monitored for a possible Write Instruction at each SCLK rising edge. SPI Reset will reset the Upper Address Register (URA) to 0, but the register contents are not reset. By default, SPI reset is disabled, but it can be enabled by writing 0x01 to SPI Reset Register (ADDR 0x02). 16.5.6 DRDYB - Data Ready Bar DRDYB is a signal generated by the LMP90xxx that indicates a fresh conversion data is available in the ADC_DOUT registers. DRDYB is automatically asserted every (1/ODR) second and deasserts when ADC_DOUT is completely read out (LSB of ADC_DOUTL) (). 30139584 FIGURE 20. DRDYB Behavior for a Complete ADC_DOUT Reading If ADC_DOUT is not completely read out (Figure 21) or is not read out at all, but a new ADC_DOUT is available, then DRDYB will automatically pulse for tDRDYB second. The value for tDRDYB can be found in Section 13.0 Timing Diagrams. 30139585 FIGURE 21. DRDYB Behavior for an ADC_DOUT not Read If ADC_DOUT is being read, while the new ADC_DOUT becomes available, then the ADC_DOUT that is being read is still valid(Figure 22). DRDYB will be deasserted at the LSB of the data being read, but a consecutive read on the ADC_DOUT register will fetch the newly converted data available. 33 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 30139512 FIGURE 22. DRDYB Behavior for an Incomplete ADC_DOUT Reading DRDYB can also be accessed via registers using the DT_AVAIL_B bit. This bit indicates when fresh conversion data is available in the ADC_DOUT registers. If new conversion data is available, then DT_AVAIL_B = 0; otherwise, DT_AVAIL_B = 1. As opposed to the drdyb signal, a complete reading for DT_AVAIL_B occurs when the MSB of ADC_DOUTH is read out. This bit cannot be reset even if REG_AND_CNV_RST = 0xC3. DrdybCase1: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x00 30139532 FIGURE 23. DrdybCase1 Connection Diagram As shown in Figure 23, the drdyb signal and SDO can be multiplexed on the same pin as their functions are mostly complementary. In fact, this is the default mode for the SDO/DRDYB pin. Figure 24 shows a timing protocol for DrdybCase1. In this case, start by asserting CSB first to monitor a drdyb assertion. When the drdyb signal asserts, begin writing the Instruction Bytes (INST1, UAB, INST2) to read from or write to registers. Note that INST1 and UAB are omitted from the figure below because this transaction is only required if a new UAB needs to be implemented. While the CSB is asserted, DRDYB is driving the SDO/DRDYB pin unless the device is reading data, in which case, SDO will be driving the pin. If CSB is deasserted, then the SDO/DRDYB pin is High-Z. www.national.com 34 LMP90100/LMP90099/LMP90098/LMP90097 30139501 FIGURE 24. Timing Protocol for DrdybCase1 DrdybCase2: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x03 SDO/DRDYB can be made independent of CSB by setting SDO_DRDYB_DRIVER = 0x03 in the SPI Handshake Control register. In this case, DRDYB will drive the pin unless the device is reading data, independent of the state of CSB. SDO will drive the pin when CSB is asserted and the device is reading data. With this scheme, one can use SDO/DRDYB as a true interrupt source, independent of the state of CSB. But this scheme can only be used when the LMP900xx is the only device connected to the master's SPI bus because the SDO/DRDYB pin will be DRDYB even when CSB is deasserted. The timing protocol for this case can be seen in Figure 25. When drdyb asserts, assert CSB to start the SPI transaction and begin writing the Instruction Bytes (INST1, UAB, INST2) to read from or write to registers. 30139529 FIGURE 25. Timing Protocol for DrdybCase2 35 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 DrdybCase3: Routing DRDYB to D6 30139591 FIGURE 26. DrdybCase3 Connection Diagram The drdyb signal can be routed to pin D6 by setting SPI_DRDYB_D6 high and SDO_DRDYB_DRIVER to 0x4. This is the behavior for DrdybCase3 as shown in Figure 26. The timing protocol for this case can be seen in Figure 27. Since DRDYB is separated from SDO, it can be monitored using the interrupt or polling method. If polled, the drdyb signal needs to be polled faster than tDRDYB to detect a drdyb assertion. When drdyb asserts, assert CSB to start the SPI transaction and begin writing the Instruction Bytes (INST1, UAB, INST2) to read from or write to registers. 30139589 FIGURE 27. Timing Protocol for DrdybCase3 16.5.7 Data Only Read Transaction In a data only read transaction, one can directly access the data byte(s) as soon as the CSB is asserted without having to send any instruction byte. This is useful as it brings down the latency as well as the overhead associated with the instruction byte (as well as the Upper Address Byte, if any). In order to use the data only transaction, the device must be placed in the data first mode. The following table lists transaction formats for placing the device in and out of the data first mode and reading the mode status. TABLE 5. Data First Mode Transactions Bit[7] Enable Data First Mode Instruction Disable Data First Mode Instruction Read Mode Status Transaction www.national.com Bits[6:5] 11 11 00 36 Bit[4] 1 1 1 Bits[3:0] 1010 1011 1111 Data Bytes None None One 1 1 1 LMP90100/LMP90099/LMP90098/LMP90097 Note that while being in the data first mode, once the data bytes in the data only read transaction are sent out, the device is ready to start on any normal (non-data-only) transaction including the Disable Data First Mode Instruction. The current status of the data first mode (enabled/disabled status) can be read back using the Read Mode Status Transaction. This transaction consists of the Read Mode Status Instruction followed by a single data byte (driven by the device). The data first mode status is available on bit [1] of this data byte. The data only read transaction allows reading up to eight consecutive registers, starting from any start address. Usually, the start address will be the address of the most significant byte of conversion data, but it could just as well be any other address. The start address and number of bytes to be read during the data only read transaction can be programmed using the DATA_ONLY_1 AND DATA_ONLY_2 registers respectively. The upper register address is unaffected by a data only read transaction. That is, it retains its setting even after encountering a data only transaction. The data only transaction uses its own address (including the upper address) from the DATA_ONLY_1 register. When in the data first mode, the SCLK must stop high before entering the Data Only Read Transaction; this transaction should be completed before the next scheduled DRDYB deassertion. 16.5.8 Cyclic Redundancy Check (CRC) CRC can be used to ensure integrity of data read from LMP90xxx. To enable CRC, set EN_CRC high. Once CRC is enabled, the CRC value is calculated and stored in SPI_CRC_DAT so that the master device can periodically read for data comparison. Conveniently, the SPI_CRC_DAT register address is located next to the ADC_DOUT register address so that the CRC value can be easily read as part of the data set. The CRC is automatically reset when CSB or DRDYB is deasserted. The CRC polynomial is x8 + x5 + x4 + 1. The reset value of the SPI_CRC_DAT register is zero, and the final value is onescomplemented before it is sent out. Note that CRC computation only includes the bits sent out on SDO and does not include the bits of the SPI_CRC_DAT itself; thus it is okay to read SPI_CRC_DAT repeatedly. The drdyb signal normally deasserts (active high) every 1/ ODR second or when the LSB of ADC_DOUTL is read. However, this behavior can be changed so that drdyb deassertion can occur after SPI_CRC_DAT is read, but not later than normal DRDYB deassertion which occurs at every 1/ODR seconds. This is done by setting bit DRDYB_AFT_CRC high. The timing protocol for CRC can be found in Figure 28. 30139559 FIGURE 28. Timing Protocol for Reading SPI_CRC_DAT If SPI_CRC_DAT read extends beyond the normal DRDYB deassertion at every 1/ODR seconds, then CRC_RST has to be set in the SPI Data Ready Bar Control Register. This is done to avoid a CRC reset at the DRDYB deassertion.Timing protocol for reading CRC with CRC_RST set is shown in Figure 29 30139538 FIGURE 29. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every 1/ODR seconds 37 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 16.6 POWER MANAGEMENT The device can be placed in Active, Power-Down, or StandBy state. In Power-Down, the ADC is not converting data, contents of the registers are unaffected, and there is a drastic power reduction. In Stand-By, the ADC is not converting data, but the power is only slightly reduced so that the device can quickly transition into the active state if desired. These states can be selected using the PWRCN register. When written, PWRCN brings the device into the Active, Power-Down, or Stand-By state. When read, PWRCN indicates the state of the device. The read value would confirm the write value after a small latency (approximately 15 µs with the internal CLK). It may be appropriate to wait for this latency to confirm the state change. Requests not adhering to this latency requirement may be rejected. It is not possible to make a direct transition from the powerdown state to the stand-by state. This state diagram is shown below. 16.7 RESET and RESTART Writing 0xC3 to the REG_AND_CNV_RST field will reset the conversion and most of the programmable registers to their default values. The only registers that will not be reset are the System Calibration Registers (CHx_SCAL_OFFSET, CHx_SCAL_GAIN) and the DT_AVAIL_B bit. If it is desirable to reset the System Calibration Coefficient Registers, then set RESET_SYSCAL = 1 before writing 0xC3 to REG_AND_CNV_RST. If the device is operating in the “System Calibration Offset/Gain Coefficient Determination” mode (SCALCN register), then write REG_AND_CNV_RST = 0xC3 twice to get out of this mode. After a register reset, any on-going conversions will be aborted and restarted. If the device is in the power-down state, then a register reset will bring it out of the power-down state. To restart a conversion, write 1 to the RESTART bit. This bit can be used to synchronize the conversion to an external event. 30139588 FIGURE 30. Active, Power-Down, Stand-by State Diagram www.national.com 38 LMP90100/LMP90099/LMP90098/LMP90097 17.0 Applications Information 17.1 QUICK START This section shows step-by-step instructions to configure the LMP90xxx to perform a simple DC reading from CH0. 1. Apply VA = VIO = VREFP1 = 5V, and ground VREFN1 2. Apply VINP = ¾VREF and VINN = ¼VREF for CH0. Thus, set CH0 = VIN = VINP - VINN = ½VREF (CH0_INPUTCN register) 3. Set gain = 1 (CH0_CONFIG: GAIN_SEL = 0x0) 4. Exclude the buffer from the signal path (CH0_CONFIG: BUF_EN = 1) 5. Set the background to BgcalMode2 (BGCALCN = 0x2) 6. Select VREF1 (CH0_INPUTCN: VREF_SEL = 0) 7. To use the internal CLK, set CLK_EXT_DET = 1 and CLK_SEL = 0. 8. Follow the register read/write protocol (Figure 19) to capture ADC_DOUT from CH0. 17.2 CONNECTING THE SUPPLIES 17.2.1 VA and VIO Any ADC architecture is sensitive to spikes on the analog voltage, VA, digital input/output voltage, VIO, and ground pins. These spikes may originate from switching power supplies, digital logic, high power devices, and other sources. To diminish these spikes, the LMP90xxx’s VA and VIO pins should be clean and well bypassed. A 0.1 µF ceramic bypass capacitor and a 1 µF tantalum capacitor should be used to bypass the LMP90xxx supplies, with the 0.1 µF capacitor placed as close to the LMP90xxx as possible. Since the LMP90xxx has both external VA and VIO pins, the user has two options on how to connect these pins. The first option is to tie VA and VIO together and power them with the same power supply. This is the most cost effective way of powering the LMP90xxx but is also the least ideal because noise from VIO can couple into VA and negatively affect performance. The second option involves powering VA and VIO with separate power supplies. These supply voltages can have the same amplitude or they can be different. 17.2.2 VREF Operation with VREF below VA is also possible with slightly diminished performance. As VREF is reduced, the range of acceptable analog input voltages is also reduced. Reducing the value of VREF also reduces the size of the LSB. When the LSB size goes below the noise floor of the LMP90xxx, the noise will span an increasing number of codes and performance will degrade. For optimal performance, VREF should be the same as VA and sourced with a clean source that is bypassed with a ceramic capacitor value of 0.1 µF and a tantalum capacitor of 10 µF. LMP90xxx also allows ratiometric connection for noise immunity reasons. A ratiometric connection is when the ADC’s VREFP and VREFN are used to excite the input device’s (i.e. a bridge sensor) voltage references. This type of connection severely attenuates any VREF ripple seen the ADC output, and is thus strongly recommended. 17.3 ADC_DOUT CALCULATION The output code of the LMP90xxx can be calculated as: Equation 1 — Output Code ADC_DOUT is in 24−bit two's complement binary format. The largest positive value is 0x7F_FFFF while the largest negative value is 0x80_0000. In case of an over range the value is automatically clamped to one of these two values. Figure 31 shows the theoretical output code, ADC_DOUT, vs. analog input voltage, VIN, using the equation above. 30139547 FIGURE 31. ADC_DOUT vs. VIN of a 24-Bit Resolution (VREF = 5.5V, Gain = 1). 39 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 17.4 REGISTER READ/WRITE EXAMPLES 17.4.1 Writing to Register Examples Using the register read/write protocol shown in Figure 19 , the following example shows how to write three data bytes starting at register address (ADDR) 0x1F. After the last byte has been written to ADDR 0x21, deassert CSB to end the register-write. 30139537 FIGURE 32. Register-Write Example 1 The next example shows how to write one data byte to ADDR 0x12. Since the URA for this example is the same as the last example, transaction 1 can be omitted. 30139590 FIGURE 33. Register-Write Example 2 www.national.com 40 LMP90100/LMP90099/LMP90098/LMP90097 17.4.2 Reading from Register Example The following example shows how to read two bytes. The first byte will be read from starting ADDR 0x24, and the second byte will be read from ADDR 0x25. 30139539 FIGURE 34. Register-Read Example 41 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 17.5 STREAMING EXAMPLES 17.5.1 Normal Streaming Example This example shows how to write six data bytes starting at ADDR 0x28 using the Normal Streaming mode. Because the default STRM_TYPE is the Normal Streaming mode, setting up the SPI_STREAMCN register can be omitted. 30139592 FIGURE 35. Normal Streaming Example www.national.com 42 LMP90100/LMP90099/LMP90098/LMP90097 17.5.2 Controlled Streaming Example This example shows how to read the 24-bit conversion data (ADC_DOUT) four times using the Controlled Streaming mode. The ADC_DOUT registers consist of ADC_DOUTH at ADDR 0x1A, ADC_DOUTM at ADDR 0x1B, and ADC_DOUTL at ADDR 0x1C. The first step (Figure 36) sets up the SPI_STREAMCN register. This step enters the Controlled Streaming mode by setting STRM_TYPE high in ADDR 0x03. Since three registers (ADDR 0x1A - 0x1C) need to be read, the STRM_RANGE is 2. 30139593 FIGURE 36. Setting up SPI_STREAMCN The next step shows how to perform the Controlled Streaming mode so that the master device will read ADC_DOUT from ADDR 0x1A, 0x1B, 0x1C, then wrap back to ADDR 0x1A, and repeat this process for four times. After this process, deassert CSB to end the Controlled Streaming mode. 43 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 30139594 FIGURE 37. Controlled Streaming Example www.national.com 44 LMP90100/LMP90099/LMP90098/LMP90097 17.6 EXAMPLE APPLICATIONS 17.6.1 3–Wire RTD 30139552 FIGURE 38. Topology #1: 3-wire RTD Using 2 Current Sources Figure 38 shows the first topology for a 3-wire resistive temperature detector (RTD) application. Topology #1 uses two excitation current sources, IB1 and IB2, to create a differential voltage across VIN0 and VIN1. As a result of using both IB1 and IB2, only one channel (VIN0-VIN1) needs to be measured. As shown in Equation 2, the equation for this channel is IB1 x (RTD – RCOMP) assuming that RLINE1 = RLINE2. The advantage of this circuit is its ratiometric configuration, where VREF = (IB1 + IB2) x (RREF). Equation 3 shows that a ratiometric configuration eliminates IB1 and IB2 from the output equation, thus increasing the overall performance. Equation 2 — VIN Equation for Topology #1 The PT-100 changes linearly from 100 Ohm at 0°C to 146.07 Ohm at 120°C. If desired, choose a suitable compensating resistor (RCOMP) so that VIN can be virtually 0V at any desirable temperature. For example, if RCOMP = 100 Ohm, then at 0°C, VIN = 0V and thus a higher gain can be used. Equation 3 — ADC_DOUT Showing IB1 & IB2 Elimination 45 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 30139596 FIGURE 39. Topology #2: 3-wire RTD Using 1 Current Source Figure 39 shows the second topology for a 3-wire RTD application. Topology #2 shows the same connection as topology #1, but without IB2. Although this topology eliminates a current source, it requires two channel measurements as shown in Equation 4. Equation 4 — VIN Equation for Topology #2 www.national.com 46 LMP90100/LMP90099/LMP90098/LMP90097 17.6.2 Thermocouple and IC Analog Temperature 30139599 FIGURE 40. Thermocouple with CJC The LMP90xxx is also ideal for thermocouple temperature applications. Thermocouples have several advantages that make them popular in many industrial and medical applications. Compare to RTDs, thermistors, and IC sensors, thermocouples are the most rugged, least expensive, and can operate over the largest temperature range. A thermocouple is a sensor whose junction generates a differential voltage, VIN, that is relative to the temperature difference (Thot – Tcold). Thot is also known as the measuring junction or “hot” junction, which is placed at the measured environment. Tcold is also known as the reference or “cold” junction, which is placed at the measuring system environment. Because a thermocouple can only measure a temperature difference, it does not have the ability to measure absolute temperature. To determine the absolute temperature of the measured environment (Thot), a technique known as cold junction compensation (CJC) must be used. In a CJC technique, the “cold” junction temperature, Tcold, is sensed by using an IC temperature sensor, such as the LM94022. The temperature sensor should be placed within close proximity of the reference junction and should have an isothermal connection to the board to minimize any potential temperature gradients. Once Tcold is obtained, use a standard thermocouple lookup-table to find its equivalent voltage. Next, measure the differential thermocouple voltage and add the equivalent cold junction voltage. Lastly, convert the resulting voltage to temperature using a standard thermocouple look-up-table. For example, assume Tcold = 20°C. The equivalent voltage from a type K thermocouple look-up-table is 0.798 mV. Next, add the measured differential thermocouple voltage to the Tcold equivalent voltage. For example, if the thermocouple voltage is 4.096 mV, the total would be 0.798 mV + 4.096 mV = 4.894 mV. Referring to the type K thermocouple table gives a temperature of 119.37°C for 4.894 mV. 47 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 18.0 Registers 1. 2. 3. If written to, RESERVED bits must be written to only 0 unless otherwise indicated. Read back value of RESERVED bits and registers is unspecified and should be discarded. Recommended values must be programmed and forbidden values must not be programmed where they are indicated in order to avoid unexpected results. Register Name RESETCN SPI_HANDSHAKECN SPI_RESET SPI_STREAMCN Reserved PWRCN DATA_ONLY_1 DATA_ONLY_2 ADC_RESTART Reserved GPIO_DIRCN GPIO_DAT BGCALCN SPI_DRDYBCN ADC_AUXCN SPI_CRC_CN SENDIAG_THLD Reserved SCALCN ADC_DONE SENDIAG_FLAGS ADC_DOUT SPI_CRC_DAT Reset Control SPI Handshake Control SPI Reset Control SPI Stream Control Power Mode Control and Status Data Only Read Control 1 Data Only Read Control 2 ADC Restart Conversion GPIO Direction Control GPIO Data Background Calibration Control SPI Data Ready Bar Control ADC Auxiliary Control CRC Control Sensor Diagnostic Threshold 1,0 System Calibration Control ADC Data Available Sensor Diagnostic Flags Conversion Data 2,1,0 CRC Data 4. If written to, registers indicated as Reserved must have the indicated default value as shown below. Any other value can cause unexpected results. 18.1 REGISTER MAP ADDR (URA & LRA) 0x00 0x01 0x02 0x03 0x04 - 0x07 0x08 0x09 0x0A 0x0B 0x0C - 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 - 0x15 0x16 0x17 0x18 0x19 0x1A - 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0X22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C Type WO R/W R/W R/W RO & WO R/W R/W WO R/W RO & WO R/W R/W R/W R/W R/W R/W RO RO RO RO & WO RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0x00 0x00 0x00 0x00 0x00 0x1A 0x02 0x00 0x00 0x00 0x03 0x00 0x02 0x0000 0x00 0x00 0x00 0x30 0x01 0x70 0x13 0x70 0x25 0x70 0x37 0x70 0x01 0x70 0x13 0x70 0x25 CHANNEL CONFIGURATION REGISTERS (CH4 to CH6 for LMP90100/LMP9099 only) CH_STS CH_SCAN CH0_INPUTCN CH0_CONFIG CH1_INPUTCN CH1_CONFIG CH2_INPUTCN CH2_CONFIG CH3_INPUTCN CH3_CONFIG CH4_INPUTCN CH4_CONFIG CH5_INPUTCN CH5_CONFIG CH6_INPUTCN Channel Status Channel Scan Mode CH0 Input Control CH0 Configuration CH1 Input Control CH1 Configuration CH2 Input Control CH2 Configuration CH3 Input Control CH3 Configuration CH4 Input Control CH4 Configuration CH5 Input Control CH5 Configuration CH6 Input Control www.national.com 48 LMP90100/LMP90099/LMP90098/LMP90097 Register Name CH6_CONFIG Reserved CH0_SCAL_OFFSET CH0_SCAL_GAIN CH0_SCAL_SCALING CH0_SCAL_BITS_SEL ECTOR CH1_SCAL_OFFSET CH1_SCAL_GAIN CH1_SCAL_SCALING CH1_SCAL_BITS_SEL ECTOR CH2_SCAL_OFFSET CH2_SCAL_GAIN CH2_SCAL_SCALING CH2_SCAL_BITS_SEL ECTOR CH3_SCAL_OFFSET CH3_SCAL_GAIN CH3_SCAL_SCALING CH3_SCAL_BITS_SEL ECTOR Reserved CH6 Configuration CH0 System Calibration Offset Coefficients CH0 System Calibration Gain Coefficients CH0 System Calibration Scaling Coefficients CH0 System Calibration Bits Selector CH1 System Calibration Offset Coefficients CH1 System Calibration Gain Coefficient CH1 System Calibration Scaling Coefficients CH1 System Calibration Bits Selector CH2 System Calibration Offset Coefficients CH2 System Calibration Gain Coefficient CH2 System Calibration Scaling Coefficients CH2 System Calibration Bits Selector CH3 System Calibration Offset Coefficients CH3 System Calibration Gain Coefficient CH3 System Calibration Scaling Coefficients CH3 System Calibration Bits Selector - ADDR (URA & LRA) 0x2D 0x2E - 0x2F 0x30 - 0x32 0x33 - 0x35 0x36 0x37 0x38 - 0x3A 0x3B - 0x3D 0x3E 0x3F 0x40 - 0x42 0x43 - 0x45 0x46 0x47 0x48 - 0x4A 0x4B - 0x4D 0x4E 0x4F 0x50 - 0x7F Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - Default 0x70 0x00 0x00_0000 0x80_0000 0x01 0x00 0x00_0000 0x80_0000 0x01 0x00 0x00_0000 0x80_0000 0x01 0x00 0x00_0000 0x80_0000 0x01 0x00 0x00 SYSTEM CALIBRATION REGISTERS 18.2 POWER AND RESET REGISTERS   RESETCN: Reset Control (Address 0x00) Bit Bit Symbol Bit Description Register and Conversion Reset [7:0] REG_AND_CNV_ RST 0xC3: Register and conversion reset Others: Neglected   SPI_RESET: SPI Reset Control (Address 0x02) Bit Bit Symbol Bit Description SPI Reset Enable [0] SPI_ RST 0x0 (default): SPI Reset Disabled 0x1: SPI Reset Enabled Note:Once Written, The contents of this register are sticky. That is, the content of this register cannot be changed with subsequent write.However, a Register reset clears the register as well as the sticky status.   49 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 PWRCN: Power Mode Control and Status (Address 0x08) Bit Bit Symbol Bit Description Power Control Write Only – power down mode control 0x0: Active Mode 0x1: Power-down Mode 0x3: Stand-by Mode Read Only – the present mode is: 0x0 (default): Active Mode 0x1: Power-down Mode 0x3: Stand-by Mode   [7:2] Reserved [1:0] PWRCN www.national.com 50 LMP90100/LMP90099/LMP90098/LMP90097 18.3 ADC REGISTERS   ADC_RESTART: ADC Restart Conversion (Address 0x0B) Bit Bit Symbol Bit Description Restart conversion 1: Restart conversion. [7:1] Reserved 0 RESTART   14.2.1. ADC_AUXCN: ADC Auxiliary Control (Address 0x12) Bit 7 Bit Symbol Reserved Bit Description The System Calibration registers (CHx_SCAL_OFFSET and CHx_SCAL_GAIN) are: 6 RESET_SYSCAL 0 (default): preserved even when "REG_AND_CNV_ RST" = 0xC3. 1: reset by setting "REG_AND_CNV_ RST" = 0xC3. External clock detection 5 CLK_EXT_DET 0 (default): "External Clock Detection" is operational 1: "External-Clock Detection" is bypassed Clock select – only valid if CLK_EXT_DET = 1 4 CLK_SEL 0 (default): Selects internal clock 1: Selects external clock Selects RTD Current as follows: 0x0 (default): 0 µA 0x1: 100 µA 0x2: 200 µA 0x3: 300 µA 0x4: 400 µA 0x5: 500 µA 0x6: 600 µA 0x7: 700 µA 0x8: 800 µA 0x9: 900 µA 0xA: 1000 µA RTD_CUR_SEL [3:0] (LMP90100 and LMP90098 only)   ADC_DONE: ADC Data Available (Address 0x18) Bit Bit Symbol Bit Description Data Available – indicates if new conversion data is available [7:0] DT_AVAIL_B 0x00 − 0xFE: Available 0xFF: Not available 51 www.national.com LMP90100/LMP90099/LMP90098/LMP90097   ADC_DOUT: 24-bit Conversion Data (two’s complement) (Address 0x1A - 0x1C) Address 0x1A 0x1B 0x1C Name ADC_DOUTH ADC_DOUTM ADC_DOUTL Register Description ADC Conversion Data [23:16] ADC Conversion Data [15:8] ADC Conversion Data [7:0] Note: Repeat reads of these registers are allowed as long as such reads are spaced apart by at least 72 µs.   18.4 CHANNEL CONFIGURATION REGISTERS   CH_STS: Channel Status (Address 0x1E) Bit Bit Symbol Bit Description Channel Scan Not Ready – indicates if it is okay to program CH_SCAN 1 CH_SCAN_NRDY 0: Update not pending, CH_SCAN register is okay to program 1: Update pending, CH_SCAN register is not ready to be programmed [7:2] Reserved Invalid or Repeated Read Status 0 INV_OR_RPT_RD_STS 0: ADC_DOUT just read was valid and hitherto unread 1: ADC_DOUT just read was either invalid (not ready) or there was a repeated read.   www.national.com 52 LMP90100/LMP90099/LMP90098/LMP90097 CH_SCAN: Channel Scan Mode (Address 0x1F) Bit Bit Symbol Bit Description Channel Scan Select [7:6] CH_SCAN_SEL 0x0 (default): ScanMode0: Single-Channel Continuous Conversion 0x1: ScanMode1: One or more channels Single Scan 0x2: ScanMode2: One or more channels Continuous Scan 0x3: ScanMode3: One or more channels Continuous Scan with Burnout Currents Last channel for conversion 0x0: CH0 0x1: CH1 0x2: CH2 0x3: CH3 0x4: CH4 0x5: CH5 0x6 (default): CH6 Note: LAST_CH cannot be smaller than FIRST_CH. For example, if LAST_CH = CH5, then FIRST_CH cannot be CH6. If 0x7 is written it is ignored.   Starting channel for conversion 0x0 (default): CH0 0x1: CH1 0x2: CH2 0x3: CH3 0x4: CH4 0x5: CH5 0x6: CH6 Note: FIRST_CH cannot be greater than LAST_CH. For example, if FIRST_CH = CH1, then LAST_CH cannot be CH0. If 0x7 is written it is ignored.     LAST_CH [5:3] (CH4 to CH6 for LMP90100 and LMP90099 only) FIRST_CH [2:0] (CH4 to CH6 for LMP90100 and LMP90099 only) Note: While writing to the CH_SCAN register, if 0x7 is written to FIRST_CH or LAST_CH the write to the entire CH_SCAN register is ignored. 53 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 CHx_INPUTCN: Channel Input Control (CH4 to CH6 for LMP90100/LMP9099 only) Register Address (hex): a. CH0: 0x20 b. CH1: 0X22 c. CH2: 0x24 d. CH3: 0x26 e. CH4: 0x28 f. CH5: 0x2A g. CH6: 0x2C   Bit Bit Symbol Bit Description Enable sensor diagnostic 0 (default): Disable Sensor Diagnostics current injection for this Channel 1: Enable Sensor Diagnostics current injection for this Channel Select the reference 6 VREF_SEL 0 (Default): Select VREFP1 and VREFN1 1: Select VREFP2 and VREFN2 Positive input select 0x0: VIN0 0x1: VIN1 0x2: VIN2 0x3: VIN3 (LMP90100/LMP90099 only) 0x4: VIN4 (LMP90100/LMP90099 only) 0x5: VIN5 (LMP90100/LMP90099 only) 0x6: VIN6 0x7: VIN7 Note: to see the default values for each channel, refer to the table below. 7 BURNOUT_EN [5:3] VINP Negative input select 0x0: VIN0 0x1: VIN1 0x2: VIN2 0x3: VIN3 (LMP90100/LMP90099 only) 0x4: VIN4 (LMP90100/LMP90099 only) 0x5: VIN5 (LMP90100/LMP90099 only) 0x6: VIN6 0x7: VIN7 Note: to see the default values for each channel, refer to the table below. [2:0] VINN Default VINx for CH0-CH6 VINP CH0 CH1 CH2 CH3 www.national.com VINN VIN1 VIN3 (LMP90100/ LMP90099 only) CH4 (LMP90100/ LMP90099 only) CH5 (LMP90100/ LMP90099 only) CH6 (LMP90100/ LMP90099 only)   VIN0 VIN2 VIN4 VIN1 VIN3 VIN5 VIN0 VIN2 VIN4 (LMP90100/ VIN5 (LMP90100/ LMP90099 only) LMP90099 only) VIN6 VIN7 54 LMP90100/LMP90099/LMP90098/LMP90097 CHx_CONFIG: Channel Configuration (CH4 to CH6 LMP90100/LMP90099 only) Register Address (hex): a. CH0: 0x21 b. CH1: 0x23 c. CH2: 0x25 d. CH3: 0x27 e. CH4: 0x29 f. CH5: 0x2B g. CH6: 0x2D   Bit 7 Bit Symbol Reserved Bit Description ODR Select 0x0: 13.42 / 8 = 1.6775 SPS 0x1: 13.42 / 4 = 3.355 SPS 0x2: 13.42 / 2 = 6.71 SPS 0x3: 13.42 SPS 0x4: 214.65 / 8 = 26.83125 SPS 0x5: 214.65 / 4 = 53.6625 SPS 0x6: 214.65 / 2 = 107.325 SPS 0x7 (default): 214.65 SPS Gain Select 0x0 (default): 1 (FGA OFF) 0x1: 2 (FGA OFF) 0x2: 4 (FGA OFF) 0x3: 8 (FGA OFF) 0x4: 16 (FGA ON) 0x5: 32 (FGA ON) 0x6: 64 (FGA ON) 0x7: 128 (FGA ON) [6:4] ODR_SEL [3:1] GAIN_SEL Enable/Disable the buffer 0 BUF_EN 0 (default): Include the buffer in the signal path 1: Exclude the buffer from the signal path Note: When gain ≥ 16, the buffer is automatically included in the signal path irrespective of this bit. 55 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 18.5 CALIBRATION REGISTERS   BGCALCN: Background Calibration Control (Address 0x10) Bit Bit Symbol Bit Description   Background calibration control – selects scheme for continuous background calibration. [1:0] BGCALN 0x0 (default): BgcalMode0: Background Calibration OFF 0x1: BgcalMode1: Offset Correction / Gain Estimation 0x2: BgcalMode2: Offset Correction / Gain Correction 0x3: BgcalMode3: Offset Estimation / Gain Estimation [7:2] Reserved   SCALCN: System Calibration Control (Address 0x17) Bit Bit Symbol Bit Description   System Calibration Control When written, set SCALCN to: 0x0 (default): Normal Mode 0x1: “System Calibration Offset Coefficient Determination” mode 0x2: “System Calibration Gain Coefficient Determination” mode 0x3: Reserved [1:0] SCALCN When read, this bit indicates the system calibration mode is in: 0x0: Normal Mode 0x1: "System Calibration Offset Coefficient Determination" mode 0x2: "System Calibration Gain Coefficient Determination" mode 0x3: Reserved Note: when read, this bit will indicate the current System Calibration status. Since this coefficient determination mode will only take 1 conversion cycle, reading this register will only return 0x00, unless this register is read within 1 conversion window.     CHx_SCAL_OFFSET: CH0-CH3 System Calibration Offset Registers (Two's-Complement) ADDR CH0 0x30 0x31 0x32   CHx_SCAL_GAIN: CH0-CH3 System Calibration Gain Registers (Fixed Point 1.23 Format) ADDR CH0 0x33 0x34 0x35 CH1 CH2 CH3 0x3B 0x43 0x3C 0x44 0x3D 0x45 Name Description System Calibration Gain Coefficient Data [23:16] System Calibration Gain Coefficient Data [15:8] System Calibration Gain Coefficient Data[7:0] 56 [7:2] Reserved CH1 0x38 0x39 CH2 0x40 0x41 CH3 0x48 0x49 Name CHx_SCAL_OFFSETH CHx_SCAL_OFFSETM Description System Calibration Offset Coefficient Data [23:16] System Calibration Offset Coefficient Data [15:8] System Calibration Offset Coefficient Data[7:0] 0x3A 0x42 0x4A CHx_SCAL_OFFSETL 0x4B CHx_SCAL_GAINH 0x4C CHx_SCAL_GAINM 0x4D CHx_SCAL_GAINL www.national.com LMP90100/LMP90099/LMP90098/LMP90097 CHx_SCAL_SCALING: CH0-CH3 System Calibration Scaling Coefficient Registers ADDR CH0 0x36 CH1 CH2 CH3 0x3E 0x46 Name Description System Calibration Scaling Coefficient Data [5:0] 0x4E CHx_SCAL_SCALING CHx_SCAL_BITS_SELECTOR: CH0-CH3 System Calibration Bits Selector Registers ADDR CH0 0x37   18.6 SENSOR DIAGNOSTIC REGISTERS   SENDIAG_THLD: Sensor Diagnostic Threshold (Address 0x14 - 0x15) Address 0x14 0x15 Name SENDIAG_THLDH SENDIAG_THLDL Register Description Sensor Diagnostic threshold [15:8] Sensor Diagnostic threshold [7:0] CH1 0x3F CH2 0x47 CH3 0x4F Name CHx_SCAL_BITS_SELECTOR Description System Calibration Bits Selection Data [2:0]   SENDIAG_FLAGS: Sensor Diagnostic Flags (Address 0x19 ) Bit Bit Symbol Bit Description   Short Circuit Threshold Flag = 1 when the absolute value of VOUT is within the absolute threshold voltage set by SENDIAG_THLDH and SENDIAG_THLDL.     6 RAILS_FLAG Rails Flag = 1 when at least one of the inputs is near rail (VA or GND).     5 POR_AFT_LST_RD Power-on-reset after last read = 1 when there was a power-on-reset event since the last time the SENDIAG_FLAGS register was read.     Overflow flags [4:3] OFLO_FLAGS 0x0: Normal operation 0x1: The modulator was not overranged, but ADC_DOUT got clamped to 0x7f_ffff (positive fullscale) or 0x80_0000 (negative full scale) 0x2: The modulator was over-ranged (VIN > 1.2*VREF/GAIN) 0x3: The modulator was over-ranged (VIN < -1.2*VREF/GAIN)   Channel Number – the sampled channel for ADC_DOUT and SENDIAG_FLAGS.     7 SHORT_THLD_ FLAG [2:0] SAMPLED_CH 57 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 18.7 SPI REGISTERS   SPI_HANDSHAKECN: SPI Handshake Control (Address 0x01) Bit Bit Symbol Bit Description   SDO/DRDYB Driver – sets who is driving the SDO/DRYB pin   Whenever CSB is Whenever CSB is Asserted and the Device CSB is Asserted and the Device is Not Reading Deasserted is Reading ADC_DOUT ADC_DOUT 0x0 (default) 0x3 0x4 SDO is driving SDO is driving SDO is driving DRDYB is driving DRDYB is driving High-Z High-Z DRDYB is driving High-Z [7:4] Reserved [3:1] SDO_DRDYB_ DRIVER 0 SW_OFF_TRG Others Forbidden   Switch-off trigger - refers to the switching of the output drive from the slave to the master. 0 (default): SDO will be high-Z after the last (16th, 24th, 32nd, etc) rising edge of SCLK. This option allows time for the slave to transfer control back to the master at the end of the frame.   1: SDO’s high-Z is postponed to the subsequent falling edge following the last (16th, 24th, 32nd, etc) rising edge of SCLK. This option provides additional hold time for the last bit, DB0, in non-streaming read transfers.     SPI_STREAMCN: SPI Streaming Control (Address 0x03) Bit Bit Symbol Bit Description   Stream type 7 STRM_TYPE 0 (default): Normal Streaming mode 1: Controlled Streaming mode     Stream range – selects Range for Controlled Streaming mode Default: 0x00   [6:0] STRM_ RANGE   DATA_ONLY_1: Data Only Read Control 1 (Address 0x09) Bit 7 Bit Symbol Reserved Bit Description Start address for the Data Only Read Transaction [6:0] DATA_ONLY_ADR Default: 0x1A Please refer to the description of DT_ONLY_SZ in DATA_ONLY_2 register. www.national.com 58 LMP90100/LMP90099/LMP90098/LMP90097 DATA_ONLY_2: Data Only Read Control 2 (Address 0x0A) Bit [2:0] DATA_ONLY_SZ Number of bytes to be read out in Data Only mode. A value of 0x0 means read one byte and 0x7 means read 8 bytes. Default: 0x2 Bit Symbol Bit Description [7:3] Reserved SPI_DRDYBCN: SPI Data Ready Bar Control (Address 0x11 ) Bit Bit Symbol Bit Description   Enable DRDYB on D6 7 SPI_DRDYB_D6 0 (default): D6 is a GPIO 1: D6 = drdyb signal   CRC Reset 0 (default): Enable CRC reset on DRDYB deassertion 1: Disbale CRC reset on DRDYB deassertion   Gain background calibration 3 FGA_BGCAL 0 (default): Correct FGA gain error. This is useful only if the device is operating in BgcalMode2 and ScanMode2 or ScanMode3. 1: Correct FGA gain error using the last known coefficients.   Default - 0x3 (do not change this value) 6 Reserved 5 CRC_RST 4 Reserved [2:0] Reserved   SPI_CRC_CN: CRC Control (Address 0x13 ) Bit Bit Symbol Bit Description   Enable CRC 4 EN_CRC 0 (default): Disable CRC 1: Enable CRC   Default - 0x1 (do not change this value)   DRDYB After CRC 2 DRDYB_AFT_CRC 0 (default): DRDYB is deasserted (active high) after ADC_DOUTL is read. 1: DRDYB is deasserted after SPI_CRC_DAT (which follows ADC_DOUTL), is read.   [7:5] Reserved 3 Reserved [1:0] Reserved   59 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 SPI_CRC_DAT: CRC Data (Address 0x1D ) Bit Bit Symbol Bit Description     CRC Data [7:0] CRC_DAT When written, this register reset CRC: Any Value: Reset CRC When read, this register indicates the CRC data.   18.8 GPIO REGISTERS   GPIO_DIRCN: GPIO Direction (Address 0x0E ) Bit 7 Bit Symbol Reserved Bit Description   GPIO direction control – these bits are used to control the direction of each General Purpose Input/Outputs (GPIO) pins D0 - D6. x GPIO_DIRCNx 0 (default): Dx is an Input 1: Dx is an Output where 0 ≤ x ≤ 6.   For example, writing a 1 to bit 6 means D6 is an Output. Note: If D6 is used for DRDYB, then it cannot be used for GPIO.   GPIO_DAT: GPIO Data (Address 0x0F) Bit 7 Bit Symbol Reserved Bit Description   Write Only - when GPIO_DIRCNx = 0 0: Dx is LO 1: Dx is HI   Read Only - when GPIO_DIRCNx = 1 x Dx 0: Dx driven LO 1: Dx driven HI   where 0 ≤ x ≤ 6.   For example, writing a 0 to bit 4 means D4 is LO. It is okay to Read the GPIOs that are configured as outputs and write to GPIOs that are configured as inputs. Reading the GPIOs that are outputs would return the current value on those GPIOs, and writing to the GPIOs that are inputs are neglected   www.national.com 60 LMP90100/LMP90099/LMP90098/LMP90097 19.0 Physical Dimensions inches (millimeters) unless otherwise noted 28-Lead Molded Plastic TSSOP Order Number LMP90100MH/NOPB, LMP90099MH/NOPB, LMP90098MH/NOPB, LMP90097MH/NOPB NS Package Number MO-153 61 www.national.com LMP90100/LMP90099/LMP90098/LMP90097 Sensor AFE System: Multi-Channel, Low Power 24Bit Sensor AFE with True Continuous Background Calibration Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage References PowerWise® Solutions Temperature Sensors PLL/VCO www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Applications & Markets Mil/Aero PowerWise® Design University Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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