LMS1485 5V Low Power RS-485 Differential Bus Transceiver
July 2003
LMS1485 5V Low Power RS-485 Differential Bus Transceiver
General Description
The LMS1485 is a low power differential bus/line transceiver designed for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines. It meets ANSI Standards TIA/EIA RS422-B, TIA/EIA RS485-A and ITU recommendation and V.11 and X.27. The LMS1485 combines a TRI-STATE™ differential line driver and differential input receiver, both of which operate from a single 5.0V power supply. The driver and receiver have an active high and active low, respectively, that can be externally connected to function as a direction control. The driver and receiver differential inputs are internally connected to form differential input/output (I/O) bus ports that are designed to offer minimum loading to bus whenever the driver is disabled or when VCC = 0V. These ports feature wide positive and negative common mode voltage ranges, making the device suitable for multipoint applications in noisy environments. The LMS1485 is build with National’s advanced BiCMOS process and is available in a 8-Pin SOIC package. It is a drop-in socket replacement to ADI’s ADM1485 and LTC’s LT1485.
Features
n n n n n n n n n n n n n n n Meet ANSI standard RS-485-A and RS-422-B Data rate 30Mbps Single supply voltage operation, 5V Wide input and output voltage range Thermal shutdown protection Short circuit protection Driver propagation delay 10ns Receiver propagation delay 25ns High impedance outputs with power off Open circuit fail-safe for receiver Extended operating temperature range −40˚C to 85˚C ESD rating 8kV HBM Drop-in replacement to ADM1485 and LT1485 Available in 8-pin SOIC Low supply current, ICC = 1mA
Applications
n n n n n n n n Low power RS-485 systems Network hubs, bridges, and routers Point of sales equipment (ATM, barcode scanners,…) Local area networks (LAN) Integrated service digital network (ISDN) Industrial programmable logic controllers High speed parallel and serial applications Multipoint applications with noisy environment
Typical Application
20048801
A typical multipoint application is shown in the above figure. Terminating resistors, RT, are typically required but only located at the two ends of the cable. Pull up and pull down resistors maybe required at the end of the bus to provide failsafe biasing. The biasing resistors provide a bias to the cable when all drivers are in TRI-STATE, See National Application Note, AN-847 for further information.
© 2003 National Semiconductor Corporation
DS200488
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LMS1485
Connection Diagram
8-Pin SOIC
20048802
Top View
Ordering Information
Package Part Number LMS1485M 8-Pin SOIC LMS1485MX LMS1485IM LMS1485IMX Package Marking LMS1485M LMS1485IM Transport Media 95 Units/Rail 2.5k Units Tape and Reel 95 Units/Rail 2.5k Units Tape and Reel M08A NSC Drawing
Pin Descriptions
Pin # I/O 1 2 3 4 5 6 7 8 O I I I N/A I/O I/O N/A Name RO RE DE DI GND A B VCC Function Receiver Output: If A > B by 200 mV, RO will be high; If A < B by 200mV, RO will be low. RO will be high also if the inputs (A and B) are open (non-terminated) Receiver Output Enable: RO is enabled when RE is low; RO is in TRI-STATE when RE is high Driver Output Enable: The driver outputs (A and B) are enabled when DE is high; they are in TRI-STATE when DE is low. Pins A and B also function as the receiver input pins (see below) Driver Input: A low on DI forces A low and B high while a high on DI forces A high and B low when the driver is enabled Ground Non-inverting Driver Output and Receiver Input pin. Driver Output levels conform to RS-485 signaling levels Inverting Driver Output and Receiver Input pin. Driver Output levels conform to RS-485 signaling levels Power Supply: 4.75V ≤ VCC ≤ 5.25V
Truth Table
DRIVER SECTION RE X X X RECEIVER SECTION RE L L H L
Note: * = Non Terminated, Open Input only X = Irrelevant Z = TRI-STATE H = High level L = Low level
DE H H L DE L L X L
DI H L X A-B ≥ +0.2V ≤ −0.2V X OPEN *
A H L Z
B L H Z RO H L Z H
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LMS1485
Absolute Maximum Ratings
(Note 1)
ESD Rating (Note 4) (Note 9) Soldering Information Infrared or Convection (20 sec.)
2kV 235˚C
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VCC (Note 2) Input Voltage, VIN (DI, DE, or RE) Voltage Range at Any Bus Terminal (AB) Receiver Outputs Package Thermal Impedance, θJA SOIC (Note 3) Junction Temperature (Note 3) Operating Free-Air Temperature Range, TA Commercial Industrial Storage Temperature Range ESD Rating (Note 4) (Note 8) 0˚C to 70˚C −40˚C to 85˚C −65˚C to 150˚C 8kV 125˚C/W 150˚C 7V −0.3V to VCC+ 0.3V −7V to 12V −0.3V to VCC + 0.3V
Operating Ratings
Min Nom Max Supply Voltage, VCC Voltage at any Bus Terminal (Separately or Common Mode) VIN or VIC High-Level Input Voltage, VIH (Note 5) Low-Level Input Voltage, VIL (Note 5) Differential Input Voltage, VID (Note 6) 2 0.8 V V V 4.75 −7 5.0 5.25 12 V V
± 12
Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Symbol Driver Section VOD VOD1 VOD2 VOD3 ∆VOD VOC ∆VOC Differential Output Voltage Differential Output Voltage Differential Output Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage Common-Mode Output Voltage Change in Magnitude of Common-Mode Output Voltage Short-Circuit Output Current CMOS Input Logic Threshold Low CMOS Input Logic Threshold High Logic Input Current Differential Input Threshold Voltage Input Hysteresis Voltage (VTH+ − VTH−) Input Resistance Input Current (A, B) Logic Enable Input Current CMOS Low-Level Output Voltage R = ∞ (Figure 1) R = 50Ω (Figure 1), RS-422 R = 27Ω (Figure 1), RS-485 VTEST = −7V to + 12V (Figure 2) R = 27Ω or 50Ω (Figure 1 ), (Note 7) R = 27Ω or 50Ω (Figure 1), (Note 7) R = 27Ω or 50Ω (Figure 1), (Note 7) −0.2 2 1.5 1.5 −0.2 5 5 5 5 0.2 3 0.2 V V V V V V V Parameter Conditions Min Typ Max Units
IOSD VINL VINH IIN VTH ∆VTH RIN IIN IRE VOL
VO = High, −7V≤VCM ≤+12V VO = Low, −7V ≤VCM ≤+12V DE, DI, RE DE, DI, RE DE, DI −7V ≤ VCM ≤ + 12V VCM = 0 −7V ≤ VCM ≤ + 12V VIN = 12V VIN = −7V RE IOL = 4mA
−250 −250
250 250 0.8
mA V V
2 −1 −0.2 70 12 1 −0.8 −1 1 0.4 1 +0.2
µA V mV kΩ mA µA V
Receiver Section
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LMS1485
Electrical Characteristics
Symbol VOH IOSR IOZ Parameter CMOS High-Level Output Voltage Short-Circuit Output Current Tristate Output Leakage Current Supply Current
(Continued) Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Conditions IOH = −4mA VO = GND or VCC 0.4V ≤VO ≤+2.4V Min 4 7 −1 85 1 Typ Max Units V mA µA
Power Supply Current ICC Driver Enabled, Output = No Load, Digital Inputs = GND or VCC Driver Disabled, Output = No Load, Digital Inputs = GND or VCC Switching Characteristics Driver TPLH, TPHL TSKEW TR, TF TENABLE TDISABLE Receiver TPLH, TPHL TSKEW TENABLE TDISABLE Propagation Delay Input to Output Receiver Output Skew Receiver Enable Time Receiver Disable Time CL = 15pF (Figure 5, Figure 7) (Figure 5, Figure 7) (Figure 6, Figure 10) (Figure 6, Figure 10) 18 33 2 6 15 25 25 55 ns ns ns ns Propagation Delay Input to Output Driver Output Skew Driver Rise and Fall Time Driver Enable to Ouput Valid Time Output Disable Time RL = 54Ω, CL = 100pF (Figure 3, Figure 7) RL = 54Ω, CL = 100pF (Figure 3, Figure 7) RL = 100Ω, CL = 100pF (Figure 3, Figure 7) (Figure 4, Figure 8) (Figure 4, Figure 8) 11 1 5 18 20 10 32 40 20 ns ns ns ns ns 1.1 1 2.2 2.2 mA mA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics Note 2: All voltage values, except differential I/O bus voltage, are with respect to network ground terminal. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board. Note 4: ESD rating based upon human body model, 100pF discharged through 1.5kΩ. Note 5: Voltage limits apply to DI, DE, RE pins. Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B. Note 7: |∆VOD| and |∆VOC| are changes in magnitude of VOD and VOC, respectively when the input changes from high to low levels. Note 8: ESD rating applies to pins 6 and 7 Note 9: ESD rating applies to pins 1, 2, 3, 4, 5 and 8
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LMS1485
Typical Performance Characteristics
Receiver Output Low Voltage vs. Output Current Receiver Output High Voltage vs. Output Current
20048813
20048814
Receiver Output High Voltage vs. Temperature
Receiver Output Low Voltage vs. Temperature
20048815
20048816
Driver Differential Output Voltage vs. Output Current
Driver Differential Output Voltage vs. Temperature RL = 54Ω
20048817
20048818
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LMS1485
Typical Performance Characteristics
Driver Output Low Voltage vs. Output Current
(Continued) Driver Output High Voltage vs. Output Current
20048819
20048820
Supply Current vs. Temperature
Receiver Skew vs. Temperature
20048821
20048822
Driver Skew vs. Temperature
20048823
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LMS1485
Parameter Measuring Information
20048803
FIGURE 1. Test Circuit for VOD and VOC
20048804
FIGURE 2. Test Circuit for VOD3
20048805
FIGURE 3. Test Circuit for Driver Propagation Delay
20048806
FIGURE 4. Test Circuit for Driver Enable / Disable
20048807
FIGURE 5. Test Circuit for Receiver Propagation Delay
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LMS1485
Parameter Measuring Information
(Continued)
20048808
FIGURE 6. Test Circuit for Receiver Enable / Disable
Switching Characteristics
20048811 20048809
FIGURE 9. Receiver Propagation Delay
FIGURE 7. Driver Propagation Delay, Rise / Fall Time
20048812 20048810
FIGURE 10. Receiver Enable / Disable Time FIGURE 8. Driver Enable / Disable Time
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LMS1485
Application Information
POWER LINE NOISE FILTERING A factor to consider in designing power and ground is noise filtering. A noise filtering circuit is designed to prevent noise generated by the integrated circuit (IC) as well as noise entering the IC from other devices. A common filtering method is to place by-pass capacitors (Cbp) between the power and ground lines. Placing a by-pass capacitor (Cbp) with the correct value at the proper location solves many power supply noise problems. Choosing the correct capacitor value is based upon the desired noise filtering range. Since capacitors are not
ideal, they may act more like inductors or resistors over a specific frequency range. Thus, many times two by-pass capacitors may be used to filter a wider bandwidth of noise. It is highly recommended to place a larger capacitor, such as 10µF, between the power supply pin and ground to filter out low frequencies and a 0.1µF to filter out high frequencies. By pass-capacitors must be mounted as close as possible to the IC to be effective. Long leads produce higher impedance at higher frequencies due to stray inductance. Thus, this will reduce the by-pass capacitor’s effectiveness. Surface mounted chip capacitors are the best solution because they have lower inductance.
20048824
FIGURE 11. Placement of by-pass Capacitors, Cbp
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LMS1485 5V Low Power RS-485 Differential Bus Transceiver
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Pin SOIC NS Package Number M08A
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