LMS485E Low Power RS-485 / RS-422 Differential Bus Transceiver
November 2003
LMS485E Low Power RS-485 / RS-422 Differential Bus Transceiver
General Description
The LMS485E is a low power differential bus/line transceiver designed for high speed bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines. It meets ANSI Standards TIA/EIA RS422-B, TIA/EIA RS485-A and ITU recommendation and V.11 and X.27. The driver outputs and receiver inputs have ± 15kV ESD protection. The LMS485E combines a TRISTATE™ differential line driver and differential input receiver, both of which operate from a single 5.0V power supply. The driver and receiver have an active high and active low, respectively, that can be externally connected to function as a direction control. The driver outputs and receiver inputs are internally connected to form a differential input/output (I/O) bus port that is designed to offer minimum loading to bus whenever the driver is disabled or when VCC = 0V. These ports feature wide positive and negative common mode voltage ranges, making the device suitable for multipoint applications in noisy environments. The LMS485E is available in 8-Pin SOIC and 8-pin DIP packages. It is a drop-in replacement to Maxim’s MAX485E.
Features
n n n n n n n n n n n n Meet ANSI standard RS-485 and RS-422 Data rate 2.5 Mbps Single supply voltage operation, 5V Wide input and output voltage range Thermal shutdown protection Short circuit protection Low quiescent current 800µA (max) Allows up to 32 transceivers on the bus Open circuit fail-safe for receiver Extended operating temperature range −40˚C to 85˚C Drop-in replacement to MAX485E Available in 8-pin SOIC and 8-pin DIP packages
Applications
n n n n n n n n Low power RS-485 systems Network hubs, bridges, and routers Point of sales equipment (ATM, barcode scanners,…) Local area networks (LAN) Integrated service digital network (ISDN) Industrial programmable logic controllers High speed parallel and serial applications Multipoint applications with noisy environment
Typical Application
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A typical multipoint application is shown in the above figure. Terminating resistor, RT are typically required but only located at the two ends of the cable. Pull-up and pull-down resistors maybe required at the end of the bus to provide fail-safe biasing. The biasing resistors provide a bias to the cable when all drivers are in TRI-STATE, See National Application Note, AN-847 for further information.
© 2003 National Semiconductor Corporation
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LMS485E
Connection Diagram
8-Pin SOIC / DIP
20086602
Top View
Truth Table
DRIVER SECTION RE* X X X RECEIVER SECTION RE* L L H L
Note: * = Non Terminated, Open Input only X = Irrelevant Z = TRI-STATE H = High level L = Low level
DE H H L DE L L X L
DI H L X A-B ≥ +0.2V ≤ −0.2V X OPEN *
A H L Z
B L H Z RO H L Z H
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LMS485E
Pin Descriptions
Pin # I/O 1 2 3 O I I Name RO RE* DE Function Receiver Output: If A > B by 200 mV, RO will be high; If A < B by 200 mV, RO will be low. RO will be high also if the inputs (A and B) are open (non-terminated). Receiver Output Enable: RO is enabled when RE* is low; RO is in TRI-STATEwhen RE* is high Driver Output Enable: The driver outputs (A and B) are enabled when DE is high; they are in TRI-STATETRI-STATE ® when DE is low. Pins A and B also function as the receiver input pins (see below) Driver Input: A low on DI forces A low and B high while a high on DI forces A high and B low when the driver is enabled Ground Non-inverting Driver Output and Receiver Input pin. Driver output levels conform to RS-485 signaling levels Inverting Driver Output and Receiver Input pin. Driver Output levels conform to RS-485 signaling levels Power Supply: 4.75V ≤ VCC ≤ 5.25V
4 5 6 7 8
I NA I/O I/O NA
DI GND A B VCC
Ordering Information
Package Part Number LMS485ECM 8-Pin SOIC LMS485ECMX LMS485EIM LMS485EIMX 8-Pin DIP LMS485ECNA LMS485EINA Package Marking LMS485ECM LMS485EIM LMS485ECNA LMS485EINA Transport Media 95 Units/Rail 2.5k Units Tape and Reel 95 Units/Rail 2.5k Units Tape and Reel 40 Units/Rail 40 Units/Rail N08E M08A NSC Drawing
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LMS485E
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage, VCC (Note 2) Input Voltage, VIN (DI, DE, or RE) Voltage Range at Bus Terminals (AB) Receiver Output Package Thermal Impedance, θJA SOIC DIP Junction Temperature (Note 3) Operating Free-Air Temperature Range, TA Commercial Industrial Storage Temperature Range Soldering Information Infrared or Convection (20 sec.) Lead Temperature Range 235˚C +260˚C 0˚C to 70˚C −40˚C to 85˚C −65˚C to 150˚C 125˚ C/W 92˚ C/W 150˚C Supply Voltage, VCC Voltage at any Bus Terminal (Separately or Common Mode) High-Level Input Voltage, VIH (Note 5) Low-Level Input Voltage, VIL (Note 5) Differential Input Voltage, VID (Note 6) 6V −0.3V to VCC + 0.3V −7V to 12V −0.3V to VCC + 0.3V ESD Rating (Human Body Model)(Note 4) Bus Pins Other Pins ESD Rating (Machine Model) All Pins 200V 15kV 2kV
Operating Ratings
Min Nom Max 4.75 −7 2 0.8 5.0 5.25 12 V V V V V
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Electrical Characteristics
Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Symbol Driver Section |VOD1| |VOD2| ∆VOD Differential Output Voltage Differential Output Voltage Change in Magnitude of Driver Differential Output Voltage for Complementary Output States Common Mode Output Voltage R = ∞ (Figure 1) R = 50Ω (Figure 1) , RS-422 R = 27Ω (Figure 1) , RS-485 R = 27Ω or 50Ω (Figure 1) , (Note 7) 2.0 1.5 5.0 0.2 V 5.25 V V Parameter Conditions Min Typ Max Units
VOC ∆VOC
R = 27Ω or 50Ω (Figure 1)
3.0 0.2
V V
Change in Magnitude of R = 27Ω or 50Ω (Figure 1), (Note 7) Driver Common-Mode Output Voltage for Complementary Output States CMOS Input Logic Threshold High CMOS Input Logic Threshold Low Logic Input Current Input Current (A, B) DE, DI, RE DE, DI, RE DE, DI, RE DE = 0V, VCC = 0V or 5.25V VIN = 12V VIN = − 7V −7V ≤ VCM ≤ + 12V VCM = 0 IOH = 4 mA, VID = −200 mV 3.5 −0.2 95 2.0
VIH VIL IIN1 IIN2
V 0.8
V µA mA
±2
0.25 −0.2 +0.2
Receiver Section
VTH ∆VTH VOH
Differential Input Threshold Voltage Input Hysteresis (VTH+− VTH−) CMOS High-level Output Voltage
V mV V
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LMS485E
Electrical Characteristics
Symbol VOL IOZR RIN ICC IOSD1 IOSD2 IOSR Parameter CMOS Low-level Output Voltage Tristate Output Leakage Current Input Resistance Supply Current Driver Short-circuit Output Current Driver Short-circuit Output Current Receiver Short-circuit Output Current
(Continued) Over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) Conditions IOL = −4 mA, VID = 200 mV 0.4V ≤ VO ≤ + 2.4V − 7V ≤VCM ≤ +12V DE = VCC, RE = GND or VCC DE = 0V, RE = GND or VCC VO = high, −7V ≤ VCM ≤ +12V VO = low, − 7V ≤VCM ≤ +12V 0 V ≤ VO ≤ VCC 12 400 360 800 560 250 250 95 mA mA mA Min Typ Max 0.4 Units V µA kΩ µA
±1
Power Supply Current
Switching Characteristics Driver TPLH, TPHL TSKEW TR, TF TZH, TZL THZ, TLZ Receiver TPLH, TPHL TSKEW TZH, TZL THZ, TLZ FMAX Propagation Delay Input to Output Receiver Output Skew Receiver Enable Time Receiver Disable Time Maximum Data Rate RL = 54Ω, CL = 100 pF RL = 54Ω, CL = 100 pF CL = 15 pF CL = 15 pF 2.5 20 90 5 20 20 50 50 200 ns ns ns ns Mbps Propagation Delay Input to Output Driver Output Skew Driver Rise and Fall Time Driver Enable to Ouput Valid Time Driver Output Disable Time RL = 54Ω, CL = 100 pF RL = 54Ω, CL = 100 pF RL = 54Ω, CL = 100 pF CL = 100 pF CL = 15 pF 3 10 40 5 10 25 35 80 10 40 70 70 ns ns ns ns ns
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Note 2: All voltage values, except differential I/O bus voltage, are with respect to the network ground terminal. Note 3: The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient temperature, TA, is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board. Note 4: ESD rating based upon human body model, 100 pF discharged through 1.5 kΩ. Note 5: Voltage limits apply to DI, DE, RE pins. Note 6: Differential input/output bus voltage is measured at the non-inverting terminal A with respect to the inverting terminal B. Note 7: |∆VOD| and |∆VOC| are changes in magnitude of VOD and VOC, respectively when the input changes from high to low levels. Note 8: Peak current
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LMS485E
Typical Performance Characteristics
Output Current vs. Receiver Output Low Voltage Output Current vs. Receiver Output High Voltage
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Receiver Output High Voltage vs. Temperature
Receiver Output Low-Voltage vs. Temperature
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Driver Output Current vs. Differential Output Voltage
Driver Differential Output Voltage vs. Temperature
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LMS485E
Typical Performance Characteristics
Output Current vs. Driver Output Low Voltage
(Continued) Output Current vs. Driver Output High Voltage
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Supply Current vs. Temperature
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LMS485E
Parameter Measuring Information
20086603
FIGURE 1. Test Circuit for VOD and VOC
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FIGURE 2. Test Circuit for VOD3
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FIGURE 3. Test Circuit for Driver Propagation Delay
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FIGURE 4. Test Circuit for Driver Enable / Disable
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Parameter Measuring Information
(Continued)
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FIGURE 5. Test Circuit for Receiver Propagation Delay
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FIGURE 6. Test Circuit for Receiver Enable / Disable
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LMS485E
Switching Characteristics
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FIGURE 9. Receiver Propagation Delay
FIGURE 7. Driver Propagation Delay, Rise / Fall Time
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FIGURE 10. Receiver Enable / Disable Time FIGURE 8. Driver Enable / Disable Time
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LMS485E
Application Information
POWER LINE NOISE FILTERING A factor to consider in designing power and ground is noise filtering. A noise filtering circuit is designed to prevent noise generated by the integrated circuit (IC) as well as noise entering the IC from other devices. A common filtering method is to place by-pass capacitors (Cbp) between the power and ground lines. Placing a by-pass capacitor (Cbp) with the correct value at the proper location solves many power supply noise problems. Choosing the correct capacitor value is based upon the desired noise filtering range. Since capacitors are not
ideal, they may act more like inductors or resistors over a specific frequency range. Thus, many times two by-pass capacitors may be used to filter a wider bandwidth of noise. It is highly recommended to place a larger capacitor, such as 10µF, between the power supply pin and ground to filter out low frequencies and a 0.1µF to filter out high frequencies. By-pass capacitors must be mounted as close as possible to the IC to be effective. Longs leads produce higher impedance at higher frequencies due to stray inductance. Thus, this will reduce the by-pass capacitor’s effectiveness. Surface mounted chip capacitors are the best solution because they have lower inductance.
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FIGURE 11. Placement of by-pass Capacitors, Cbp
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LMS485E
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Pin SOIC NS Package Number M08A
8-Pin DIP NS Package Number N08E
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LMS485E Low Power RS-485 / RS-422 Differential Bus Transceiver
Notes
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