LMV115MGX

LMV115 GSM Baseband 30MHz 2.8V Oscillator Buffer December 2003 LMV115 GSM Baseband 30MHz 2.8V Oscillator Buffer General Description The LMV115 is a 30MHz buffer specially designed to minimize the effects of spurious signals from the base band chip to the oscillator. The buffer also minimizes the influence of varying load resistance and capacitance to the oscillator and increases the drive capability. The input of the LMV115 is internally biased with two equal resistors to the power supply rails. This allows AC coupling on the input. The LMV115 offers a shutdown function to optimize current consumption. This shutdown function can also be used to control the supply voltage of an external oscillator. The device is in shutdown mode when the shutdown pin is connected to VDD. The LMV115 comes in SC70-6 package. This space saving product reduces components, improves clock signal and allows ease of placement for the best form factor. Features (Typical 2.8V supply; values unless otherwise specified) n Low supply current: 0.3mA n 2.5V to 3.3V supply n AC coupling possible without external bias resistors. n Includes shutdown function external oscillator n SC70-6 pin package 2.1 x 2mm n Operating Temperature Range −40˚C to 85˚C Applications n Cellular phones n GSM Modules n Oscillator Modules Schematic Diagram 20075129 © 2003 National Semiconductor Corporation DS200751 www.national.com LMV115 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance Human Body Model Machine Model Supply Voltage (V+ – V−) Output Short Circuit to V + Junction Temperature (Note 6) Mounting Temperature Infrared or Convection (20 sec.) +150˚C 235˚C 2000V (Note 2) 150V (Note 3) 3.6V (Note 4), (Note 5) (Note 4), (Note 5) −65˚C to +150˚C Operating Ratings (Note 1) Supply Voltage (V+ – V−) Temperature Range (Note 6), (Note 7) SC70-6 2.5V to 3.3V −40˚C to +85˚C 414˚C/W Package Thermal Resistance (Note 6), (Note 7) Output Short Circuit to V− Storage Temperature Range 2.8V Electrical Characteristics Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 2.8V, V− = 0V, VCM = V+/2, shutdown = 0.0V, and RL = 50kΩ to V+/2, CL = 5pF to V+/2 and CCOUPLING = 1nF.Boldface limits apply at the temperature extremes. Symbol SSBW GFN FPBW tr tf ts OS SR HD2 HD3 THD en Isolation Parameter Small Signal Bandwidth Gain Flatness < 0.1dB Full Power Bandwidth (−3dB) Rise Time Fall Time Settling Time to 0.1% Overshoot Slew Rate 2nd Harmonic Distortion 3rd Harmonic Distortion Total Harmonic Distortion Input-Referred Voltage Noise Output to Input 0.1VSTEP 0.1VSTEP (Note 11) VOUT = 500mVPP; f = 100kHz VOUT = 500mVPP; f = 100kHz VOUT = 500mVPP; f = 100kHz f = 1MHz See also Typical Performance Characteristics VOUT = 100mVPP 0.90 0.85 f > 50kHz VOUT = 1.0VPP (+4.5dBm) 0.1VSTEP (10-90%) Conditions VOUT < 0.5VPP; −3dB Min (Note 9) Typ (Note 8) 31 2.8 9 11 11 95 24 18 −41 −43 −38 27 Max (Note 9) Units MHz MHz MHz Time Domain Response ns ns % V/µs dBc dBc dBc nV/ dB Distortion and Noise Performance > 40 Static DC Performance ACL VOS TC VOS ROUT PSRR IS Small Signal Voltage Gain Output Offset Voltage Temperature Coefficient Output Offset Voltage Output Resistance Power Supply Rejection Ratio Supply Current (Note 12) f = 10kHz f = 25MHz V+ = 2.8V to V+ = 3.3V No Load; Shutdown = 2.8V No Load; Shutdown = 0V Miscellaneous Performance RIN CIN Input Resistance Input Capacitance Shutdown = 2.8V Shutdown = 0V Shutdown = 2.8V Shutdown = 0V 65 64 1.82 1.50 kΩ pF 41 38 0.998 3.5 102 61 330 42 0.0 314 2.00 450 520 µA 1.10 1.11 35 55 V/V mV µV/˚C Ω dB www.national.com 2 LMV115 2.8V Electrical Characteristics (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C, V+ = 2.8V, V− = 0V, VCM = V+/2, shutdown = 0.0V, and RL = 50kΩ to V+/2, CL = 5pF to V+/2 and CCOUPLING = 1nF.Boldface limits apply at the temperature extremes. Parameter Input Impedance Output Swing Positive Output Swing Negative Conditions f = 25MHz; Shutdown = 2.8V f = 25MHz; Shutdown = 0V RL = 50kΩ to V+/2 RL = 50kΩ to V /2 + Symbol ZIN VO Min (Note 9) Typ (Note 8) 2.38 2.47 Max (Note 9) Units kΩ 1.90 1.65 2.16 1.05 1.35 1.30 V IO Linear Output Current No Load; VOUT = V+ − 1.1V (Sourcing) No Load; VOUT = V− + 1.1V (Sinking) −90 −35 100 50 −90 −35 100 50 −206 µA 205 −186 µA 191 21 40 45 Ω ISC Output Short-Circuit Current (Note 5) No Load; Sourcing to V+/2 No Load; Sinking from V+/2 RON Switch in ON Position Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics. Note 2: Human Body Model (HBM) is 1.5kΩ in series with 100pF. Note 3: Machine Model, 0Ω in series with 200pF. Note 4: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C Note 5: Infinite Duration; Short circuit test is a momentary test. See next note. Note 6: The maximum power dissipation is a function of TJ(MAX), θJA , and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) -TA) / θJA. All numbers apply for packages soldered directly onto a PC board. Note 7: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA . There is no guarantee of parametric performance as indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Applications section for information on temperature de-rating of this device. Note 8: Typical Values represent the most likely parametric norm. Note 9: All limits are guaranteed by testing or statistical analysis. Note 10: Positive current corresponds to current flowing into the device. Note 11: Slew rate is the average of the positive and negative slew rate. Note 12: Average Temperature Coefficient is determined by dividing the change in a parameter at temperature extremes by the total temperature change. 3 www.national.com LMV115 Connection Diagram SC70-6 20075130 Top View Ordering Information Package Part Number LMV115MG LMV115MGX Package Marking Transport Media 250 Units Tape and Reel 3k Units Tape and Reel NSC Drawing SC70-6 B04 MAA06A www.national.com 4 LMV115 Typical Performance Characteristics connected to V /2; Unless otherwise specified. Frequency and Phase Response + TJ = 25˚C, V+ = 2.8V, V− = 0V, VCM = V+/2, and RL, CL is Frequency Response Over Temperature 20075103 20075104 Phase Response Over Temperature Gain Flatness 0.1dB 20075114 20075106 Full Power Bandwidth Transient Response Positive 20075105 20075119 5 www.national.com LMV115 Typical Performance Characteristics TJ = 25˚C, V+ = 2.8V, V− = 0V, VCM = V+/2, and RL, CL is connected to V+/2; Unless otherwise specified. (Continued) Transient Response Negative Harmonic Distortion vs. VOUT @ 100kHz 20075118 20075107 Harmonic Distortion vs. VOUT @ 500kHz Harmonic Distortion vs. VOUT @ 1MHz 20075109 20075108 THD vs. VOUT for Various Frequencies Voltage Noise 20075117 20075102 www.national.com 6 LMV115 Typical Performance Characteristics TJ = 25˚C, V+ = 2.8V, V− = 0V, VCM = V+/2, and RL, CL is connected to V+/2; Unless otherwise specified. (Continued) ROUT vs. Frequency Input Impedance vs. Frequency 20075101 20075111 Isolation Output to Input VOUT vs. IOUT (Sinking) 20075112 20075120 VOUT vs. IOUT (Sourcing) ISC Sourcing vs. VSUPPLY 20075121 20075122 7 www.national.com LMV115 Typical Performance Characteristics TJ = 25˚C, V+ = 2.8V, V− = 0V, VCM = V+/2, and RL, CL is connected to V+/2; Unless otherwise specified. (Continued) ISC Sinking vs. VSUPPLY VOS vs. VSUPPLY for 3 Units 20075123 20075124 VOS vs. VSUPPLY for Unit 1 VOS vs. VSUPPLY for Unit 2 20075125 20075126 VOS vs. VSUPPLY for Unit 3 ISUPPLY vs. VSUPPLY 20075127 20075128 www.national.com 8 LMV115 Typical Performance Characteristics TJ = 25˚C, V+ = 2.8V, V− = 0V, VCM = V+/2, and RL, CL is connected to V+/2; Unless otherwise specified. (Continued) PSRR vs. Frequency Small Signal Pulse Response 20075115 20075116 Large Signal Pulse Response 20075113 9 www.national.com LMV115 Application Section GENERAL The LMV115 is specially designed to minimize the effects of spurious signals from the base band chip to the oscillator. Beside this the influence of varying load resistance and capacitance to the oscillator is minimized, while increasing the drive capability. The input of the LMV115 is internally biased with two equal resistors to the power supply rails, and makes AC coupling possible without external bias resistors at the input. The LMV115 has excellent gain phase margin. The LMV115 offers a shutdown pin that can be used to disable the device in order to optimize current consumption and also has a feature to control the supply voltage to an external oscillator. When the shutdown pin is connected to VDD the device is in shutdown mode. SWITCHED POWER SUPPLY CONNECTION The LMV115 features an enable/disable function for an external oscillator by controlling its supply voltage (pin 4). See also the schematic diagram on the front page. During normal operating mode, pin 4 is connected to the positive supply rail via an internal switch. The resistance between the positive supply rail and pin 4, RON, is specified in the electrical characterization table. Oscillators with a supply current up to several milliamps can easily be powered from pin 4. During shutdown, pin 4 is switched to the negative supply rail. The simplified schematic for this part of the device is shown in Figure 1 20075132 FIGURE 2. Dual Supply Mode PSRR If an AC signal is applied to one of the supply lines, while the input is floating, the signal at the input pin is half the signal at the supply line, causing the same signal at the output of the buffer. This will result in a PSRR of only 6dB (see Figure 2). In a typical application the input is driven from a low ohmic source that means the disturbance at the supply lines is attenuated by the series resistors of 110k and the source impedance. In case the buffer is connected to a 50Ω source, the resulting suppression will be 20*log [(R1 + RBIAS)/RBIAS] = 67dB for signals at the supply line. The PSRR can also be measured correctly for this type of input by shorten the input to mid-supply. Due to the internal structure it is not recommended to measure with the input connected to ground. To measure correctly the PSRR, two signals are applied to both VDD and VEE but with 180˚ phase difference (see Figure 2). In this case, both signals are subtracted and there will be no signal at the input. The resulting disturbance at the output is now only caused by the signals at the supply lines. INPUT AND OUTPUT LEVEL Due to the internal loop gain of 1, the output will follow the input. The output voltage cannot swing as close to the supply rail as the input voltage. For linear operation the input voltage swing should not exceed the output voltage swing. The restrictions for the output voltage can be examined by the two curves in Figure 3. The curve VOUT (V) shows the response of the output signal versus the input signal and the curve VOUT – VIN (V) shows the difference between the output and the input signal. 20075131 FIGURE 1. Supply For External Oscillator INPUT CONFIGURATION The input of the LMV115 is internally biased at mid-supply by a divider of two equal resistors. With the LMV115 in shutdown mode, the internal resistor connected to the VDD is shortened to the negative power supply rail via a switch. This makes the power consumption in ‘off’ mode almost zero, but causes a small difference for the input impedance between the on and off modes. Both resistors are 110kΩ so the resulting input impedance will be approximately 55kΩ. The input configuration allows AC coupling on the input of the LMV115. A simplified schematic of the input is shown in Figure 2. www.national.com 10 LMV115 Application Section (Continued) DRIVING RESISTIVE AND CAPACITIVE LOADS The maximum output current of the LMV115 is about 200µA which means the output can drive a maximum load of 1V/ 200µA = 5kΩ. Using lower load resistances will exceed the maximum linear output current. The LMV115 can drive a small capacitive load, but make sure that every capacitor directly connected to the output becomes part of the loop of the buffer and will reduce the gain/phase margin, increasing the instability at higher capacitive values. This will lead to peaking in the frequency response and in extreme situations oscillations can occur. A good practice when driving larger capacitive loads is to include a series resistor to the load capacitor. A to D converters present complex and varying capacitive loads to the buffer. The best value for this isolation resistance is often found by experimentation. SHUTDOWN MODE LMV115 offers a shutdown function that can be used to disable the device and to optimize current consumption. Switching between the normal mode and the shutdown mode requires connecting the shutdown pin either to the negative or the positive supply rail. If directly connected to one of the supply rails, the part is guaranteed in the correct mode. But if the shutdown pin is driven by other output stages, there is a voltage range in which the installed mode is not certainly set and it is recommended not to drive the shutdown pin in this voltage range. As can be seen in Figure 5 this hysteresis varies from 1V to 1.6V. Below 1V the LMV115 is securely ‘ON’ and above 1.6V securely ‘OFF’ while using a supply voltage of 2.8V. 20075133 FIGURE 3. VOUT – VIN In Figure 3 the input signal is swept between both supply rails (0V - 2.8V). The linear part of the plot ‘VOUT vs. VIN’ covers approximately the voltage range between 1.0V and 2.0V. If a difference of 50mV between output and input is acceptable, the output range is between 1.05V and 2.15V (see curve VOUT – VIN). Alternatively the output voltage swing can be determined by using Figure 4. In the plot ‘Gain vs. VIN’ it can be seen that the gain is flat for input voltages from 1.15V till 2.1V. Outside this range the gain differs from 1. This will introduce distortion of the output signal. 20075135 FIGURE 5. Hysteresis PRINTED CIRCUIT BOARD LAYOUT AND COMPONENT VALUES SELECTION For a good high frequency design both the active parts and the passive ones should be suitable for the purpose they are used for. Amplifying high frequencies is possible with standard through-hole components, but for frequencies above several hundreds of MHz the best choice is using surface mount devices. Nowadays designs are often assembled with surface mount devices for the aspect of minimizing space, but this also greatly improves the performance of designs, handling high frequencies. Another important issue is the PCB, which is no longer a simple carrier for all the parts and a medium to interconnect them. The board becomes a real 20075134 FIGURE 4. Gain Another point is the DC bias voltage necessary to get the optimum output voltage swing. As discussed above, the output voltage swing can be 1VPP, but if the two internal bias resistors are used, the DC bias will be 1.4V, which is half of the supply voltage of 2.8V. In this situation the output swing will exceed the lower limit of 1.15V, so it is necessary to introduce a small DC offset of 200mV to make use of the full output swing range of the output stage. 11 www.national.com LMV115 Application Section (Continued) causes a significant increase in power consumption, while loading inputs or outputs to heavily. NSC suggests the following evaluation board as a guide for high frequency layout and as an aid in device testing and characterization. Device LMV115 Package SC70-6 Evaluation Board PN LMV115/117 Eval Board part itself, adding its own high frequency properties to the overall performance of the circuit. It is good practice to have at least one ground plane on a PCB giving a low impedance path for all decoupling and other ground connections. In order to achieve high immunity for unwanted signals from outside, it is important to place the components as flat as possible on the PCB. Be aware that a long lead can act as an inductor, a capacitor or an antenna. A pair of leads can even form a transformer. Careful design of the PCB avoids oscillations or other unwanted behavior. Another important issue is the value of components, which also determines the sensitivity to pick-up unwanted signals. Choose the value of resistors as low as possible, but avoid using values that This free evaluation board is shipped when a device sample request is placed with National Semiconductor. www.national.com 12 LMV115 GSM Baseband 30MHz 2.8V Oscillator Buffer Physical Dimensions inches (millimeters) unless otherwise noted NS Package Number MAA06A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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