LMX2305

LMX2305 PLLatinum 550 MHz Frequency Synthesizer for RF Personal Communications PRELIMINARY August 1996 LMX2305 PLLatinum TM 550 MHz Frequency Synthesizer for RF Personal Communications General Description The LMX2305 is a high performance frequency synthesizer with an integrated prescaler designed for RF operation up to 550 MHz It is fabricated using National’s ABiC IV BiCMOS process The LMX2305 contains a dual modulus prescaler which can select either a 64 65 or a 128 129 divide ratio at input frequencies of up to 550 MHz LMX2305 which employs the digital phase lock loop technique combined with a high quality reference oscillator and a loop filter provides the tuning voltage for the voltage controlled oscillator to generate a very stable low noise local oscillator signal Serial data is transferred into the LMX2305 via a three line MICROWIRETM interface (Data Enable Clock) Supply voltage can range from 2 65V to 5 5V The LMX2305 features very low current consumption typically 4 0 mA at 2 75V The LMX2305 is available in a TSSOP 20-pin surface mount plastic package Features Y Y Y Y Y Y RF operation up to 550 MHz 2 65V to 5 5V operation Low current consumption ICC e 4 0 mA (typ) at VCC e 2 75V Dual modulus prescaler 64 65 or 128 129 Internal balanced low leakage charge pump Small-outline plastic surface mount TSSOP 0 173 wide package Applications Y Y Y Y Y Analog Cellular telephone systems (AMPS ETACS NMT) Portable wireless communications (PCS PCN cordless) Wireless local area networks (WLANs) Other wireless communication systems Pagers Block Diagram TL W 12459 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation MICROWIRETM and PLLatinumTM are trademarks of National Semiconductor Corporation C1996 National Semiconductor Corporation TL W 12459 RRD-B30M126 Printed in U S A http www national com Connection Diagram LMX2305 TL W 12459 – 2 20-Lead (0 173 Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2305TM or LMX2305TMX See NS Package Number MTC20 Pin Descriptions Pin No 1 Pin Name OSCIN IO I Description Oscillator input A CMOS inverting gate input intended for connection to a crystal resonator for operation as an oscillator The input has a VCC 2 input threshold and can be driven from an external CMOS or TTL logic gate May also be from a reference oscillator Oscillator output Power supply for charge pump Must be t VCC Power supply voltage input Input may range from 2 65V to 5 5V Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane O Internal charge pump output For connection to a loop filter for driving the input of an external VCO Ground O I I I I Lock detect Output provided to indicate when the VCO frequency is in ‘‘lock’’ When the loop is locked the pin’s output is HIGH with narrow low pulses Prescaler input Small signal input from the VCO High impedance CMOS Clock input Data is clocked in on the rising edge into the various counters and registers Binary serial data input Data entered MSB first LSB is control bit High impedance CMOS input Load enable input (with internal pull-up resistor) When LE transitions HIGH data stored in the shift registers is loaded into the appropriate latch (control bit dependent) Clock must be low when LE toggles high or low See Serial Data Input Timing Diagram Phase control select (with internal pull-up resistor) When FC is LOW the polarity of the phase comparator and charge pump combination is reversed Analog switch output When LE is HIGH the analog switch is ON routing the internal charge pump output through BISW (as well as through Do) Monitor pin of phase comparator input CMOS output Output for external charge pump wp is an open drain N-channel transistor and requires a pull-up resistor Power Down (with internal pull-up resistor) PWDN e HIGH for normal operation PWDN e LOW for power saving Power down function is gated by the return of the charge pump to a TRI-STATE condition Output for external charge pump wr is a CMOS logic output No connect 3 4 5 6 7 8 10 11 13 14 OSCOUT VP VCC Do GND LD fIN CLOCK DATA LE O 15 16 17 18 19 FC BISW fOUT wp PWDN I O O O I 20 2 9 12 wr NC O http www national com 2 Functional Block Diagram TL W 12459 – 3 Note 1 The power down function is gated by the charge pump to prevent any unwanted frequency jumps Once the power down pin is brought low the part will go into power down mode when the charge pump reaches a TRI-STATE condition 3 http www national com Absolute Maximum Ratings (Notes 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Power Supply Voltage VCC VP Voltage on Any Pin with GND e 0V (VI) Storage Temperature Range (TS) Lead Temperature (TL) (solder 4 sec ) b 0 3V to a 6 5V b 0 3V to a 6 5V b 0 3V to VCC a 0 3V b 65 C to a 150 C a 260 C Recommended Operating Conditions Power Supply Voltage VCC VP Operating Temperature (TA) 2 65V to 5 5V VCC to a 5 5V b 40 C to a 85 C Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur Operating Ratings indicate conditions for which the device is intended to be functional but do not guarantee specific performance limits For guaranteed specifications and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Note 2 This device is a high performance RF integrated circuit with an ESD rating k 2 keV and is ESD sensitive Handling and assembly of this device should only be done at ESD workstations Electrical Characteristics VCC e 2 75V Symbol ICC ICC-PWDN fIN fOSC fw PfIN VOSC VIH VIL IIH IIL IIH IIL IIH IIL High-Level Input Current (LE FC) Low-Level Input Current (LE FC) Parameter Power Supply Current Power Down Current RF Input Operating Frequency Oscillator Input Operating Frequency Phase Detector Frequency Input Sensitivity Oscillator Sensitivity High-Level Input Voltage Low-Level Input Voltage High-Level Input Current (Clock Data) Low-Level Input Current (Clock Data) Oscillator Input Current VP e 2 75V b40 C k TA k 85 C except as specified Conditions Min Typ 4 30 45 5 VCC e 2 65V to 5 5V OSCIN b 10 Max 6 180 550 22 10 a6 Units mA mA MHz MHz MHz dBm VPP V 05 0 7 VCC 0 3 VCC V mA mA mA mA mA mA VIH e VCC e 5 5V VIL e 0V VCC e 5 5V VIH e VCC e 5 5V VIL e 0V VCC e 5 5V VIH e VCC e 5 5V VIL e 0V VCC e 5 5V b1 0 b1 0 10 10 100 b 100 b1 0 b 100 10 10 Except fIN and OSCIN http www national com 4 Electrical Characteristics VCC e 2 75V Symbol IDo-source IDo-sink IDo-Tri VOH VOL VOH VOL IOL IOH tCS tCH tCWH tCWL tES tEW Charge Pump TRI-STATE Current High-Level Output Voltage Low-Level Output Voltage High-Level Output Voltage (OSCOUT) Low-Level Output Voltage (OSCOUT) Open Drain Output Current (wp) Open Drain Output Current (wp) Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Enable Set Up Time Enable Pulse Width Parameter Charge Pump Output Current VP e 2 75V b40 C k TA k 85 C except as specified (Continued) Conditions Min Typ b2 5 Max b1 0 Units mA mA VDo e VP 2 VDo e VP 2 0 5V s VDo s VP b 0 5V TA e b40 C k TA k 85 C IOH e b1 0 mA IOL e 1 0 mA IOH e b200 mA IOL e 200 mA VOL e 0 4V VOH e 2 75V See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing 50 10 50 50 50 50 10 VCC b 0 8 10 b5 0 25 50 nA V VCC b 0 8 04 04 V V V mA 100 mA ns ns ns ns ns ns Except OSCOUT 5 http www national com Functional Description The simplified block diagram below shows the 19-bit data register the 14-bit R Counter and the R15 Latch and the 18-bit N Counter (intermediate latches are not shown) The data stream is clocked (on the rising edge) into the DATA input MSB first If the Control Bit (last bit input) is HIGH the DATA is transferred into the R Counter (programmable reference divider) and the S Latch (prescaler select 64 65 or 128 129) If the Control Bit (LSB) is LOW the DATA is transferred into the N Counter (programmable divider) TL W 12459 – 1 PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (R15 LATCH) If the Control Bit (last bit shifted into the Data Register) is HIGH data is transferred from the 19-bit shift register into a 14-bit latch (which sets the 14-bit R Counter) and the 1-bit R15 Latch which sets the prescaler 64 65 or 128 129 Serial data format is shown below TL W 12459 – 14 14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) Divide R R R R RRRRRRRRRR Ratio 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R 3 4 0 0 0 0 0 0 0 0 0 0 000000011 000000100 1-BIT PRESCALER SELECT (R15 LATCH) Prescaler Select P 128 129 64 65 R 15 0 1 # 16383 # 1 # 1 # 1 # 1 # 1 ######### 111111111 Notes Divide ratios less than 3 are prohibited Divide ratio 3 to 16383 R1 to R14 These bits select the divide ratio of the programmable reference divider C Control bit (set to HIGH level to load R counter and R15 Latch) Data is shifted in MSB first http www national com 6 Functional Description (Continued) PROGRAMMABLE DIVIDER (N COUNTER) The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter) If the Control Bit (last bit shifted into the Data Register) is LOW data is transferred from the 19-bit shift register into a 7-bit latch which sets the 7-bit Swallow (A) Counter and an 11-bit latch which sets the 11-bit programmable (B) Counter Serial data format is shown below TL W 12459 – 15 Note S8 to S18 Programmable counter divide ratio control bits (3 to 2047) 7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) Divide Ratio A 0 1 N 7 0 0 N 6 0 0 N 5 0 0 N 4 0 0 N 3 0 0 N 2 0 0 N 1 0 1 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER) Divide Ratio B 3 4 N 18 0 0 N 17 0 0 N 16 0 0 N 15 0 0 N 14 0 0 N 13 0 0 N 12 0 0 N 11 0 0 N 10 0 1 N 9 1 0 N 8 1 0 # 127 # 1 # 1 # 1 # 1 # 1 # 1 # 1 # 2047 # 1 # 1 # 1 # 1 # 1 # 1 # 1 # 1 # 1 # 1 # 1 Note Divide ratio 0 to 127 BtA Note Divide ratio 3 to 2047 (Divide ratios less than 3 are prohibited) BtA PULSE SWALLOW FUNCTION fVCO e (P c B) a A c fOSC R fVCO Output frequency of external voltage controlled oscillator (VCO) B Preset divide ratio of binary 11-bit programmable counter (3 to 2047) A Preset divide ratio of binary 7-bit swallow counter (0 s A s 127 A s B) fOSC Output frequency of the external reference frequency oscillator R Preset divide ratio of binary 14-bit programmable reference counter (3 to 16383) P Preset modulus of dual modulus prescaler (64 or 128) 7 http www national com Functional Description (Continued) SERIAL DATA INPUT TIMING TL W 12459 – 16 Notes Parenthesis data indicates programmable reference divider data Data shifted into register on clock rising edge Data is shifted in MSB first Test Conditions The Serial Data Input Timing is tested using a symmetrical waveform around VCC 2 The test waveform has an edge rate of 0 6 V ns with amplitudes of 2 2V VCC e 2 7V and 2 6V VCC e 5 5V Phase Characteristics In normal operation the FC pin is used to reverse the polarity of the phase detector Both the internal and any external charge pump are affected Depending upon VCO characteristics FC pin should be set accordingly When VCO characteristics are like (1) FC should be set HIGH or OPEN CIRCUIT When VCO characteristics are like (2) FC should be set LOW When FC is set HIGH or OPEN CIRCUIT the monitor pin of the phase comparator input fout is set to the reference divider output fr When FC is set LOW fout is set to the programmable divider output fp PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS VCO Characteristics TL W 12459 – 17 TL W 12459 – 18 Notes Phase difference detection range b 2q to a 2q The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked FC e HIGH http www national com 8 Analog Switch The analog switch is useful for radio systems that utilize a frequency scanning mode and a narrow band mode The purpose of the analog switch is to decrease the loop filter time constant allowing the VCO to adjust to its new frequency in a shorter amount of time This is achieved by adding another filter stage in parallel The output of the charge pump is normally through the Do pin but when LE is set HIGH the charge pump output also becomes available at BISW A typical circuit is shown below The second filter stage (LPF-2) is effective only when the switch is closed (in the scanning mode) TL W 12459 – 19 Typical Crystal Oscillator Circuit A typical circuit which can be used to implement a crystal oscillator is shown below Typical Lock Detect Circuit A lock detect circuit is needed in order to provide a steady LOW signal when the PLL is in the locked state A typical circuit is shown below TL W 12459 – 20 TL W 12459 – 21 9 http www national com Typical Application Example Operational Notes VCO is assumed AC coupled TL W 12459 – 22 RIN increases impedance so that VCO output power is provided to the load rather than the PLL Typical values are 10X to 200X depending on the VCO power level fIN RF impedance ranges from 40X to 100X 50X termination is often used on test boards to allow use of external reference oscillator For most typical products a CMOS clock is used and no terminating resistor is required OSCIN may be AC or DC coupled AC coupling is recommended because the input circuit provides its own bias (See Figure below) TL W 12459 – 23 Application Hints Proper use of grounds and bypass capacitors is essential to achieve a high level of performance Crosstalk between pins can be reduced by careful board layout This is an electrostatic sensitive device It should be handled only at static free work stations http www national com 10 Application Information LOOP FILTER DESIGN A block diagram of the basic phase locked loop is shown TL W 12459 – 24 FIGURE 1 Basic Charge Pump Phase Locked Loop An example of a passive loop filter configuration including the transfer function of the loop filter is shown in Figure 2 TL W 12459 – 25 Z(s) e s (C2 # R2) a 1 s2 (C1 # C2 # R2) a sC1 a sC2 TL W 12459 – 26 FIGURE 2 2nd Order Passive Filter Define the time constants which determine the pole and zero frequencies of the filter transfer function by letting (1a) T2 e R2 # C2 and C1 # C2 T1 e R2 # C1 a C2 (1b) The PLL linear model control circuit is shown along with the open loop transfer function in Figure 3 Using the phase detector and VCO gain constants Kw and KVCO and the loop filter transfer function Z(s) the open loop Bode plot can be calculated The loop bandwidth is shown on the Bode plot (0p) as the point of unity gain The phase margin is shown to be the difference between the phase at the unity gain point and b180 FIGURE 3 Open Loop Transfer Function Thus we can calculate the 3rd order PLL Open Loop Gain in terms of frequency (2) From equation 2 we can see that the phase term will be dependent on the single pole and zero such that w(0) e tanb1 (0 # T2) b tanb1 (0 # T1) a 180 (3) By setting T2 T1 dw e b e0 d0 1 a (0 # T2)2 1 a (0 # T1)2 (4) we find the frequency point corresponding to the phase inflection point in terms of the filter time constants T1 and T2 This relationship is given in equation 5 G(s) # H(s)ls e j # 0 e b Kw # KVCO (1 a j0 # T2) T1 # 02C1 # N(1 a j0 # T1) T2 0p e 1 0T2 # T1 (5) For the loop to be stable the unity gain point must occur before the phase reaches b180 degrees We therefore want the phase margin to be at a maximum when the magnitude of the open loop gain equals 1 Equation 2 then gives TL W 12459 – 27 Open Loop Gain e ii ie e H(s) G(s) e Kw Z(s) KVCO Ns Closed Loop Gain e io ii e G(s) 1 a H(s) G(s) C1 e Kw # KVCO # T1 (1 a j0p # T2) 0p2 # N # T2 (1 a j0p # T1) (6) 11 http www national com Application Information (Continued) Therefore if we specify the loop bandwidth 0p and the phase margin wp Equations 1 through 6 allow us to calculate the two time constants T1 and T2 as shown in equations 7 and 8 A common rule of thumb is to begin your design with a 45 phase margin secwp b tanwp T1 e 0p (7) (8) From the time constants T1 and T2 and the loop bandwidth 0p the values for C1 R2 and C2 are obtained in equations 9 to 11 T1 Kw # KVCO 1 a (0p # T2)2 # T2 0p2 # N 1 a (0p # T1)2 (9) T2 b1 C2 e C1 # T1 (10) T2 R2 e C2 (11) Voltage Controlled Oscillator (VCO) KVCO (MHz V) Tuning Voltage constant The frequency vs voltage tuning ratio Kw (mA) Phase detector charge pump gain constant The ratio of the current output to the input phase differential N Main divider ratio Equal to RFopt fref C1 e T2 e 1 0p2 # T1 In choosing the loop filter components a trade off must be made between lock time noise stability and reference spurs The greater the loop bandwidth the faster the lock time will be but a large loop bandwidth could result in higher reference spurs Wider loop bandwidths generally improve close in phase noise but may increase integrated phase noise depending on the reference input VCO and division ratios used The reference spurs can be reduced by reducing the loop bandwidth or by adding more low pass filter stages but the lock time will increase and stability will decrease as a result THIRD ORDER FILTER A low pass filter section may be needed for some applications that require additional rejection of the reference sidebands or spurs This configuration is given in Figure 4 In order to compensate for the added low pass section the component values are recalculated using the new open loop unity gain frequency The degradation of phase margin caused by the added low pass is then mitigated by slightly increasing C1 and C2 while slightly decreasing R2 The added attenuation from the low pass filter is ATTEN e 20 log (2qfref # R3 # C3)2 a 1 (12) Defining the additional time constant as T3 e R3 # C3 (13) Then in terms of the attenuation of the reference spurs added by the low pass pole we have 10ATTEN 20 b 1 (14) (2q # fref)2 We then use the calculated value for loop bandwidth 0c in equation 11 to determine the loop filter component values in equations 15 – 17 0c is slightly less than 0p therefore the frequency jump lock time will increase T3 e # 0 J RFopt (MHz) fref (kHz) Radio Frequency output of the VCO at which the loop filter is optimized Frequency of the phase detector inputs Usually equivalent to the RF channel spacing 0 T2 e 1 0c2 # (T1 a T3) tanw # (T1 a T3) # (T1 a T3)2 a T1 # T3 (15) 0c e 01 a (T1 a T3)2 a T1 # T3 b1 tanw # (T1 a T3) 2 ( (16) C1 e T1 Kw # KVCO (1 a 0c2 # T22) # # T2 0c2 # N (1 a 0c2 # T12) (1 a 0c2 # T32) ( (17) http www national com 12 Application Information (Continued) EXTERNAL CHARGE PUMP The LMX PLLatinum series of frequency synthesizers are equipped with an internal balanced charge pump as well as outputs for driving an external charge pump Although the superior performance of NSC’s on board charge pump eliminates the need for an external charge pump in most applications certain system requirements are more stringent In these cases using an external charge pump allows the designer to take direct control of such parameters as charge pump voltage swing current magnitude TRI-STATE leakage and temperature compensation One possible architecture for an external charge pump current source is shown in Figure 9 The signals wp and wr in the diagram correspond to the phase detector outputs of the LMX2305 frequency synthesizer These logic signals are converted into current pulses using the circuitry shown in Figure 9 to enable either charging or discharging of the loop filter components to control the output frequency of the PLL Referring to Figure 9 the design goal is to generate a 5 mA current which is relatively constant to within 0 5V of the power supply rail To accomplish this it is important to establish as large of a voltage drop across R5 R8 as possible without saturating Q2 Q4 A voltage of approximately 300 mV provides a good compromise This allows the current source reference being generated to be relatively repeatable in the absence of good Q1 Q2 Q3 Q4 matching (Matched transistor pairs is recommended ) The wp and wr outputs are rated for a maximum output load current of 1 mA while 5 mA current sources are desired The voltages developed across R4 9 will consequently be approximately 258 mV or 42 mV k R8 5 due to the current density differences 0 026 1n (5 mA 1 mA) through the Q1 Q2 Q3 Q4 pairs In order to calculate the value of R7 it is necessary to first estimate the forward base to emitter voltage drop (Vfn p) of the transistors used the VOL drop of wp and the VOH drop of wr’s under 1 mA loads (wp’s VOL k 0 1V and wr’s VOH k 0 1V ) Knowing these parameters along with the desired current allow us to design a simple external charge pump Separating the pump up and pump down circuits facilitates the nodal analysis and give the following equations VR5 b VT # ln R4 e EXAMPLE Typical Device Parameters Typical System Parameters bn e 100 bp e 50 VP e 5 0V Vcntl e 0 5V b 4 5V Vwp e 0 0V Vwr e 5 0V ISINK e ISOURCE e 5 0 mA Vfn e Vfp e 0 8V Irmax e Ipmax e 1 mA VR8 e VR5 e 0 3V VOLwp e VOHwr e 100 mV Design Parameters TL W 12459 – 28 FIGURE 9 Therefore select R4 e R9 e R5 e R8 e 0 3V b 0 026 # 1n(5 0 mA 1 0 mA) e 51 6X 5 mA 0 3V e 300X 1 0 mA 0 3V e 300X 1 0 mA (5V b 0 1V) b (0 3V a 0 8V) e 3 8 kX 1 0 mA isource VR8 b VT # ln #i #i isource p max J R6 e R7 e isink R9 e R5 e R8 e R6 e R7 e VR5 ip max VR8 ir max n max isink J (Vp b VVOLwp) b (VR5 a Vfp) ip max (VP b VVOHwr) b (VR8 a Vfn) imax 13 http www national com LMX2305 PLLatinum 550 MHz Frequency Synthesizer for RF Personal Communications Physical Dimensions inches (millimeters) unless otherwise noted NS Package Number MTC20 20-Lead (0 173 Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2305TM For Tape and Reel Order Number LMX2305TMX (2500 Units per Reel) LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation Americas Tel 1(800) 272-9959 Fax 1(800) 737-7018 Email support nsc com 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness http www national com National Semiconductor Europe Fax a49 (0) 180-530 85 86 Email europe support nsc com Deutsch Tel a49 (0) 180-530 85 85 English Tel a49 (0) 180-532 78 32 Fran ais Tel a49 (0) 180-532 93 58 Italiano Tel a49 (0) 180-534 16 80 National Semiconductor Southeast Asia Fax (852) 2376 3901 Email sea support nsc com National Semiconductor Japan Ltd Tel 81-3-5620-7561 Fax 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications