LMX2330U

LMX2330U/LMX2331U/LMX2332U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications July 2002 LMX2330U/LMX2331U/LMX2332U PLLatinum™ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications LMX2330U 2.5 GHz/600 MHz LMX2331U 2.0 GHz/600 MHz LMX2332U 1.2 GHz/600 MHz General Description The LMX233xU devices are high performance frequency synthesizers with integrated dual modulus prescalers. The LMX233xU devices are designed for use as RF and IF local oscillators for dual conversion radio transceivers. A 32/33 or a 64/65 prescale ratio can be selected for the 2.5 GHz LMX2330U RF synthesizer. A 64/65 or a 128/129 prescale ratio can be selected for both the LMX2331U and LMX2332U RF synthesizers. The IF circuitry contains an 8/9 or a 16/17 prescaler. Using a proprietary digital phase locked loop technique, the LMX233xU devices generate very stable, low noise control signals for RF and IF voltage controlled oscillators. Both the RF and IF synthesizers include a two-level programmable charge pump. The RF synthesizer has dedicated Fastlock circuitry. Serial data is transferred to the devices via a three-wire interface (Data, LE, Clock). Supply voltages from 2.7V to 5.5V are supported. The LMX233xU family features ultra low current consumption: LMX2330U (2.5 GHz) — 3.3 mA, LMX2331U (2.0 GHz) — 2.9 mA, LMX2332U (1.2 GHz) — 2.5 mA at 3.0V. The LMX233xU devices are available in 20-Pin TSSOP and 24-Pin CSP surface mount plastic packages. Features n n n n Ultra Low Current Consumption Upgrade and Compatible to LMX233xL Family 2.7V to 5.5V Operation Selectable Synchronous or Asynchronous Powerdown Mode: ICC-PWDN = 1 µA typical Selectable Dual Modulus Prescaler: LMX2330U RF: 32/33 or 64/65 LMX2331U RF: 64/65 or 128/129 LMX2332U RF: 64/65 or 128/129 LMX2330U/31U/32U IF: 8/9 or 16/17 Selectable Charge Pump TRI-STATE ® Mode Programmable Charge Pump Current Levels RF and IF: 0.95 or 3.8 mA Selectable Fastlock™ Mode for the RF Synthesizer Push-Pull Analog Lock Detect Output Available in 20-Pin TSSOP and 24-Pin Chip Scale Package (CSP) n n n n n n Applications n Mobile Handsets (GSM, GPRS, W-CDMA, CDMA, PCS, AMPS, PDC, DCS) n Cordless Handsets (DECT, DCT) n Wireless Data n Cable TV Tuners Thin Shrink Small Outline Package (MTC20) Chip Scale Package (SLB24A) 10136680 10136681 PLLatinum™ is a trademark of National Semiconductor Corporation. © 2002 National Semiconductor Corporation DS101366 www.national.com LMX2330U/LMX2331U/LMX2332U Functional Block Diagram 10136601 www.national.com 2 LMX2330U/LMX2331U/LMX2332U Connection Diagrams Chip Scale Package (SLB) (Top View) Thin Shrink Small Outline Package (TM) (Top View) 10136602 10136639 Pin Descriptions Pin Name VCC Pin No. 24-Pin CSP 24 Pin No. 20-Pin TSSOP 1 I/O — Description Power supply bias for the RF PLL analog and digital circuits. VCC may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. RF PLL charge pump power supply. Must be ≥ VCC. RF PLL charge pump output. The output is connected to the external loop filter, which drives the input of the VCO. Ground for the RF PLL digital circuitry. RF PLL prescaler input. Small signal input from the VCO. RF PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX233xU RF PLL can be driven differentially when the bypass capacitor is omitted. Ground for the RF PLL analog circuitry. Reference oscillator input. The input has an approximate VCC/2 threshold and can be driven from an external CMOS or TTL logic gate. Ground for the IF PLL digital circuits, MICROWIRE™, FoLD, and oscillator circuits. Programmable multiplexed output pin. Functions as a general purpose CMOS TRI-STATE output, RF/IF PLL push-pull analog lock detect output, N and R divider output or Fastlock output, which connects a parallel resistor to the external loop filter. MICROWIRE Clock input. High impedance CMOS input. Data is clocked into the 22-bit shift register on the rising edge of Clock. MICROWIRE Data input. High impedance CMOS input. Binary serial data. The MSB of Data is shifted in first. The last two bits are the control bits. MICROWIRE Latch Enable input. High impedance CMOS input. When LE transitions HIGH, Data stored in the shift register is loaded into one of 4 internal control registers. Ground for the IF PLL analog circuitry. VP RF Do RF GND fIN RF fIN RF 2 3 4 5 6 2 3 4 5 6 — O — I I GND OSCin GND FoLD 7 8 10 11 7 8 9 10 — I — O Clock Data LE 12 14 15 11 12 13 I I I GND 16 14 — 3 www.national.com LMX2330U/LMX2331U/LMX2332U Pin Descriptions Pin Name fIN IF Pin No. 24-Pin CSP 17 (Continued) Pin No. 20-Pin TSSOP 15 I/O I Description IF PLL prescaler complementary input. For single ended operation, this pin should be AC grounded. The LMX233xU IF PLL can be driven differentially when the bypass capacitor is omitted. IF PLL prescaler input. Small signal input from the VCO. Ground for the IF PLL digital circuitry, MICROWIRE, FoLD, and oscillator circuits. IF PLL charge pump output. The output is connected to the external loop filter, which drives the input of the VCO. IF PLL charge pump power supply. Must be ≥ VCC. Power supply bias for the IF PLL analog and digital circuits, MICROWIRE, FoLD, and oscillator circuits. VCC may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. No connect. fIN IF GND Do IF VP IF VCC 18 19 20 22 23 16 17 18 19 20 I — O — — NC 1, 9, 13, 21 X — Ordering Information Model LMX2330USLBX LMX2330UTM Temperature Range −40˚C to +85˚C −40˚C to +85˚C Package Description Chip Scale Package (CSP) Tape and Reel Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Tape and Reel Chip Scale Package (CSP) Tape and Reel Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Tape and Reel Chip Scale Package (CSP) Tape and Reel Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Tape and Reel Packing 2500 Units Per Reel 73 Units Per Rail NS Package Number SLB24A MTC20 LMX2330UTMX −40˚C to +85˚C 2500 Units Per Reel MTC20 LMX2331USLBX LMX2331UTM −40˚C to +85˚C −40˚C to +85˚C 2500 Units Per Reel 73 Units Per Rail SLB24A MTC20 LMX2331UTMX −40˚C to +85˚C 2500 Units Per Reel MTC20 LMX2332USLBX LMX2332UTM −40˚C to +85˚C −40˚C to +85˚C 2500 Units Per Reel 73 Units Per Rail SLB24A MTC20 LMX2332UTMX −40˚C to +85˚C 2500 Units Per Reel MTC20 www.national.com 4 LMX2330U/LMX2331U/LMX2332U Detailed Block Diagram 10136603 Notes: 1. A 64/65 or 128/129 prescaler ratio can be selected for the LMX2331U and LMX2332U RF synthesizers. A 32/33 or 64/65 prescaler ratio can be selected for the LMX2330U RF synthesizer. 2. VCC supplies power to the RF and IF prescalers, RF and IF feedback dividers, RF and IF reference dividers, RF and IF phase detectors, the OSCin buffer, MICROWIRE, and FoLD circuitry. 3. VP RF and VP IF supply power to the charge pumps. They can be run separately as long as VP RF ≥ VCC and VP IF ≥ VCC. 5 www.national.com LMX2330U/LMX2331U/LMX2332U Absolute Maximum Ratings 2, 3) (Notes 1, Recommended Operating Conditions (Note 1) Power Supply Voltage VCC to GND VP RF to GND VP IF to GND Operating Temperature (TA) +2.7V to +5.5V VCC to +5.5V VCC to +5.5V −40˚C to +85˚C If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage VCC to GND VP RF to GND VP IF to GND Voltage on any pin to GND (VI) VI must be < +6.5V Storage Temperature Range (TS) Lead Temperature (solder 4 s) (TL) TSSOP θJA Thermal Impedance CSP θJA Thermal Impedance −0.3V to VCC+0.3V −65˚C to +150˚C +260˚C 114.5˚C/W 112˚C/W −0.3V to +6.5V −0.3V to +6.5V −0.3V to +6.5V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, refer to the Electrical Characteristics section. The guaranteed specifications apply only for the conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating < 2 kV and is ESD sensitive. Handling and assembly of this device should only be done at ESD protected work stations. Note 3: GND = 0V Electrical Characteristics VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Symbol ICC PARAMETERS ICCRF + IF Power Supply Current, RF + IF Synthesizers Power Supply Current, RF Synthesizer Only Power Supply Current, IF Synthesizer Only Powerdown Current LMX2330U LMX2331U LMX2332U ICCRF LMX2330U LMX2331U LMX2332U ICCIF LMX233xU Clock, Data and LE = GND OSCin = GND PWDN RF Bit = 0 PWDN IF Bit = 0 Clock, Data and LE = GND OSCin = GND PWDN RF Bit = 0 PWDN IF Bit = 1 Clock, Data and LE = GND OSCin = GND PWDN RF Bit = 1 PWDN IF Bit = 0 Clock, Data and LE = GND OSCin = GND PWDN RF Bit = 1 PWDN IF Bit = 1 500 200 100 Prescaler = 32/33 (Note 4) Prescaler = 64/65 (Note 4) Prescaler = 128/129 (Note 4) RRF FφRF RF R Divider Range RF Phase Detector Frequency 96 192 384 3 3.3 2.9 2.5 2.3 1.9 1.5 1.0 4.3 3.8 3.3 3.0 2.5 2.0 1.3 mA mA mA mA mA mA mA Parameter Conditions Value Min Typ Max Units ICC-PWDN LMX233xU 1.0 10.0 µA RF SYNTHESIZER PARAMETERS fIN RF RF Operating Frequency RF N Divider Range LMX2330U LMX2331U LMX2332U NRF 2500 2000 1200 65631 131135 262143 32767 10 MHz MHz MHz MHz www.national.com 6 LMX2330U/LMX2331U/LMX2332U Electrical Characteristics Symbol Parameter (Continued) VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Conditions Value Min −15 −10 -0.95 Typ Max 0 0 Units RF SYNTHESIZER PARAMETERS PfIN RF RF Input Sensitivity 2.7V ≤ VCC ≤ 3.0V (Note 5) 3.0 < VCC ≤ 5.5V (Note 5) IDo RF SOURCE RF Charge Pump Output Source Current VDo RF = VP RF/2 IDo RF Bit = 0 (Note 6) VDo RF = VP RF/2 IDo RF Bit = 1 (Note 6) IDo RF SINK RF Charge Pump Output Sink Current VDo RF = VP RF/2 IDo RF Bit = 0 (Note 6) VDo RF = VP RF/2 IDo RF Bit = 1 (Note 6) IDo RF TRI-STATE IDo RF SINK Vs IDo RF SOURCE IDo RF Vs VDo RF IDo RF Vs TA fIN IF RF Charge Pump Output TRI-STATE Current 0.5V ≤ VDo RF ≤ VP RF - 0.5V (Note 6) -2.5 3 dBm dBm mA -3.80 mA 0.95 mA 3.80 mA 2.5 10 nA % RF Charge Pump Output Sink Current VDo RF = VP RF/2 Vs Charge Pump Output Source TA = +25˚C (Note 7) Current Mismatch RF Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage RF Charge Pump Output Current Magnitude Variation Vs Temperature 0.5V ≤ VDo RF ≤ VP RF - 0.5V TA = +25˚C (Note 7) VDo RF = VP RF/2 (Note 7) 10 15 % 10 % IF SYNTHESIZER PARAMETERS IF Operating Frequency IF N Divider Range LMX2330U LMX2331U LMX2332U NIF Prescaler = 8/9 (Note 4) Prescaler = 16/17 (Note 4) RIF FφIF PfIN IF IF R Divider Range IF Phase Detector Frequency IF Input Sensitivity 2.7V ≤ VCC ≤ 5.5V (Note 5) -10 45 45 45 24 48 3 600 600 600 16391 32767 32767 10 0 MHz dBm MHz MHz MHz 7 www.national.com LMX2330U/LMX2331U/LMX2332U Electrical Characteristics Symbol Parameter (Continued) VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Conditions Value Min Typ -0.95 Max Units IF SYNTHESIZER PARAMETERS IDo IF SOURCE IF Charge Pump Output Source Current VDo IF = VP IF/2 IDo IF Bit = 0 (Note 6) VDo IF = VP IF/2 IDo IF Bit = 1 (Note 6) IDo IF SINK IF Charge Pump Output Sink Current VDo IF = VP IF/2 IDo IF Bit = 0 (Note 6) VDo IF = VP IF/2 IDo IF Bit = 1 (Note 6) IDo IF TRI-STATE IDo IF SINK Vs IDo IF SOURCE IDo IF Vs VDo IF IDo IF Vs TA FOSC VOSC IOSC IF Charge Pump Output TRI-STATE Current IF Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch 0.5V ≤ VDo IF ≤ VP IF - 0.5V (Note 6) VDo IF = VP IF/2 TA = +25˚C (Note 7) -2.5 3 mA -3.80 mA 0.95 mA 3.80 mA 2.5 10 nA % IF Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage IF Charge Pump Output Current Magnitude Variation Vs Temperature 0.5V ≤ VDo IF ≤ VP IF - 0.5V TA = +25˚C (Note 7) VDo IF = VP IF/2 (Note 7) 10 15 % 10 % OSCILLATOR PARAMETERS Oscillator Operating Frequency Oscillator Sensitivity Oscillator Input Current (Note 8) VOSC = VCC = 5.5V VOSC = 0V, VCC = 5.5V DIGITAL INTERFACE (Data, LE, Clock, FoLD) VIH VIL IIH IIL VOH VOL tCS tCH tCWH tCWL tES tEW High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Output Voltage Low-Level Output Voltage Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width HIGH Clock Pulse Width LOW Clock to Load Enable Set Up Time Latch Enable Pulse Width VIH = VCC = 5.5V VIL = 0V, VCC = 5.5V IOH = −500 µA IOL = 500 µA (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) 50 10 50 50 50 50 −1.0 −1.0 VCC − 0.4 0.4 0.8 VCC 0.2 VCC 1.0 1.0 V V µA µA V V ns ns ns ns ns ns -100 2 0.5 40 VCC 100 MHz VPP µA µA MICROWIRE INTERFACE www.national.com 8 LMX2330U/LMX2331U/LMX2332U Electrical Characteristics Symbol Parameter (Continued) VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Conditions Value Min Typ -212.0 Max Units PHASE NOISE CHARACTERISTICS LN(f) RF RF Synthesizer Normalized Phase Noise Contribution (Note 10) RF Synthesizer Single LMX2330U Side Band Phase Noise Measured TCXO Reference Source IDo RF Bit = 1 fIN RF = 2450 MHz f = 1 kHz Offset FφRF = 200 kHz Loop Bandwidth = 7.5 kHz N = 12250 FOSC = 10 MHz VOSC = 0.632 VPP IDo RF Bit = 1 PWDN IF Bit = 1 TA = +25˚C (Note 11) fIN RF = 1960 MHz f = 1 kHz Offset FφRF = 200 kHz Loop Bandwidth = 15 kHz N = 9800 FOSC = 10 MHz VOSC = 0.632 VPP IDo RF Bit = 1 PWDN IF Bit = 1 TA = +25˚C (Note 11) fIN RF = 900 MHz f = 1 kHz Offset FφRF = 200 kHz Loop Bandwidth = 12 kHz N = 4500 FOSC = 10 MHz VOSC = 0.632 VPP IDo RF Bit = 1 PWDN IF Bit = 1 TA = +25˚C (Note 11) dBc/ Hz dBc/ Hz L(f) RF -77.24 LMX2331U -79.18 dBc/ Hz LMX2332U -85.94 dBc/ Hz 9 www.national.com LMX2330U/LMX2331U/LMX2332U Electrical Characteristics Symbol Parameter (Continued) VCC = VP RF = VP IF = 3.0V, −40˚C ≤ TA ≤ +85˚C, unless otherwise specified Conditions Value Min Typ -212.0 Max Units PHASE NOISE CHARACTERISTICS LN(f) IF IF Synthesizer Normalized Phase Noise Contribution (Note 10) IF Synthesizer Single Side Band Phase Noise Measured LMX233xU TCXO Reference Source IDo IF Bit = 1 fIN IF = 200 MHz f = 1 kHz Offset FφIF = 200 kHz Loop Bandwidth = 18 kHz N = 1000 FOSC = 10 MHz VOSC = 0.632 VPP IDo IF Bit = 1 PWDN RF Bit = 1 TA = +25˚C (Note 11) dBc/ Hz dBc/ Hz L(f) IF -99.00 Note 4: Some of the values in this range are illegal divide ratios (B < A). To obtain continuous legal division, the Minimum Divide Ratio must be calculated. Use N ≥ P * (P−1), where P is the value of the prescaler selected. Note 5: Refer to the LMX233xU fIN Sensitivity Test Setup section Note 6: Refer to the LMX233xU Charge Pump Test Setup section Note 7: Refer to the Charge Pump Current Specification Definitions for details on how these measurements are made. Note 8: Refer to the LMX233xU OSCin Sensitivity Test Setup section Note 9: Refer to the LMX233xU Serial Data Input Timing section Note 10: Normalized Phase Noise Contribution is defined as : LN(f) = L(f) − 20 log (N) − 10 log (Fφ), where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL’s loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. N is the value selected for the feedback divider and Fφ is the RF/IF phase detector comparison frequency. Note 11: The synthesizer phase noise is measured with the LMX2330TMEB/LMX2330SLBEB Evaluation boards and the HP8566B Spectrum Analyzer. www.national.com 10 LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Sensitivity LMX2330U fIN RF Input Power Vs Frequency VCC = VP RF = 3.0V 10136642 LMX2330U fIN RF Input Power Vs Frequency VCC = VP RF = 5.5V 10136643 11 www.national.com LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Sensitivity (Continued) LMX2331U fIN RF Input Power Vs Frequency VCC = VP RF = 3.0V 10136644 LMX2331U fIN RF Input Power Vs Frequency VCC = VP RF = 5.5V 10136645 www.national.com 12 LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Sensitivity (Continued) LMX2332U fIN RF Input Power Vs Frequency VCC = VP RF = 3.0V 10136646 LMX2332U fIN RF Input Power Vs Frequency VCC = VP RF = 5.5V 10136647 13 www.national.com LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Sensitivity (Continued) LMX233xU fIN IF Input Power Vs Frequency VCC = VP IF = 3.0V 10136648 LMX233xU fIN IF Input Power Vs Frequency VCC = VP IF = 5.5V 10136649 www.national.com 14 LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Sensitivity (Continued) LMX233xU OSCin Input Voltage Vs Frequency VCC = 3.0V 10136652 LMX233xU OSCin Input Voltage Vs Frequency VCC = 5.5V 10136653 15 www.national.com LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Charge Pump LMX233xU RF Charge Pump Sweeps −40˚C ≤ TA ≤ +85˚C 10136660 www.national.com 16 LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Charge Pump (Continued) LMX233xU IF Charge Pump Sweeps −40˚C ≤ TA ≤ +85˚C 10136661 17 www.national.com LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Input Impedance LMX233xU TSSOP fIN RF Input Impedance VCC = 3.0V, TA = +25˚C LMX233xU TSSOP fIN RF Input Impedance VCC = 5.5V, TA = +25˚C 10136666 10136667 LMX233xU CSP fIN RF Input Impedance VCC = 3.0V, TA = +25˚C LMX233xU CSP fIN RF Input Impedance VCC = 5.5V, TA = +25˚C 10136668 10136669 www.national.com 18 Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP and LMX233xU CSP fIN RF Input Impedance Table LMX2330U/LMX2331U/LMX2332U 19 10136670 www.national.com LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP fIN IF Input Impedance VCC = 3.0V, TA = +25˚C LMX233xU TSSOP fIN IF Input Impedance VCC = 5.5V, TA = +25˚C 10136671 10136672 LMX233xU CSP fIN IF Input Impedance VCC = 3.0V, TA = +25˚C LMX233xU CSP fIN IF Input Impedance VCC = 5.5V, TA = +25˚C 10136673 10136674 www.national.com 20 Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP and LMX233xU CSP fIN IF Input Impedance Table LMX2330U/LMX2331U/LMX2332U 21 10136675 www.national.com LMX2330U/LMX2331U/LMX2332U Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP OSCin Input Impedance Vs Frequency TA = +25˚C 10136676 LMX233xU CSP OSCin Input Impedance Vs Frequency TA = +25˚C 10136677 www.national.com 22 Typical Performance Characteristics Input Impedance (Continued) LMX233xU TSSOP and LMX233xU CSP OSCin Input Impedance Table LMX2330U/LMX2331U/LMX2332U 23 10136678 www.national.com LMX2330U/LMX2331U/LMX2332U Charge Pump Current Specification Definitions 10136637 I1 = Charge Pump Sink Current at VDo = VP − ∆V I2 = Charge Pump Sink Current at VDo = VP/2 I3 = Charge Pump Sink Current at VDo = ∆V I4 = Charge Pump Source Current at VDo = VP − ∆V I5 = Charge Pump Source Current at VDo = VP/2 I6 = Charge Pump Source Current at VDo = ∆V ∆V = Voltage offset from the positive and negative rails. Dependent on the VCO tuning range relative to VCC and GND. Typical values are between 0.5V and 1.0V. VP refers to either VP RF or VP IF VDo refers to either VDo RF or VDo IF IDo refers to either IDo RF or IDo IF Charge Pump Output Current Magnitude Variation Vs Charge Pump Output Voltage 10136663 Charge Pump Output Sink Current Vs Charge Pump Output Source Current Mismatch 10136664 Charge Pump Output Current Magnitude Variation Vs Temperature 10136665 www.national.com 24 LMX2330U/LMX2331U/LMX2332U Test Setups LMX233xU Charge Pump Test Setup 10136650 The block diagram above illustrates the setup required to measure the LMX233xU device’s RF charge pump sink current. The same setup is used for a LMX2330TMEB Evaluation Board. The IF charge pump measurement setup is similar to the RF charge pump measurement setup. The purpose of this test is to assess the functionality of the RF charge pump. This setup uses an open loop configuration. A power supply is connected to Vcc and swept from 2.7V to 5.5V. By means of a signal generator, a 10 MHz signal is typically applied to the fIN RF pin. The signal is one of two inputs to the phase detector. The 3 dB pad provides a 50 Ω match between the PLL and the signal generator. The OSCin pin is tied to Vcc. This establishes the other input to the phase detector. Alternatively, this input can be tied directly to the ground plane. With the Do RF pin connected to a Semiconductor Parameter Analyzer in this way, the sink, source, and TRI-STATE currents can be measured by simply toggling the Phase Detector Polarity and Charge Pump State states in Code Loader. Similarly, the LOW and HIGH currents can be measured by switching the Charge Pump Gain’s state between 1X and 4X in Code Loader. Let Fr represent the frequency of the signal applied to the OSCin pin, which is simply zero in this case (DC), and let Fp represent the frequency of the signal applied to the fIN RF pin. The phase detector is sensitive to the rising edges of Fr and Fp. Assuming positive VCO characteristics; the charge pump turns ON and sinks current when the first rising edge of Fp is detected. Since Fr has no rising edge, the charge pump continues to sink current indefinitely. Toggling the Phase Detector Polarity state to negative VCO characteristics allows the measurement of the RF charge pump source current. Likewise, selecting TRI-STATE (TRI-STATE IDo RF Bit = 1) for Charge Pump State in Code Loader facilitates the measurement of the TRI-STATE current. The measurements are repeated at different temperatures, namely TA = -40˚C, +25˚C, and +85˚C. 25 www.national.com LMX2330U/LMX2331U/LMX2332U Test Setups (Continued) LMX233xU fIN Sensitivity Test Setup 10136640 The block diagram above illustrates the setup required to measure the LMX233xU device’s RF input sensitivity level. The same setup is used for a LMX2330TMEB Evaluation Board. The IF input sensitivity test setup is similar to the RF sensitivity test setup. The purpose of this test is to measure the acceptable signal level to the fIN RF input of the PLL chip. Outside the acceptable signal range, the feedback divider begins to divide incorrectly and miscount the frequency. The setup uses an open loop configuration. A power supply is connected to Vcc and swept from 2.7V to 5.5V. The IF PLL is powered down (PWDN IF Bit = 1). By means of a signal generator, an RF signal is applied to the fIN RF pin. The 3 dB pad provides a 50 Ω match between the PLL and the signal generator. The OSCin pin is tied to Vcc. The N value is typically set to 10000 in Code Loader, i.e. RF N_CNTRB Word = 156 and RF N_CNTRA Word = 16 for PRE RF Bit = 1 (LMX2330U) or PRE RF = 0 (LMX2331U and LMX2332U). The feedback divider output is routed to the FoLD pin by selecting the RF PLL N Divider Output word (FoLD Word = 6 or 14) in Code Loader. A Universal Counter is connected to the FoLD pin and tied to the 10 MHz reference output of the signal generator. The output of the feedback divider is thus monitored and should be equal to fIN RF / N. The fIN RF input frequency and power level are then swept with the signal generator. The measurements are repeated at different temperatures, namely TA = -40˚C, +25˚C, and +85˚C. Sensitivity is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz. The power attenuation from the cable and the 3 dB pad must be accounted for. The feedback divider will actually miscount if too much or too little power is applied to the fIN RF input. Therefore, the allowed input power level will be bounded by the upper and lower sensitivity limits. In a typical application, if the power level to the fIN RF input approaches the sensitivity limits, this can introduce spurs and degradation in phase noise. When the power level gets even closer to these limits, or exceeds it, then the RF PLL loses lock. www.national.com 26 LMX2330U/LMX2331U/LMX2332U Test Setups (Continued) LMX233xU OSCin Sensitivity Test Setup 10136641 The block diagram above illustrates the setup required to measure the LMX233xU device’s OSCin buffer sensitivity level. The same setup is used for a LMX2330TMEB Evaluation Board. This setup is similar to the fIN sensitivity setup except that the signal generator is now connected to the OSCin pin and both fIN pins are tied to VCC. The 51 Ω shunt resistor matches the OSCin input to the signal generator. The R counter is typically set to 1000, i.e. RF R_CNTR Word = 1000 or IF R_CNTR Word = 1000. The reference divider output is routed to the FoLD pin by selecting the RF PLL R Divider Output word (FoLD Word = 2 or 10) or the IF PLL R Divider Output word (FoLD Word = 1 or 9) in Code Loader. Similarly, a Universal Counter is connected to the FoLD pin and is tied to the 10 MHz reference output from the signal generator. The output of the reference divider is monitored and should be equal to OSCin/ RF R_CNTR or OSCin/ IF R_CNTR. Again, VCC is swept from 2.7V to 5.5V. The OSCin input frequency and voltage level are then swept with the signal generator. The measurements are repeated at different temperatures, namely TA = -40˚C, +25˚C, and +85˚C. Sensitivity is reached when the frequency error of the divided input signal is greater than or equal to 1 Hz. 27 www.national.com LMX2330U/LMX2331U/LMX2332U Test Setups (Continued) LMX233xU fIN Impedance Test Setup 10136679 The block diagram above illustrates the setup required to measure the LMX233xU device’s RF input impedance. The IF input impedance and reference oscillator impedance setups are very much similar. The same setup is used for a LMX2330TMEB Evaluation Board. Measuring the device’s input impedance facilitates the design of appropriate matching networks to match the PLL to the VCO, or in more critical situations, to the characteristic impedance of the printed circuit board (PCB) trace, to prevent undesired transmission line effects. Before the actual measurements are taken, the Network Analyzer needs to be calibrated, i.e. the error coefficients need to be calculated. Therefore, three standards will be used to calculate these coefficients: an open, short and a matched load. A 1-port calibration is implemented here. To calculate the coefficients, the PLL chip is first removed from the PCB. The Network Analyzer port is then connected to the RF OUT connector of the evaluation board and the desired operating frequency is set. The typical frequency range selected for the LMX233xU device’s RF synthesizer is from 100 MHz to 2500 MHz. The standards will be located down the length of the RF OUT transmission line. The transmission line adds electrical length and acts as an offset from the reference plane of the Network Analyzer; therefore, it must be included in the calibration. Although not shown, 0 Ω resistors are used to complete the RF OUT transmission line (trace). To implement an open standard, the end of the RF OUT trace is simply left open. To implement a short standard, a 0 Ω resistor is placed at the end of the RF OUT transmission line. Last of all, to implement a matched load standard, two 100 Ω resistors in parallel are placed at the end of the RF OUT transmission line. The Network Analyzer calculates the calibration coefficients based on the measured S11 parameters. With this all done, calibration is now complete. The PLL chip is then placed on the PCB. A power supply is connected to VCC and swept from 2.7V to 5.5V. The OSCin pin is tied to the ground plane. Alternatively, the OSCin pin can be tied to VCC. In this setup, the complementary input (fIN RF) is AC coupled to ground. With the Network Analyzer still connected to RF OUT, the measured fIN RF impedance is displayed. Note: The impedance of the reference oscillator is measured when the oscillator buffer is powered up (PWDN RF Bit = 0 or PWDN IF Bit = 0), and when the oscillator buffer is powered down (PWDN RF Bit = 1 and PWDN IF Bit = 1). www.national.com 28 LMX2330U/LMX2331U/LMX2332U LMX233xU Serial Data Input Timing 10136610 Notes: 1. 2. Data is clocked into the 22-bit shift register on the rising edge of Clock The MSB of Data is shifted in first. 29 www.national.com LMX2330U/LMX2331U/LMX2332U 1.0 Functional Description The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer such as the National Semiconductor LMX233xU, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, programmable reference R and feedback N frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the reference divider to obtain a comparison reference frequency. This reference signal, Fr, is then presented to the input of a phase/frequency detector and compared with the feedback signal, Fp, which was obtained by dividing the VCO frequency down by way of the feedback divider. The phase/frequency detector measures the phase error between the Fr and Fp signals and outputs control signals that are directly proportional to the phase error. The charge pump then pumps charge into or out of the loop filter based on the magnitude and direction of the phase error. The loop filter converts the charge into a stable control voltage for the VCO. The phase/frequency detector’s function is to adjust the voltage presented to the VCO until the feedback signal’s frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency will be N times that of the comparison frequency, where N is the feedback divider ratio. 1.1 REFERENCE OSCILLATOR INPUT The reference oscillator frequency for both the RF and IF PLLs is provided from an external reference via the OSCin pin. The reference buffer circuit supports input frequencies from 5 to 40 MHz with a minimum input sensitivity of 0.5 VPP. The reference buffer circuit has an approximate VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. Typically, the OSCin pin is connected to the output of a crystal oscillator. 1.2 REFERENCE DIVIDERS (R COUNTERS) The reference dividers divide the reference input signal, OSCin, by a factor of R. The output of the reference divider circuits feeds the reference input of the phase detector. This reference input to the phase detector is often referred to as the comparison frequency. The divide ratio should be chosen such that the maximum phase comparison frequency (FφRF or FφIF) of 10 MHz is not exceeded. The RF and IF reference dividers are each comprised of 15-bit CMOS binary counters that support a continuous integer divide ratio from 3 to 32767. The RF and IF reference divider circuits are clocked by the output of the reference buffer circuit which is common to both. 1.3 PRESCALERS The fIN RF (fIN IF) and fIN RF (fIN IF) input pins drive the input of a bipolar, differential-pair amplifier. The output of the bipolar, differential-pair amplifier drives a chain of ECL D-type flip-flops in a dual modulus configuration. The output of the prescaler is used to clock the subsequent feedback dividers. The RF and IF PLL complementary inputs can be driven differentially, or the negative input can be AC coupled to ground through an external capacitor for single ended configuration. A 32/33 or a 64/65 prescale ratio can be selected for the 2.5 GHz LMX2330U RF synthesizer. A 64/65 or a 128/129 prescale ratio can be selected for both the LMX2331U and LMX2332U RF synthesizers. The IF circuitry contains an 8/9 or a 16/17 prescaler. 1.4 PROGRAMMABLE FEEDBACK DIVIDERS (N COUNTERS) The programmable feedback dividers operate in concert with the prescalers to divide the input signal, fIN, by a factor of N. The output of the programmable reference divider is provided to the feedback input of the phase detector circuit. The divide ratio should be chosen such that the maximum phase comparison frequency (FφRF or FφIF) of 10 MHz is not exceeded. The programmable feedback divider circuit is comprised of an A counter (swallow counter) and a B counter (programmble binary counter). The RF N_CNTRA counter is a 7-bit CMOS swallow counter, programmable from 0 to 127. The IF N_CNTRA counter is also a 7-bit CMOS swallow counter, but programmable from 0 to 15. The three most significant bits are ’don’t cares’ in this case. The RF N_CNTRB and IF N_CNTRB counters are both 11-bit CMOS binary counters, programmable from 3 to 2047. A continuous integer divide ratio is achieved if N ≥ P * (P−1), where P is the value of the prescaler selected. Divide ratios less than the minimum continuous divide ratio are achievable as long as the binary programmable counter value is greater than the swallow counter value (N_CNTRB ≥ N_CNTRA). Refer to Sections 2.6.1, 2.6.2, 2.7.1 and 2.7.2 for details on how to program the N_CNTRA and N_CNTRB counters. The following equations are useful in determining and programming a particular value of N: N = (P x N_CNTRB) + N_CNTRA fIN = N x Fφ Definitions: Fφ : RF or IF phase detector comparison frequency RF or IF input frequency fIN: N_CNTRA: RF or IF A counter value N_CNTRB: RF or IF B counter value P: Preset modulus of the dual moduIus prescaler LMX2330U RF synthesizer: P = 32 or 64 LMX2331U RF synthesizer: P = 64 or 128 LMX2332U RF synthesizer: P = 64 or 128 LMX233xU IF synthesizer: P = 8 or 16 1.5 PHASE/FREQUENCY DETECTORS The RF and IF phase/frequency detectors are driven from their respective N and R counter outputs. The maximum frequency for both the RF and IF phase detector inputs is 10 MHz. The phase/frequency detector outputs control the respective charge pumps. The polarity of the pump-up or pump-down control signals are programmed using the PD_POL RF or PD_POL IF control bits, depending on whether the RF or IF VCO characteristics are positive or negative. Refer to Sections 2.4.2 and 2.5.2 for more details. The phase/frequency detectors have a detection range of −2π to +2π. The phase/frequency detectors also receive a feedback signal from the charge pump in order to eliminate dead zone. www.national.com 30 LMX2330U/LMX2331U/LMX2332U 1.0 Functional Description (Continued) PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS 10136611 Notes: 1. 2. 3. 4. 5. The minimum width of the pump-up and pump-down current pulses occur at the Do RF or Do IF pins when the loop is phase locked. The diagram assumes positive VCO characteristics, i.e. PD_POL RF or PD_POL IF = 1. Fr is the phase detector input from the reference divider (R counter). Fp is the phase detector input from the programmable feedback divder (N counter). Do refers to either the RF or IF charge pump output. 1.6 CHARGE PUMPS The charge pump directs charge into or out of an external loop filter. The loop filter converts the charge into a stable control voltage which is applied to the tuning input of the VCO. The charge pump steers the VCO control voltage towards VP RF or VP IF during pump-up events and towards GND during pump-down events. When locked, Do RF or Do IF are primarily in a TRI-STATE mode with small corrections occuring at the phase comparator rate. The charge pump output current magnitude can be selected by toggling the IDo RF or IDo IF control bits. 1.7 MICROWIRE SERIAL INTERFACE The programmable register set is accessed via the MICROWIRE serial interface. The interface is comprised of three signal pins: Clock, Data and LE (Latch Enable). Serial data is clocked into the 22-bit shift register on the rising edge of Clock. The last two bits decode the internal control register address. When LE transitions HIGH, data stored in the shift register is loaded into one of four control registers depending on the state of the address bits. The MSB of Data is loaded in first. The synthesizers can be programmed even in power down mode. A complete programming description is provided in Section 2.0 Programming Description. 1.8 MULTI-FUNCTION OUTPUTS The LMX233xU device’s FoLD output pin is a multi-function output that can be configured as the RF FastLock output, a push-pull analog lock detect output, counter reset, or used to monitor the output of the various reference divider (R counter) or feedback divider (N counter) circuits. The FoLD control word is used to select the desired output function. When the PLL is in powerdown mode, the FoLD output is pulled to a LOW state. A complete programming description of the multi-function output is provided in Section 2.8 FoLD. 1.8.1 Push-Pull Analog Lock Detect Output An analog lock detect status generated from the phase detector is available on the FoLD output pin if selected. The lock detect output goes HIGH when the charge pump is inactive. It goes LOW when the charge pump is active during a comparison cycle. When viewed with an oscilloscope, narrow negative pulses are observed when the charge pump turns on. The lock detect output signal is a push-pull configuration. Three separate lock detect signals are routed to the multiplexer. Two of these monitor the ‘lock’ status of the individual synthesizers. The third detects the condition when both the RF and IF synthesizers are in a ‘locked state’. External circuitry however, is required to provide a steady DC signal to indicate when the PLL is in a locked state. Refer to Section 2.8 FoLD for details on how to program the different lock detect options. 31 www.national.com LMX2330U/LMX2331U/LMX2332U 1.0 Functional Description 1.8.2 Open Drain FastLock Output (Continued) The LMX233xU Fastlock feature allows faster loop response time during lock aquisition. The loop response time (lock time) can be approximately halved if the loop bandwidth is doubled. In order to achieve this, the same gain/ phase relationship at twice the loop bandwidth must be maintained. This can be achieved by increasing the charge pump current from 0.95 mA (IDo RF Bit = 0) in the steady state mode, to 3.8 mA (IDo RF Bit = 1) in Fastlock. When the FoLD output is configured as a FastLock output, an open drain device is enabled. The open drain device switches in a parallel resistor R2’ to ground, of equal value to resistor R2 of the external loop filter. The loop bandwidth is effectively doubled and stability is maintained. Once locked to the correct frequency, the PLL will return to a steady state condition. Refer to Section 2.8 FoLD for details on how to configure the FoLD output to an open drain Fastlock output. 1.8.3 Counter Reset Three separate counter reset functions are provided. When the FoLD is programmed to Reset IF Counters, both the IF feedback divider and the IF reference divider are held at their load point. When the Reset RF Counters is programmed, both the RF feedback divider and the RF reference divider are held at their load point. When the Reset All Counters mode is enabled, all feedback dividers and reference dividers are held at their load point. When the device is programmed to normal operation, both the feedback divider and reference divider are enabled and resume counting in ‘close’ alignment to each other. Refer to Section 2.8 FoLD for more details. 1.8.4 Reference Divider and Feedback Divider Output The outputs of the various N and R dividers can be monitored by selecting the appropriate FoLD word. This is essential when performing OSCin or fIN sensitivity measurements. Refer to the Test Setups section for more details. Refer to Section 2.8 FoLD for more details on how to route the appropriate divider output to the FoLD pin. 1.9 POWER CONTROL Each synthesizer in the LMX233xU device is individually power controlled by device powerdown bits. The powerdown word is comprised of the PWDN RF (PWDN IF) bit, in conjuction with the TRI-STATE IDo RF (TRI-STATE IDo IF) bit. The powerdown control word is used to set the operating mode of the device. Refer to Sections 2.4.4, 2.5.4, 2.6.4, and 2.7.4 for details on how to program the RF or IF powerdown bits. When either the RF synthesizer or the IF synthesizer enters the powerdown mode, the respective prescaler, phase detector, and charge pump circuit are disabled. The Do RF (Do IF), fIN RF (fIN IF), and fIN RF (fIN IF) pins are all forced to a high impedance state. The reference divider and feedback divider circuits are held at the load point during powerdown. The oscillator buffer is disabled when both the RF and IF synthesizers are powered down. The OSCin pin is forced to a HIGH state through an approximate 100 kΩ resistance when this condition exists. When either synthesizer is activated, the respective prescaler, phase detector, charge pump circuit, and the oscillator buffer are all powered up. The feedback divider, and the reference divider are held at load point. This allows the reference oscillator, feedback divider, reference divider and prescaler circuitry to reach proper bias levels. After a finite delay, the feedback and reference dividers are enabled and they resume counting in ‘close’ alignment (the maximum error is one prescaler cycle). The MICROWIRE control register remains active and capable of loading and latching data while in the powerdown mode. Synchronous Powerdown Mode In this mode, the powerdown function is gated by the charge pump. When the device is configured for synchronous powerdown, the device will enter the powerdown mode upon completion of the next charge pump pulse event. Asynchronous Powerdown Mode In this mode, the powerdown function is NOT gated by the completion of a charge pump pulse event. When the device is configured for asynchronous powerdown, the part will go into powerdown mode immediately. TRI-STATE IDo 0 1 0 1 PWDN 0 0 1 1 Operating Mode PLL Active, Normal Operation PLL Active, Charge Pump Output in High Impedance State Synchronous Powerdown Asynchronous Powerdown Notes: 1. TRI-STATE IDo refers to either the TRI-STATE IDo RF or TRI-STATE IDo IF bit . 2. PWDN refers to either the PWDN RF or PWDN IF bit. www.national.com 32 LMX2330U/LMX2331U/LMX2332U 2.0 Programming Description 2.1 MICROWIRE INTERFACE The 22-bit shift register is loaded via the MICROWIRE interface. The shift register consists of a 20-bit Data[19:0] Field and a 2-bit Address[1:0] Field as shown below. The Address Field is used to decode the internal control register address. When LE transitions HIGH, data stored in the shift register is loaded into one of 4 control registers depending on the state of the address bits. The MSB of Data is loaded in first. The Data Field assignments are shown in Section 2.3 CONTROL REGISTER CONTENT MAP. MSB Data[19:0] 21 2.2 CONTROL REGISTER LOCATION The address bits Address[1:0] decode the internal register address. The table below shows how the address bits are mapped into the target control register. Address[1:0] Field 0 0 1 1 0 1 0 1 Target Register IF R RF R IF N RF N 21 Address[1:0] 0 LSB 2.3 CONTROL REGISTER CONTENT MAP The control register content map describes how the bits within each control register are allocated to specific control functions. 33 www.national.com LMX2330U/LMX2331U/LMX2332U (Continued) SHIFT REGISTER BIT LOCATION 18 Data Field IDo IF IF R_CNTR[14:0] 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Least Significant Bit 2 1 0 Address Field 2.0 Programming Description www.national.com Reg. Most Significant Bit 21 20 19 IF R PD_ POL IF FoLD0 FoLD2 TRISTATE IDo IF IDo RF RF R_CNTR[14:0] 0 0 RF R FoLD1 FoLD3 TRISTATE IDo RF IF N_CNTRB[10:0] PD_ POL RF 0 1 IF N PWDN IF PRE IF IF N_CNTRA[6:0] 1 0 RF N PWDN RF RF N_CNTRB[10:0] PRE RF RF N_CNTRA[6:0] 1 1 34 LMX2330U/LMX2331U/LMX2332U 2.0 Programming Description 2.4 IF R REGISTER (Continued) The IF R register contains the IF R_CNTR, PD_POL IF, IDo IF, and TRI-STATE IDo IF control words, in addition to two bits that compose the FoLD control word. The detailed descriptions and programming information for each control word is discussed in the following sections. IF R_CNTR[14:0] Reg. Most Significant Bit 21 20 19 18 17 16 15 14 SHIFT REGISTER BIT LOCATION 13 12 11 10 9 8 7 6 5 4 Least Significant Bit 3 2 1 0 Address Field Data Field TRI- IF R PD_ STATE FoLD0 FoLD2 IDo IF IDo IF IF POL IF R_CNTR[14:0] 0 0 2.4.1 IF R_CNTR[14:0] IF SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) IF R[2:16] The IF reference divider (IF R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3 are prohibited. Divide Ratio 14 3 4 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 IF R_CNTR[14:0] 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 1 1 1 0 0 1 0 • 32767 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 2.4.2 PD_POL IF IF SYNTHESIZER PHASE DETECTOR POLARITY IF R[17] The PD_POL IF bit is used to control the IF synthesizer’s phase detector polarity based on the VCO tuning characteristics. Control Bit PD_POL IF Register Location IF R[17] Description 0 IF Phase Detector Polarity IF VCO Negative Tuning Characteristics Function 1 IF VCO Positive Tuning Characteristics IF VCO Characteristics 10136609 2.4.3 IDo IF IF SYNTHESIZER CHARGE PUMP CURRENT GAIN The IDo IF bit controls the IF synthesizer’s charge pump gain. Two current levels are available. Control Bit IDo IF Register Location IF R[18] Description 0 IF Charge Pump Current Gain LOW 0.95 mA Function 1 IF R[18] HIGH 3.80 mA 35 www.national.com LMX2330U/LMX2331U/LMX2332U 2.0 Programming Description (Continued) 2.4.4 TRI-STATE IDo IF IF SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT IF R[19] The TRI-STATE IDo IF bit allows the charge pump to be switched between a normal operating mode and a high impedance output state. This happens asynchronously with the change in the TRI-STATE IDo IF bit. Furthermore, the TRI-STATE IDo IF bit operates in conjuction with the PWDN IF bit to set a synchronous or an asynchronous powerdown mode. Control Bit TRI-STATE IDo IF Register Location IF R[19] Description 0 IF Charge Pump TRI-STATE Current IF Charge Pump Normal Operation Function 1 IF Charge Pump Output in High Impedance State 2.5 RF R REGISTER The RF R register contains the RF R_CNTR, PD_POL RF, IDo RF, and TRI-STATE IDo RF control words, in addition to two bits that compose the FoLD control word. The detailed descriptions and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 17 16 15 14 SHIFT REGISTER BIT LOCATION 13 12 11 10 9 8 7 6 5 4 Least Significant Bit 3 2 1 0 Address Field Data Field RF R FoLD1 FoLD3 TRIPD_ STATE IDo RF IDo RF RF POL RF R_CNTR[14:0] 0 1 2.5.1 RF R_CNTR[14:0] RF SYNTHESIZER PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) RF R[2:16] The RF reference divider (RF R_CNTR) can be programmed to support divide ratios from 3 to 32767. Divide ratios less than 3 are prohibited. Divide Ratio 14 3 4 0 0 13 0 0 12 0 0 11 0 0 10 0 0 9 0 0 RF R_CNTR[14:0] 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 1 1 1 0 0 1 0 • 32767 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 2.5.2 PD_POL RF RF SYNTHESIZER PHASE DETECTOR POLARITY RF R[17] The PD_POL RF bit is used to control the RF synthesizer’s phase detector polarity based on the VCO tuning characteristics. Control Bit PD_POL RF Register Location RF R[17] Description 0 RF Phase Detector Polarity RF VCO Negative Tuning Characteristics Function 1 RF VCO Positive Tuning Characteristics RF VCO Characteristics 10136682 www.national.com 36 LMX2330U/LMX2331U/LMX2332U 2.0 Programming Description (Continued) RF R[18] 2.5.3 IDo RF RF SYNTHESIZER CHARGE PUMP CURRENT GAIN The IDo RF bit controls the RF synthesizer’s charge pump gain. Two current levels are available. Control Bit IDo RF Register Location RF R[18] Description 0 RF Charge Pump Current Gain LOW 0.95 mA Function 1 HIGH 3.80 mA RF SYNTHESIZER CHARGE PUMP TRI-STATE CURRENT RF R[19] 2.5.4 TRI-STATE IDo RF The TRI-STATE IDo RF bit allows the charge pump to be switched between a normal operating mode and a high impedance output state. This happens asynchronously with the change in the TRI-STATE IDo RF bit. Furthermore, the TRI-STATE IDo RF bit operates in conjuction with the PWDN RF bit to set a synchronous or an asynchronous powerdown mode. Control Bit TRI-STATE IDo RF Register Location RF R[19] Description 0 RF Charge Pump TRI-STATE Current RF Charge Pump Normal Operation Function 1 RF Charge Pump Output in High Impedance State 2.6 IF N REGISTER The IF N register contains the IF N_CNTRA, IF N_CNTRB, PRE IF, and PWDN IF control words. The IF N_CNTRA and IF N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 17 16 15 14 SHIFT REGISTER BIT LOCATION 13 12 11 10 9 8 7 6 5 4 Least Significant Bit 3 2 1 0 Address Field IF N_CNTRA[6:0] 1 0 Data Field IF N PWDN IF PRE IF IF N_CNTRB[10:0] 2.6.1 IF N_CNTRA[6:0] IF SYNTHESIZER SWALLOW COUNTER (A COUNTER) IF N[2:8] The IF N_CNTRA control word is used to setup the IF synthesizer’s A counter. The A counter is a 7-bit swallow counter used in the programmable feedback divider. The IF N_CNTRA control word can be programmed to values ranging from 0 to 15. The three most significant bits are ‘don’t care bits’ in this case. Divide Ratio 6 0 1 X X 5 X X 4 X X IF N_CNTRA[6:0] 3 0 0 2 0 0 1 0 0 0 0 1 • 15 • X • X • X • 1 • 1 • 1 • 1 2.6.2 IF N_CNTRB[10:0] IF SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) IF N[9:19] The IF N_CNTRB control word is used to setup the IF synthesizer’s B counter. The B counter is an 11-bit programmable binary counter used in the programmable feedback divider. The IF N_CNTRB control word can be programmed to values ranging from 3 to 2047. Divide Ratio 3 4 IF N_CNTRB[10:0] 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 1 1 1 0 0 1 0 • 2047 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 37 www.national.com LMX2330U/LMX2331U/LMX2332U 2.0 Programming Description 2.6.3 PRE IF (Continued) IF N[20] IF SYNTHESIZER PRESCALER SELECT The IF synthesizer utilizes a selectable dual modulus prescaler. Control Bit PRE IF Register Location IF N[20] Description 0 IF Prescaler Select 8/9 Prescaler Selected Function 1 16/17 Prescaler Selected IF N[21] 2.6.4 PWDN IF IF SYNTHESIZER POWERDOWN The PWDN IF bit is used to switch the IF PLL between a powered up and powered down mode. Furthermore, the PWDN IF bit operates in conjuction with the TRI-STATE IDo IF bit to set a synchronous or an asynchronous powerdown mode. Control Bit PWDN IF 2.7 RF N REGISTER The RF N register contains the RF N_CNTRA, RF N_CNTRB, PRE RF, and PWDN RF control words. The RF N_CNTRA and RF N_CNTRB control words are used to setup the programmable feedback divider. The detailed description and programming information for each control word is discussed in the following sections. Reg. Most Significant Bit 21 20 19 18 17 16 15 14 SHIFT REGISTER BIT LOCATION 13 12 11 10 9 8 7 6 5 4 Least Significant Bit 3 2 1 0 Address Field RF N_CNTRA[6:0] 1 1 Register Location IF N[21] Description 0 IF Powerdown IF PLL Active Function 1 IF PLL Powerdown Data Field RF N PWDN RF PRE RF RF N_CNTRB[10:0] 2.7.1 RF N_CNTRA[6:0] RF SYNTHESIZER SWALLOW COUNTER (A COUNTER) RF N[2:8] The RF N_CNTRA control word is used to setup the RF synthesizer’s A counter. The A counter is a 7-bit swallow counter used in the programmable feedback divider. The RF N_CNTRA control word can be programmed to values ranging from 0 to 127. Divide Ratio 6 0 1 0 0 5 0 0 4 0 0 RF N_CNTRA[6:0] 3 0 0 2 0 0 1 0 0 0 0 1 • 127 • 1 • 1 • 1 • 1 • 1 • 1 • 1 2.7.2 RF N_CNTRB[10:0] RF SYNTHESIZER PROGRAMMABLE BINARY COUNTER (B COUNTER) RF N[9:19] The RF N_CNTRB control word is used to setup the RF synthesizer’s B counter. The B counter is an 11-bit programmable binary counter used in the programmable feedback divider. The RF N_CNTRB control word can be programmed to values ranging from 3 to 2047. Divide Ratio 3 4 RF N_CNTRB[10:0] 10 0 0 9 0 0 8 0 0 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 1 1 1 0 0 1 0 • 2047 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 www.national.com 38 LMX2330U/LMX2331U/LMX2332U 2.0 Programming Description 2.7.3 PRE RF (Continued) RF N[20] RF SYNTHESIZER PRESCALER SELECT The RF synthesizer utilizes a selectable dual modulus prescaler. LMX2330U RF Synthesizer Prescaler Select Control Bit PRE RF Register Location RF N[20] Description 0 RF Prescaler Select 32/33 Prescaler Selected Function 1 64/65 Prescaler Selected LMX2331U and LMX2332U RF Synthesizer Prescaler Select Control Bit PRE RF Register Location RF N[20] Description 0 RF Prescaler Select 64/65 Prescaler Selected Function 1 128/129 Prescaler Selected 2.7.4 PWDN RF RF SYNTHESIZER POWERDOWN RF N[21] The PWDN RF bit is used to switch the RF PLL between a powered up and powered down mode. Furthermore, the PWDN RF bit operates in conjuction with the TRI-STATE IDo RF bit to set a synchronous or an asynchronous powerdown mode. Control Bit PWDN RF Register Location RF N[21] Description 0 RF Powerdown RF PLL Active Function 1 RF PLL Powerdown 39 www.national.com LMX2330U/LMX2331U/LMX2332U 2.0 Programming Description 2.8 FoLD[3:0] FoLD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 (Continued) [RF R[20], IF R[20], RF R [21], IF R[21]] MULTI-FUNCTION OUTPUT SELECT The FoLD control word is used to select which signal is routed to the FoLD pin. FoLD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FoLD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FoLD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LOW Logic State Output FoLD Output State IF PLL R Divider Output, Push-Pull Output RF PLL R Divider Output, Push-Pull Output Open Drain Fastlock Output IF PLL Analog Lock Detect, Push-Pull Output IF PLL N Divider Output, Push-Pull Output RF PLL N Divider Output, Push-Pull Output Reset IF Counters, LOW Logic State Output RF Analog Lock Detect, Push-Pull Output IF PLL R Divider Output, Push-Pull Output RF PLL R Divider Output, Push-Pull Output Reset RF Counters, LOW Logic State Output RF and IF Analog Lock Detect, Push-Pull Output IF PLL N Divider Output, Push-Pull Output RF PLL N Divider Output, Push-Pull Output Reset All Counters, LOW Logic State Output www.national.com 40 LMX2330U/LMX2331U/LMX2332U Physical Dimensions inches (millimeters) unless otherwise noted 20-Pin Thin Shrink Small Outline Package (TM) NS Package Number MTC20 41 www.national.com LMX2330U/LMX2331U/LMX2332U PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Pin Chip Scale Package (SLB) NS Package Number SLB24A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. 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