LMX2336

LMX2335L/LMX2336L PLLatinum Low Power Dual Frequency Synthesizer for RF Personal Communications PRELIMINARY June 1999 LMX2335L/LMX2336L PLLatinum™ Low Power Dual Frequency Synthesizer for RF Personal Communications LMX2335L LMX2336L 1.1 GHz/1.1 GHz 2.0 GHz/1.1 GHz Features n Ultra low current consumption n 2.7V to 5.5V operation n Selectable synchronous and asynchronous powerdown mode: ICC = 1 µA (typ) n Dual modulus prescaler: 64/65 or 128/129 n Selectable charge pump TRI-STATE ® mode n Selectable charge pump current levels n Selectable Fastlock™ mode n Upgrade and compatible to LMX2335/36 n Small-outline, plastic, surface mount TSSOP package n LMX2336 available in CSP package General Description The LMX2335L and LMX2336L are monolithic, integrated dual frequency synthesizers, including two high frequency prescalers, and are designed for applications requiring two RF phase-lock loops. They are fabricated using National’s 0.5µ ABiC V silicon BiCMOS process. The LMX2335L/36L contains two dual modulus prescalers. A 64/65 or a 128/129 prescaler can be selected for each RF synthesizer. A second reference divider chain is included in the IC for improved system noise. The LMX2335L/36L combined with a high quality reference oscillator, two loop filters, and two external voltage controlled oscillators generates very stable low noise RF local oscillator signals. Serial data is transferred into the LMX2335L/36L via a three wire interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The LMX2335L/36L feature very low current consumption; LMX2335L 4.0 mA at 5V, LMX2336L 5.5 mA at 5V. The LMX2335L is available in SO, TSSOP and CSP 16-pin surface mount plastic packages. The LMX2336L is available in a TSSOP 20-pin and CSP 24-pin surface mount plastic package. Applications n Cellular telephone systems (AMPS, ETACS, RCR-27) n Cordless telephone systems (DECT, ISM , PHS, CT-1+) n Personal Communication Systems (DCS-1800, PCN-1900) n Dual Mode PCS phones n Cable TV Tuners (CATV) n Other wireless communication systems Functional Block Diagram DS012807-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. Fastlock™, MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS012807 www.national.com Connection Diagrams LMX2335L (Top View) LMX2336L (Top View) DS012807-2 Order Number LMX2335LM or LM2335LTM NS Package Number M16A and MTC16 LMX2335L (Top View) DS012807-3 Order Number LMX2336LTM NS Package Number MTC20 LMX2336L (Top View) DS012807-38 Order Number LMX2335LSLB NS Package Number SLB16A DS012807-36 Order Number LMX2336LSLB NS Package Number SLB24A Pin Descriptions Pin No. 2336LTM 1 Pin No. 24 Pin No. 1 Pin No. 2335LSLB 16 Pin Name VCC1 Power supply voltage input for RF1 analog and RF1 digital circuits. Input may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Power supply for RF1 charge pump. Must be ≥ VCC. O RF1 charge pump output. For connection to a loop filter for driving the input of an external VCO. LMX2335L: Ground for RF1 analog and RF1 digital circuits. LMX2336L: Ground for RF digital circuits. I I RF1 prescaler input. Small signal input from the VCO. RF1 prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with loss of some sensitivity. Ground for RF1 analog circuitry. 2 I/O Description 2336LSLB 2335LTM 2 3 4 5 6 2 3 4 5 6 2 3 4 5 X 1 2 3 4 X Vp1 D o1 GND fIN 1 /fIN 1 7 www.national.com 7 X X GND Pin Descriptions Pin No. 2336LTM 8 9 10 Pin No. 8 10 11 (Continued) Pin No. 2335LSLB 5 6 7 Pin Name OSCin OSCout FoLD I O O Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. Oscillator output. Multiplexed output of the programmable or reference dividers, lock detect signals and Fastlock mode. CMOS output (see Programmable Modes). High impedance CMOS Clock input. Data for the various latches is clocked in on the rising edge, into the 20-bit shift register. Binary serial data input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. Load enable high impedance CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 appropriate latches (control bit dependent). Ground for RF2 analog circuitry. I RF2 prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with loss of some sensitivity. RF2 prescaler input. Small signal input from the VCO. LMX2335L: Ground for RF2 analog, RF2 digital, MICROWIRE, FoLD and Oscillator circuits. LMX2336L: Ground for IF digital, MICROWIRE, FoLD and oscillator circuits. O RF2 charge pump output. For connection to a loop filter for driving the input of an external VCO. Power supply for RF2 charge pump. Must be ≥ VCC. Power supply voltage input for RF2 analog, RF2 digital, MICROWIRE, FoLD and oscillator circuits. Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. No connect. I/O Description Pin No. 6 7 8 2336LSLB 2335LTM 11 12 13 12 14 15 9 10 11 8 9 10 Clock Data LE I I I 14 15 16 17 X X X X GND /fIN2 16 17 18 19 12 13 11 12 fIN 2 GND I 18 19 20 20 22 23 14 15 16 13 14 15 Do 2 Vp2 VCC2 X 1, 9, 13, 21 X X NC 3 www.national.com Block Diagram DS012807-4 Note 1: VCC1 supplies power to the RF1 prescaler, N-counter, R-counter, and phase detector. VCC2 supplies power to the RF2 prescaler, N-counter, phase detector, R-counter along with the OSCin buffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same voltage level. Note 2: VP1 and VP2 can be run separately as long as VP ≥ VCC. LMX2335L Pin # → 8/10 ← LMX2336L Pin # Pin Name → FoLD X signifies a function not bonded out to a pin www.national.com 4 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage VCC VP Voltage on Any Pin with GND = 0V (VI) Storage Temperature Range (TS) Lead Temperature (solder 4 sec.) (TL) −0.3V to +6.5V −0.3V to +6.5V −0.3V to VCC +0.3V −65˚C to +150˚C +260˚C Recommended Operating Conditions Power Supply Voltage VCC VP Operating Temperature (TA) 2.7V to 5.5V VCC to +5.5V −40˚C to +85˚C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating < 2 keV and is ESD sensitive. Handling and assembly of this device should only be done at ESD protected work stations. Electrical Characteristics VCC = 5.0V, VP = 5.0V; TA = 25˚C, except as specified Symbol ICC ICC ICC Power Supply Current Parameter LMX2335L RF1 and RF2 LMX2335L RF1 only LMX2336L RF1 and RF2 LMX2336L RF1 only fIN 1 fIN 2 fIN1 fIN2 ICC-PWDN fOSC fOSC fφ PfIN PfIN VOSC VIH VIL IIH IIL IIH IIL IDo-SOURCE IDo-SINK IDo-SOURCE IDo-SINK IDo-TRI VOH VOL Charge Pump TRI-STATE Current High-Level Output Voltage Low-Level Output Voltage Oscillator Sensitivity High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Oscillator Input Current Oscillator Input Current Charge Pump Output Current Maximum Phase Detector Frequency RF Input Sensitivity VCC = 3.0V, f > 100 MHz VCC = 5.0V, f > 100 MHz OSCin (Note 4) (Note 4) VIH = VCC = 5.5V (Note 4) VIL = 0V, VCC = 5.5V (Note 4) VIH = VCC = 5.5V VIL = 0V, VCC = 5.5V VDo = VP/2, ICPo = LOW (Note 3) VDo = VP/2, ICPo = LOW (Note 3) VDo = VP/2, ICPo = HIGH (Note 3) VDo = VP/2, ICPo = HIGH (Note 3) 0.5V ≤ VDo ≤ VCC − 0.5V T = 25˚C IOH = −500 µA IOL = 500 µA 5 Conditions Min VCC = 2.7V to 5.5V Value Typ 4.0 2.0 5.5 3.3 0.100 0.050 0.200 0.050 Max 5.2 2.6 7 4.3 1.1 1.1 2.0 1.1 1 5 5 10 −15 −10 0.5 0.8 VCC 0.2 VCC −1.0 −1.0 −100 −1.25 1.25 −4.25 4.25 −5.0 VCC − 0.4 0.4 5.0 1.0 1.0 100 0 0 10 20 40 Units mA mA mA mA GHz GHz GHz GHz µA MHz MHz MHz dBm VPP V V µA µA µA µA mA mA mA mA nA V V Operating Frequency LMX2335L LMX2336L Powerdown Current Oscillator Frequency LMX2335L/2336L VCC = 5.5V With resonator load on OSCout No load on OSCout www.national.com Electrical Characteristics Symbol tCS tCH tCWH tCWL tES tEW Parameter Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low (Continued) VCC = 5.0V, VP = 5.0V; TA = 25˚C, except as specified Conditions Min See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing 50 10 50 50 50 50 Value Typ Max ns ns ns ns ns ns Units Clock to Load Enable Set Up Time Load Enable Pulse Width Note 3: See PROGRAMMABLE MODES for ICPo description. Note 4: Clock, Data and LE does not include fIN1, fIN2 and OSCin. Charge Pump Current Specification Definitions DS012807-18 I1 = CP sink current at VDo = VP − ∆V I2 = CP sink current at VDo = VP/2 I3 = CP sink current at VDo = ∆V I4 = CP source current at VDo = VP − ∆V I5 = CP source current at VDo = VP/2 I6 = CP source current at VDo = ∆V V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to VCC and ground. Typical values are between 0.5V and 1.0V. 1. IDo vs VDo = Charge Pump Output Current magnitude variation vs Voltage = [1⁄2 * {|I1| − |I3|}]/[1⁄2 * {|I1| + |I3|}] * 100% and [1⁄2 * {|I4| − |I6|}]/[1⁄2 * {|I4| + |I6|}] * 100% 2. IDo-sink vs IDo-source = Charge Pump Output Current Sink vs Source Mismatch = [|I2| − |I5|]/[1⁄2 * {|I2| + |I5|}] * 100% 3. IDo vs TA = Charge Pump Output Current magnitude variation vs Temperature = [|I2 @ temp| − |I2 @ 25˚C|]/|I2 @ 25˚C| * 100% and [|I5 @ temp| − |I5 @ 25˚C|]/|I5 @ 25˚C| * 100% www.national.com 6 RF Sensitivity Test Block Diagram DS012807-19 Note 5: N = 10,000R = 50P = 64 Note 6: Sensitivity limit is reached when the error of the divided RF output, FoLD, is ≥ 1 Hz. Typical Performance Characteristics ICC vs VCC LMX2335L ICC vs VCC LMX2336L DS012807-20 DS012807-21 Charge Pump Current vs Do Voltage Icp = HIGH Charge Pump Current vs Do Voltage Icp = LOW DS012807-22 DS012807-23 7 www.national.com Typical Performance Characteristics LMX2335L Input Impedance (for SO package) VCC = 2.7V to 5.5V, IIN = 50 MHz to 1.5 GHz (Continued) LMX2336L Input Impedance (for TSSOP package) VCC = 2.7V to 5.5V, fIN = 50 MHz to 2.5 GHz DS012807-24 DS012807-25 Marker Marker Marker Marker 1 2 3 4 = = = = 1 GHz, Real = 94, Imaginary = −118 1.2 GHz, Real = 72, Imaginary = −88 1.5 GHz, Real = 53, Imaginary = −45 500 MHz, Real = 201, Imaginary = −224 Marker Marker Marker Marker 1 2 3 4 = = = = 1 GHz, Real = 97, Imaginary = −146 1.89 GHz, Real = 43, Imaginary = −67 2.5 GHz, Real = 30, Imaginary = −33 500 MHz, Real = 189, Imaginary = −233 LMX2335L Input Impedance (for TSSOP package) VCC = 2.7V to 5.5V, fIN = 50 MHz to 2.5 GHz DS012807-31 www.national.com 8 Typical Performance Characteristics IDO TRI-STATE vs Do Voltage (Continued) LMX2335L RF1 Sensitivity vs Frequency DS012807-27 DS012807-26 LMX2335L RF2 Sensitivity vs Frequency LMX2336L RF1 Sensitivity vs Frequency DS012807-28 DS012807-29 LMX2336L RF2 Sensitivity vs Frequency Oscillator Input Sensitivity vs Frequency DS012807-30 DS012807-37 9 www.national.com Functional Description The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and two 18-bit N Counters (intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The data stored in the shift register is loaded into one of the 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits. The DATA is transferred into the counters as follows: Control Bits C1 0 0 1 1 C2 0 1 0 1 RF2 R Counter RF1 R Counter RF2 N Counter RF1 N Counter DATA Location DS012807-5 PROGRAMMABLE REFERENCE DIVIDERS (RF1 AND RF2 R COUNTERS) If the Control Bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transferred from the 22-bit shift register into a latch which sets the 15-bit R Counter. Serial data format is shown below. DS012807-6 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) Divide 3 4 R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 9 0 0 R 8 0 0 R 7 0 0 R 6 0 0 R 5 0 0 R 4 0 0 R 3 0 1 R 2 1 0 R 1 1 0 Ratio 15 14 13 12 11 10 • 32767 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 Notes: Divide ratios less than 3 are prohibited. Divide ratio: 3 to 32767 R1 to R15: These bits select the divide ratio of the programmable reference divider. Data is shifted in MSB first. www.national.com 10 Functional Description (Continued) PROGRAMMABLE DIVIDER (N COUNTER) Each N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bits are 10 or 11 (10 for RF2 counter and 11 for RF1 counter) data is transferred from the 20-bit shift register into a 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data format is shown below. DS012807-7 7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) Divide Ratio A 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 N 7 N 6 N 5 N 4 N 3 N 2 N 1 • 127 • 1 • 1 • 1 • 1 • 1 • 1 • 1 Notes: Divide ratio: 0 to 127 B≥A A