LMX2502LQ1635

LMX2502/LMX2512 Frequency Synthesizer System with Integrated VCO June 2003 LMX2502/LMX2512 PLLatinum™ Frequency Synthesizer System with Integrated VCO General Description LMX2502 and LMX2512 are highly integrated, high performance, low power frequency synthesizer systems optimized for Korean PCS and Korean Cellular CDMA (1xRTT, IS-95) mobile handsets. Using a proprietary digital phase locked loop technique, LMX2502 and LMX2512 generate very stable, low noise local oscillator signals for up and down conversion in wireless communications devices. LMX2502 and LMX2512 include a voltage controlled oscillator (VCO), a loop filter, and a fractional-N RF PLL based on a delta sigma modulator. In concert these blocks form a closed loop RF synthesizer system. LMX2502 supports the Korean PCS band and LMX2512 supports the Korean Cellular band. LMX2502 and LMX2512 include an Integer-N IF PLL also. For more flexible loop filter designs, the IF PLL includes a 4-level programmable charge pump. Together with an external VCO and loop filter, LMX2502 and LMX2512 make a complete closed loop IF synthesizer system. Serial data is transferred to the device via a three-wire MICROWIRE interface (DATA, LE, CLK). Operating supply voltage ranges from 2.7 V to 3.3 V. LMX2502 and LMX2512 feature low current consumption: 17 mA at 2.8 V. LMX2502 and LMX2512 are available in a 28-pin leadless leadframe package (LLP). Features n Small Size 5.0 mm X 5.0 mm X 0.75 mm 28-Pin LLP Package n RF Synthesizer System Integrated RF VCO Integrated Loop Filter Low Spurious, Low Phase Noise Fractional-N RF PLL Based on 11-Bit Delta Sigma Modulator 10 kHz Frequency Resolution n IF Synthesizer System Integer-N IF PLL Programmable Charge Pump Current Levels Programmable Frequency n Supports Various Reference Frequencies 19.20/19.68 MHz n Fast Lock Time: 500 µs n Low Current Consumption 17 mA at 2.8 V n 2.7 V to 3.3 V Operation n Digital Filtered Lock Detect Output n Hardware and Software Power Down Control Applications n Korean PCS CDMA Systems n Korean Cellular CDMA Systems Functional Block Diagram 20068001 PLLatinum™ is a trademark of National Semiconductor Corporation. © 2003 National Semiconductor Corporation DS200680 www.national.com LMX2502/LMX2512 Connection Diagram 28-Pin LLP (LQ) Package 20068002 NOTE: Analog ground connected through exposed die attached pad. Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name CPout NC NC VDD LE CLK DATA VDD NC NC NC NC VDD VDD RFout VCC VCC VCC LD CE GND OSCin VCC GND VCC Fin VCC NC I/O O – – – I I I – – – – – – – O – – – O I – I – – – I – – Description IF PLL charge pump output Do not connect to any node on the printed circuit board. Do not connect to any node on the printed circuit board. Supply voltage for IF analog circuitry MICROWIRE Latch Enable MICROWIRE Clock MICROWIRE Data Supply voltage for VCO Do not connect to any node on the printed circuit board. Do not connect to any node on the printed circuit board. Do not connect to any node on the printed circuit board. Do not connect to any node on the printed circuit board. Supply voltage for VCO Supply voltage for VCO output buffer Buffered VCO output Supply voltage for RF prescaler Supply voltage for charge pump Supply voltage for RF digital circuitry Lock Detect Chip Enable control pin Ground for digital circuitry Reference frequency input Supply voltage for reference input buffer Ground for digital circuitry Supply voltage for IF digital circuitry IF buffer/prescaler input Supply voltage for IF buffer/prescaler Do not connect to any node on the printed circuit board. www.national.com 2 LMX2502/LMX2512 Ordering Information Part Number LMX2502LQX1635 LMX2502LQ1635 LMX2512LQX0967 LMX2512LQ0967 LMX2512LQX1065 LMX2512LQ1065 RF Min. (MHz) 1619.62 1619.62 954.42 954.42 1052.64 1052.64 RF Max. (MHz) 1649.62 1649.62 979.35 979.35 1077.57 1077.57 RF Center (MHz) ~1635 ~1635 ~967 ~967 ~1065 ~1065 IF (MHz) 440.76 440.76 170.76 170.76 367.20 367.20 Package Marking 25021635 25021635 25120967 25120967 25121065 25121065 Supplied As 4500 units on tape and reel 1000 units on tape and reel 4500 units on tape and reel 1000 units on tape and reel 4500 units on tape and reel 1000 units on tape and reel Part Number Description 20068003 3 www.national.com LMX2502/LMX2512 Absolute Maximum Ratings 2, 3) (Notes 1, Recommended Operating Conditions Parameter Ambient Temperature Symbol TA Min Typ Max Units -30 25 85 3.3 ˚C V If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Supply Voltage Voltage on any pin to GND Symbol VI Ratings -0. 3 to VCC+0.3 -0. 3 to VDD+0.3 -65 to 150 Units V V V ˚C Supply Voltage (to GND) VCC, VDD 2.7 VCC, VDD -0.3 to 3.6 Storage Temperature TSTG Range Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, refer to the Electrical Characteristics section. The guaranteed specifications apply only for the conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating < 2 kV and is ESD sensitive. Handling and assembly of this device should be done at ESD protected work stations. Note 3: GND = 0 V. Electrical Characteristics Symbol ICC + IDD (ICC + IDD)RF IPD Parameter Total Supply Current RF PLL Total Supply Current Power Down Current (Note 4) ICC PARAMETERS (VCC = VDD = 2.8 V, TA = 25 ˚C; unless otherwise noted) Condition OB_CRL [1:0] = 00 OB_CRL [1:0] = 00 CE = LOW or RF_EN = 0 IF_EN = 0 19.20 MHz and 19.68 MHz are supported 19.20 0.2 RF VCO 1619.62 954.42 1052.64 OB_CRL [1:0] = 11 OB_CRL [1:0] = 10 OB_CRL [1:0] = 01 OB_CRL [1:0] = 00 -2 -5 -7 -9 1 -2 -4 -6 500 500 500 Min Typ 17 16 Max 19 18 20 Units mA mA µA REFERENCE OSCILLATOR PARAMETERS fOSCin VOSCin RF VCO fRFout Frequency Range (Note 6) RF Output Power LMX2502LQ1635 LMX2512LQ0967 LMX2512LQ1065 PRFout 1649.62 979.35 1077.57 4 1 -1 -3 800 800 800 -75 RF PLL in all band LMX2502LQ1635 LMX2512LQ0967 LMX2512LQ1065 2nd Harmonic Suppression 3rd Harmonic Suppression @ 100 kHz offset @ 1.25 MHz offset @ 100 kHz offset @ 900 kHz offset @ 100 kHz offset @ 900 kHz offset Reference Oscillator Input Frequency (Note 5) Reference Oscillator Input Sensitivity 19.68 VCC MHz Vp-p MHz MHz MHz dBm dBm dBm dBm µs µs µs dBc degrees dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc dBc Lock Time (Note 7) LMX2502LQ1635 LMX2512LQ0967 LMX2512LQ1065 30 MHz Band for RF PLL 25 MHz Band for RF PLL 25 MHz Band for RF PLL Reference Spurs RMS Phase Error L(f)RFout Phase Noise 1.3 -113 -138 -117 -139 -117 -139 -112 -136 -115 -138 -115 -138 -25 -20 www.national.com 4 LMX2502/LMX2512 Electrical Characteristics (VCC = VDD = 2.8 V, TA = 25 ˚C; unless otherwise noted) Symbol IF PLL fFin Operating Frequency LMX2502LQ1635 (Note 8) LMX2512LQ0967 LMX2512LQ1065 PFin fΦIF ICPout IF Input Sensitivity Phase Detector Frequency Charge Pump Current IF_CUR [1:0] = 00 IF_CUR [1:0] = 01 IF_CUR [1:0] = 10 IF_CUR [1:0] = 11 DIGITAL INTERFACE (DATA, CLK, LE, LD, CE) VIH VIL IIH IIL VOH VOL High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current Input Capacitance High-Level Output Voltage Low-Level Output Voltage Output Capacitance MICROWIRE INTERFACE TIMING tCS tCH tCWH tCWL tES tEW Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width HIGH Clock Pulse Width LOW Clock to Latch Enable Set Up Time Latch Enable Pulse Width 50 10 50 50 50 50 0.9 VDD 0.9 VCC 0.8 VDD 0.8 VCC 0 0 -10 -10 3 IF_FREQ [1:0] = 10, Default Value IF_FREQ [1:0] = 00, Default Value IF_FREQ [1:0] = 01, Default Value -10 120 100 200 300 800 Parameter Condition Min Typ (Continued) Max Units MHz MHz MHz 0 dBm kHz µA µA µA µA VDD VCC 0.2 VDD 0.2 VCC 10 10 V V V V µA µA pF V V 0.1 VDD 0.1 VCC 5 V V pF ns ns ns ns ns ns 440.76 170.76 367.20 Note 4: In power down mode, set DATA, CLK, and LE pins to 0 V (GND). Note 5: The reference frequency must also be programmed using the OSC_FREQ control bit. For other reference frequencies, please contact National Semiconductor. Note 6: For other frequency ranges, please contact National Semiconductor. Note 7: Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/- 1 kHz of the final frequency. Note 8: Frequencies other that the default value can be programmed using Words R4 and R5. See Programming Description for details. 5 www.national.com LMX2502/LMX2512 Microwire Interface Timing Diagram 20068004 www.national.com 6 LMX2502/LMX2512 Functional Description GENERAL DESCRIPTION LMX2502/12 is a highly integrated frequency synthesizer system that generates LO signals for PCS and Cellular CDMA applications. These devices include all the functional blocks of a PLL, RF VCO, prescaler, RF phase detector, and loop filter. The need for external components is limited to a few passive elements for matching the output impedance and bypass elements for power line stabilization. In addition to the RF circuitry, the IC also includes IF frequency dividers, and an IF phase detector to complete the IF synthesis with the external VCO and the loop filter. Table 1 summarizes the counter values used to generate the default IF frequencies. Using a low spurious fractional-N synthesizer based on a delta sigma modulator, the circuit can support 10 kHz channel spacing for PCS and Cellular CDMA systems. The fractional-N synthesizer enables faster lock time, which reduces power consumption and system set-up time. Additionally, the loop filter occupies a smaller area as opposed to the integer-N architecture. This allows the loop filter to be embedded into the circuit, minimizing the external noise coupling and total form factor. The delta sigma architecture delivers very low spurious, which can be a significant problem for other PLL solutions. The circuit also supports commonly used reference frequencies of 19.20 MHz and 19.68 MHz. FREQUENCY GENERATION RF-PLL Section The divide ratio can be calculated using the following equation: LMX2502 – PCS CDMA: fVCO = {8 x RF_B + RF_A + (RF_FN / fOSC) x 104} x fOSC where (RF_A < RF_B) LMX2512 – Cellular CDMA: fVCO = {6 x RF_B + RF_A + (RF_FN / fOSC) x 104} x fOSC where (RF_A < RF_B) where fVCO: Output frequency of voltage controlled oscillator (VCO) RF_B: Preset divide ratio of binary 4-bit programmable counter (2 ≤ RF_B ≤ 15) RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤ RF_A ≤ 7 for LMX2502 or 0 ≤ RF_A ≤ 5 for LMX2512) RF_FN: Preset numerator of binary 11-bit modulus counter (0 ≤ RF_FN < 1920 for fOSC = 19.20 MHz or 0 ≤ RF_FN < 1968 for fOSC = 19.68 MHz) fOSC: Reference oscillator frequency IF-PLL Section fVCO = {16 x IF_B + IF_A} x fOSC / IF_R where (IF_A < IF_B) where fVCO: Output frequency of the voltage controlled oscillator (VCO) IF_B: Preset divide ratio of the binary 9-bit programmable counter (1 ≤ IF_B ≤ 511) IF_A: Preset divide ratio of the binary 4-bit swallow counter (0 ≤ IF_A ≤ 15) fOSC: Reference oscillator frequency IF_R: Preset divide ratio of the binary 9-bit programmable reference counter (2 ≤ IF_R ≤ 511) From the above equation, the LMX2502/12 generates the fixed IF frequencies as summarized in Table 1. TABLE 1. IF Frequencies Device Type LMX2502LQ1635 LMX2512LQ0967 LMX2512LQ1065 FVCO (MHz) 440.76 170.67 367.20 IF_B 229 88 191 IF_A 9 15 4 fOSC/IF_R (kHz) 120 120 120 VCO FREQUENCY TUNING The center frequency of the RF VCO is determined by the resonant frequency of the tank circuit. This tank circuit is implemented on-chip and requires no external inductor. The LMX2502/12 actively tunes the tank circuit to the required frequency with the built-in tracking algorithm. BANDWIDTH CONTROL AND FREQUENCY LOCK During the frequency acquisition period, the loop bandwidth is significantly extended to achieve frequency lock. Once frequency lock occurs, the PLL will return to a steady state condition with the loop bandwidth set to its nominal value. The transition between acquisition and lock modes occurs seamlessly and extremely fast, thereby, meeting the stringent requirements associated with lock time and phase noise. Several controls (BW_DUR, BW_CRL, and BW_EN) are used to optimize the lock time performance. SPURIOUS REDUCTION To improve the spurious performance of the device one of two types of spurious reduction schemes can be selected: • A continuous optimization scheme, which tracks the environmental and voltage variations, giving the best spurious performance over changing conditions • A one time optimization scheme, which sets the internal compensation values only when the PLL goes into a locked state. The spurious reduction can also be disabled, but it is recommended that the continuous optimization mode be used for normal operation. POWER DOWN MODE The LMX2502 and LMX2512 include a power down mode to reduce the power consumption. The LMX2502/12 enters into the power down mode either by taking the CE pin LOW or by setting the power down bits in Register R1. Table 2 summarizes the power down function. If CE is set LOW, the circuit is powered down regardless of the register values. When CE is HIGH, the IF and RF circuitry are individually powered down by setting the register bits. 7 www.national.com LMX2502/LMX2512 Functional Description CE Pin 0 1 1 1 1 RF_EN X 0 0 1 1 IF_EN X 0 1 0 1 (Continued) TABLE 2. Power Down Configuration RF Circuitry OFF OFF OFF ON ON IF Circuitry OFF OFF ON OFF ON LD pin remains LOW. After obtaining phase lock, the LD pin will have a logical HIGH level. The output can also be programmed to be ground at all times. TABLE 3. Lock Detect Modes LD Bit 0 1 Mode Disable (GND) Enable TABLE 4. Lock Detect Logic RF PLL Section LD Output HIGH LOW X = Don’t care. LOCK DETECT The LD output can be used to indicate the lock status of the RF PLL. Bit 21 in Register R0 determines the signal that appears on the LD pin. When the RF PLL is not locked, the Locked Not Locked 20068005 FIGURE 1. Lock Detect Timing Diagram Waveform (Notes 9, 10, 11, 12, 13) Note 9: LD output becomes LOW when the phase error is larger than tW2. Note 10: LD output becomes HIGH when the phase error is less than tW1 for four or more consecutive cycles. Note 11: Phase Error is measured on leading edge. Only errors greater than tW1 and tW2 are labeled. Note 12: tW1 and tW2 are equal to 10 ns. Note 13: The lock detect comparison occurs with every 64th cycle of fR and fN. www.national.com 8 LMX2502/LMX2512 Functional Description (Continued) 20068006 FIGURE 2. Lock Detect Flow Diagram MICROWIRE INTERFACE The programmable register set is accessed via the MICROWIRE serial interface. The interface comprises three signal pins: CLK, DATA, and LE (Latch Enable). Serial data (DATA) is clocked into the 24-bit shift register on the rising edge of the clock (CLK). The last bits decode the internal control register address. When the latch enable (LE) transitions from LOW to HIGH, data stored in the shift registers is loaded into the corresponding control register. 9 www.national.com LMX2502/LMX2512 Programming Description GENERAL PROGRAMMING INFORMATION The serial interface has a 24-bit shift register to store the incoming data bits temporarily. The incoming data is loaded into the shift register from MSB to LSB. The data is shifted at the rising edge of the clock signal. When the latch enable signal transitions from LOW to HIGH, the data stored in the shift register is transferred to the proper register depending on the address bit settings. The selection of the particular register is determined by the address bits equal to the binary representation of the number of the control register. At initial start-up, the MICROWIRE loading requires 4 default words (registers R3, loaded first, to R0, loaded last). After the device has been initially programmed, the RF VCO frequency can be changed using a single register (R0). If an IF frequency other than the default value for the device is desired the SPI_DEF bit should be set to 0, the desired values for IF_A, IF_B, and IF_R entered and words R6 to R0 should be sent. The control register content map describes how the bits within each control register are allocated to the specific control functions. COMPLETE REGISTER MAP Register MSB 23 22 21 20 19 0 RF_B [3:0] 0 0 0 0 SHIFT REGISTER BIT LOCATION 18 17 16 15 14 13 12 RF_A [2:0] 0 0 0 SPUR_ RDT [1:0] 1 0 1 1 0 11 10 9 8 7 6 5 RF_FN [10:0] 0 1 0 1 OB_ CRL [1:0] 10100 00110 0 4 3 2 LSB 10 00 RF_ IF_ 0 1 EN EN 1 0 0 10 11 R0 SPI_ RF_ RF_ (Default) DEF SEL LD R1 IF_ (Default) FREQ [1:0] R2 IF_ (Default) CUR[1:0] R3 BW_ (Default) DUR [1:0] R4 R5 R6 0 0 1 0 0 0 OSC_ 1 FREQ 0 BW_ CRL [1:0] 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 1 0 1 0 0 BW_ 1 EN 0 0 0 0 0 0 VCO_ CUR [1:0] 0 0 1 1 1 0 0 0 0 0 IF_A [3:0] 1 0 0 0 0 0 0 IF_B [8:0] IF_R [8:0] 0 00000 1 1 1 11 11 11 NOTE: Bold numbers represent the address bits. www.national.com 10 LMX2502/LMX2512 Programming Description R0 REGISTER (Continued) The R0 register address bits (R0 [1:0]) are “00”. The SPI_DEF bit selects between using the default IF counter values and user programmable values. The use of the default counter values requires that only words R0 to R3 (registers R3, loaded first, to R0, loaded last) be sent after initial power up. The RF_LD bit activates the lock detect output of the LD pin (pin 19). The lock detect mode shows the lock status of the RF PLL. The waveform of the lock detect mode is shown in Figure 1, in the Functional Description section on LOCK DETECT. The RF N counter consists of the 4-bit programmable counter (RF_B counter), the 3-bit swallow counter (RF_A counter) and the 11-bit delta sigma modulator (RF_FN counter). The equations for calculating the counter values are presented below. R0 REGISTER MSB Register 23 22 21 20 19 18 17 SHIFT REGISTER BIT LOCATION 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Data Field SPI_ DEF RF_ SEL RF_ LD 0 RF_B [3:0] RF_A [2:0] RF_FN [10:0] LSB 0 Address Field 0 0 R0 (Default) Name SPI_DEF Functions Default Register Selection 0 = OFF (Use values set in R0 to R6) 1 = ON (Use default values set in R0 to R3) RF VCO Selection 0 = LMX2512 1 = LMX2502 RF Lock Detect 0 = Hard zero (GND) 1 = Lock detect RF_B Counter 4-bit programmable counter 2 ≤ RF_B ≤ 15 RF_A Counter 3-bit swallow counter 0 ≤ RF_A ≤ 7 for LMX2502 0 ≤ RF_A ≤ 5 for LMX2512 RF Fractional Numerator Counter 11-bit programmable counter 0 ≤ RF_FN < 1920 for fOSC = 19.20 MHz 0 ≤ RF_FN < 1968 for fOSC = 19.68 MHz RF_SEL RF_LD RF_B [3:0] RF_A [2:0] RF_FN [10:0] 11 www.national.com LMX2502/LMX2512 Programming Description RF N Counter Setting: Counter Name Modulus Counter Programmable Counter Swallow Counter (Continued) Symbol RF_FN RF_B RF_A Function RF N Divider N = Prescaler x RF_B + RF_A + (RF_FN / fOSC) x 104 Pulse Swallow Function: fVCO = {Prescaler x RF_B + RF_A + (RF_FN / fOSC) x 104} x fOSC where (RF_A < RF_B) where fVCO: Output frequency of voltage controlled oscillator (VCO) Prescaler Values: Device Type LMX2502 LMX2512 RF Prescaler 8 6 RF_B: Preset divide ratio of binary 4-bit programmable counter (2 ≤ RF_B ≤ 15) RF_A: Preset divide ratio of binary 3-bit swallow counter (0 ≤ RF_A ≤ 7 for LMX2502, 0 ≤ RF_A ≤ 5 for LMX2512) RF_FN: Preset numerator of binary 11-bit modulus counter (0 ≤ RF_FN < 1920 for fOSC = 19.20 MHz; 0 ≤ RF_FN < 1968 for fOSC = 19.68 MHz). fOSC: Reference oscillator frequency NOTE: For the use of reference frequencies other than those specified, please contact National Semiconductor. www.national.com 12 LMX2502/LMX2512 Programming Description R1 REGISTER (Continued) The R1 register address bits (R1 [1:0]) are “01”. The IF_FREQ bits selects the default IF frequency applicable to the specific CDMA system. For the LMX2502 the default IF frequency is 440.76 MHz, and for the LMX2512 the default IF frequencies are 367.20 MHz and 170.76 MHz, depending on variant. Reference Frequency Selection bit (OSC_FREQ) selects either 19.20 MHz or 19.68 MHz for the reference oscillator frequency. The internal spurious reduction scheme is controlled by the SPUR_RDT [1:0] bits. There are two different spur reduction schemes: a continuous tracking mode and a single optimization mode. The continuous tracking mode will adjust for variations in voltage and temperature. The single optimization mode fixes the internal compensation parameters only when the PLL goes into the locked state. The spur reduction can also be disabled, but it is recommended that the continuous mode be used for normal operation. The OB_CRL [1:0] bits determine the power level of the RF output buffer. The power level can be set according to the system requirement. The two bits, RF_EN and IF_EN, logically select the active state of the RF synthesizer system and the IF PLL, respectively. The entire IC can be placed in a power down state by using the CE control pin (pin 20). R1 REGISTER MSB Register 23 22 21 SHIFT REGISTER BIT LOCATION 20 19 18 17 16 15 14 13 12 Data Field OSC_ 1 FREQ 0 0 0 0 0 0 0 SPUR_ RDT [1:0] 0 0 1 0 1 OB_ CRL [1:0] 11 10 9 8 7 6 5 4 3 2 1 LSB 0 Address Field RF_ IF_ 0 EN EN 1 R1 IF_ (Default) FREQ [1:0] Name IF_FREQ [1:0] Functions IF Frequency Selection 00 = 170.76 MHz (LMX2512LQ0967) 01 = 367.20 MHz (LMX2512LQ1065) 10 = 440.76 MHz (LMX2502LQ1635) Reference Frequency Selection 0 = 19.20 MHz 1 = 19.68 MHz Spur Reduction Scheme 00 = No spur reduction 01 = Not Used 10 = Continuous tracking of variation (Recommended) 11 = One time optimization RF Output Power Control 00 = Minimum Output Power 01 = 10 = 11 = Maximum Output Power RF Enable 0 = RF Off 1 = RF On IF Enable 0 = IF Off 1 = IF On OSC_FREQ SPUR_RDT [1:0] OB_CRL [1:0] RF_EN IF_EN 13 www.national.com LMX2502/LMX2512 Programming Description R2 REGISTER (Continued) The R2 Register address bits (R2 [1:0]) are “10”. The IF_CUR [1:0] bits program the IF charge-pump current. Considering the external IF VCO and loop filter, the user can select the amount of IF charge pump current to be 100 µA, 200 µA, 300 µA or 800 µA. R2 REGISTER MSB Register 23 22 21 20 19 18 17 SHIFT REGISTER BIT LOCATION 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Data Field IF_ CUR[1:0] 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 0 0 0 1 0 LSB 0 Address Field 1 0 R2 (Default) Name IF_CUR [1:0] Functions IF Charge Pump Current 00 = 100 µA 01 = 200 µA 10 = 300 µA 11 = 800 µA www.national.com 14 LMX2502/LMX2512 Programming Description R3 REGISTER (Continued) The R3 register address bits (R3 [2:0]) are “011”. Register R3 contains the controls for the phase lock bandwidth controls (BW_DUR, BW_CRL, and BW_EN). The duration of the digital controller portion of the bandwidth control is set by BW_DUR [1:0]. The minimum time set with 00 and increasing durations to the maximum value set with 11. BW_CRL [1:0] sets the phase offset criterion for the bandwidth controller. Once the phase offset between the reference clock and the divided VCO signal are within the set criterion, the bandwidth control stops. The maximum phase offset is set with 00 and decreases to the minimum value set with 11. BW_EN enables the bandwidth control in the locking state. The VCO dynamic current is also controlled in register R3 with VCO_CUR [1:0]. The minimum value corresponds to 00 and increases to a maximum value set at 11. R3 REGISTER MSB Register 23 22 21 20 19 18 17 SHIFT REGISTER BIT LOCATION 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Data Field BW_ DUR [1:0] BW_ CRL [1:0] BW_ EN 1 0 1 1 1 1 0 1 0 0 0 1 1 0 VCO_ CUR [1:0] 0 LSB 0 Address Field 1 1 R3 (Default) Name BW_DUR [1:0] Functions Bandwidth Duration 00 = Minimum value (Recommended) 01 = 10 = 11 = Maximum value Bandwidth Control 00 = Maximum phase offset (Recommended) 01 = 10 = 11 = Minimum phase offset Bandwidth Enable 0 = Disable 1 = Enable (Recommended) VCO Dynamic Current 00 = Minimum value 01 = 10 = 11 = Maximum value (Recommended) BW_CRL [1:0] BW_EN VCO_CUR [1:0] 15 www.national.com LMX2502/LMX2512 Programming Description R4 REGISTER (Continued) The R4 register address bits (R3 [3:0]) are “0111”. Register R4 is used to set the IF N counters if the default value is not desired. This register is only active if the SPI_DEF bit in register R0 is 0. R4 REGISTER MSB Register 23 22 21 20 19 18 17 SHIFT REGISTER BIT LOCATION 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Data Field 0 0 0 1 0 0 0 IF_A [3:0] IF_B [8:0] 0 LSB 0 Address Field 1 1 1 R4 Name IF_A [3:0] Functions IF A Counter 4-bit swallow counter 0 ≤ IF_A ≤ 15 IF B Counter 9-bit programmable counter 1 ≤ IF_B ≤ 511 IF_B [8:0] IF Frequency Setting: fVCO = {16 x IF_B + IF_A} x fOSC / IF_R where (IF_A < IF_B) where fVCO: Output frequency of IF voltage controlled oscillator (IF VCO) IF_B: Preset divide ratio of binary 9-bit programmable counter (1 ≤ IF_B ≤ 511) IF_A: Preset divide ratio of binary 4-bit swallow counter (0 ≤ IF_A ≤ 15) IF_R: Preset divide ratio of binary 9-bit programmable reference counter (2 ≤ IF_R ≤ 511) fOSC: Reference oscillator frequency www.national.com 16 LMX2502/LMX2512 Programming Description R5 REGISTER (Continued) The R5 register address bits (R5 [4:0]) are “01111”. Register R5 is used to set the IF_R divider if the default value is not desired. This register is only active if the SPI_DEF bit in register R0 is 0. R5 REGISTER MSB Register 23 22 21 20 19 18 17 SHIFT REGISTER BIT LOCATION 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Data Field 0 0 1 1 0 0 0 0 1 0 IF_R [8:0] 0 1 Address Field 1 1 1 LSB 0 R5 Name IF_R [8:0] Functions IF R Counter 9-bit programmable counter 2 ≤ IF_R ≤ 511 R6 REGISTER The R6 register address bits (R6 [5:0]) are “011111”. Register R6 is used for internal testing of the device and is not intended for customer use. This register is only active if the SPI_DEF bit in register R0 is 0. R6 REGISTER Register MSB 23 1 22 0 21 0 20 0 19 0 18 0 17 0 SHIFT REGISTER BIT LOCATION 16 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 1 3 1 2 1 1 1 Data Field Address Field 1 LSB 0 R6 17 www.national.com LMX2502/LMX2512 Frequency Synthesizer System with Integrated VCO Physical Dimensions inches (millimeters) unless otherwise noted Leadless Leadframe Package (LLP) NS Package Number LQA28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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