LMX2531

LMX2531 High Performance Frequency Synthesizer System with Integrated VCO June 23, 2009 LMX2531 High Performance Frequency Synthesizer System with Integrated VCO General Description The LMX2531 is a low power, high performance frequency synthesizer system which includes a fully integrated deltasigma PLL and VCO with fully integrated tank circuit. The third and fourth poles are also integrated and also adjustable. Also included are integrated ultra-low noise and high precision LDOs for the PLL and VCO which give higher supply noise immunity and also more consistent performance. When combined with a high quality reference oscillator, the LMX2531 generates very stable, low noise local oscillator signals for up and down conversion in wireless communication devices. The LMX2531 is a monolithic integrated circuit, fabricated in an advanced BiCMOS process. There are several different versions of this product in order to accommodate different frequency bands. Device programming is facilitated using a three-wire MICROWIRE Interface that can operate down to 1.8 volts. Supply voltage range is 2.8 to 3.2 Volts. The LMX2531 is available in a 36 pin 6x6x0.8 mm Lead-Free Leadless Leadframe Package (LLP). Features ■ Multiple Frequency Options Available — See Selection Guide Below — Frequencies from: 553 MHz - 3132 MHz ■ PLL Features — Fractional-N Delta Sigma Modulator Order programmable up to 4th order — FastLock/Cycle Slip Reduction with Timeout Counter — Partially integrated, adjustable Loop Filter — Very low phase noise and spurs ■ VCO Features — Integrated tank inductor — Low phase noise ■ Other Features — 2.8 V to 3.2 V Operation — Low Power-Down Current — 1.8 V MICROWIRE Support — Package: 36 Lead LLP Part LMX2531LQ1146E LMX2531LQ1226E LMX2531LQ1312E LMX2531LQ1415E LMX2531LQ1515E LMX2531LQ1570E LMX2531LQ1650E LMX2531LQ1700E LMX2531LQ1742 LMX2531LQ1778E LMX2531LQ1910E LMX2531LQ2080E Low Band 553 - 592 MHz 592 - 634 MHz 634 - 680 MHz 680 - 735 MHz 725 - 790 MHz 765 - 818 MHz 795 - 850 MHz 831 - 885 MHz 880 - 933 MHz 863 - 920 MHz 917 - 1014 MHz 952 - 1137 MHz High Band 1106 - 1184 MHz 1184 - 1268 MHz 1268 - 1360 MHz 1360 - 1470 MHz 1450 - 1580 MHz 1530 - 1636 MHz 1590 - 1700 MHz 1662 - 1770 MHz 1760 - 1866 MHz 1726 - 1840 MHz 1834 - 2028 MHz 1904 - 2274 MHz Target Applications ■ 3G Cellular Base Stations (WCDMA, TD■ ■ ■ ■ ■ ■ ■ ■ ■ SCDMA,CDMA2000) 2G Cellular Base Stations (GSM/GPRS, EDGE, CDMA1xRTT) Wireless LAN Broadband Wireless Access Satellite Communications Wireless Radio Automotive CATV Equipment Instrumentation and Test Equipment RFID Readers LMX2531LQ2265E 1089 - 1200 MHz 2178 - 2400 MHz LMX2531LQ2570E 1168 - 1395 MHz 2336 - 2790 MHz LMX2531LQ2820E 1355 - 1462 MHz 2710 - 2925 MHz LMX2531LQ3010E 1455 - 1566 MHz 2910 - 3132 MHz © 2009 National Semiconductor Corporation 201011 www.national.com LMX2531 Functional Block Diagram 20101101 www.national.com 2 LMX2531 Connection Diagrams 36-Pin LLP (LQ) Package, D Version (LMX2531LQ1146E/1226E/1312E/1415E/1515E/2820E/3010E) 20101104 36-Pin LLP (LQ) Package, A Version (All Other Versions) 20101102 3 www.national.com LMX2531 Pin Descriptions Pin # 1 3 2,4,5,7, 12, 13, 29, 35 6 8 9 10 Pin Name VccDIG GND NC VregBUF DATA CLK LE I/O I I I Description Power Supply for digital LDO circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. Ground No Connect. Internally regulated voltage for the VCO buffer circuitry. Connect to ground with a capacitor. MICROWIRE serial data input. High impedance CMOS input. This pin must not exceed 2.75V. Data is clocked in MSB first. The last bits clocked in form the control or register select bits. MICROWIRE clock input. High impedance CMOS input. This pin must not exceed 2.75V. Data is clocked into the shift register on the rising edge. MICROWIRE Latch Enable input. High impedance CMOS input. This pin must not exceed 2.75V. Data stored in the shift register is loaded into the selected latch register when LE goes HIGH. Chip Enable Input. High impedance CMOS input. This pin must not exceed 2.75V. When CE is brought high the LMX2531 is powered up corresponding to the internal power control bits. Although the part can be programmed when powered down, it is still necessary to reprogram the R0 register to get the part to re-lock. No Connect. Do NOT ground. Power Supply for VCO regulator circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. Internally regulated voltage for VCO circuitry. Not intended to drive an external load. Connect to ground with a capacitor and some series resistance. Internal reference voltage for VCO LDO. Not intended to drive an external load. Connect to ground with a capacitor. Ground for the VCO circuitry. Ground for the VCO Output Buffer circuitry. Buffered RF Output for the VCO. Power Supply for the VCO Buffer circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. Tuning voltage input for the VCO. For connection to the CPout Pin through an external passive loop filter. Charge pump output for PLL. For connection to Vtune through an external passive loop filter. An open drain NMOS output which is used for FastLock or a general purpose output. Internally regulated voltage for PLL charge pump. Not intended to drive an external load. Connect to ground with a capacitor. Power Supply for the PLL. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. Internally regulated voltage for RF digital circuitry. Not intended to drive an external load. Connect to ground with a capacitor. Multiplexed CMOS output. Typically used to monitor PLL lock condition. Oscillator input. Oscillator complimentary input. When a single ended source is used, then a bypass capacitor should be placed as close as possible to this pin and be connected to ground. This pin is for test purposes and should be grounded for normal operation. Ground Internally regulated voltage for LDO digital circuitry. 11 CE I 14, 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 31 32 33 34 36 NC VccVCO VregVCO VrefVCO GND GND Fout VccBUF Vtune CPout FLout VregPLL1 VccPLL VregPLL2 Ftest/LD OSCin OSCin* Test GND VregDIG O I O O O I I O - www.national.com 4 LMX2531 Connection Diagram 20101111 Pin(s) VccDIG VccVCO VccBUF VccPLL VregDIG VrefVCO Application Information These pins are inputs to voltage regulators. Because the LMX2531 contains internal regulators, the power supply noise rejection is very good and capacitors at this pin are not critical. An RC filter can be used to reduce supply noise, but if the capacitor is too large and is placed too close to these pins, they can sometimes cause phase noise degradation in the 100 - 300 kHz offset range. Recommended values are from open to 1 μF. The series resistors serve to filter power supply noise and isolate these pins from large capacitances. There is not really any reason to use any other values than the recommended value of 10 nF If the VrefVCO capacitor is changed, it is recommended to keep this capacitor between 1/100 and 1/1000 of the value of the VregVCO capacitor. Because this pin is the output of a regulator, there are stability concerns if there is not sufficient series resistance. For ceramic capacitors, the ESR (Equivalent Series Resistance) is too low, and it is recommended that a series resistance of VregVCO 1 - 3.3Ω is necessary. If there is insufficient ESR, then there may be degradation in the phase noise, especially in the 100 - 300 kHz offset. Recommended values are from 1 μF to 10 μF. The choice of the capacitor value at this pin involves a trade-off between integer spurs and phase noise in the 100 - 300 VregPLL1 kHz offset range. Using a series resistor of about 220 mΩ in series with a capacitance that has an impedance of about 150 mΩ at the phase detector frequency seems to give an optimal trade-off. For instance, if the phase detector frequency is VregPLL2 2.5 MHz, then make this series capacitor 470 nF. If the phase detector frequency is 10 MHz, make this capacitance about 100 nF. CLK DATA LE Since the maximum voltage on these pins is less than the minimum Vcc voltage, level shifting may be required if the output voltage of the microcontroller is too high. This can be accomplished with a resistive divider. 5 www.national.com LMX2531 Pin(s) CE Ftest/LD Fout CPout Vtune R2pLF OSCin OSCin* Application Information As with the CLK, DATA, and LE pins, level shifting may be required if the output voltage of the microcontroller is too high. A resistive divider or a series diode are two ways to accomplish this. The diode has the advantage that no current flows through it when the chip is powered down. It is an option to use the lock detect information from this pin. This is the high frequency output. This needs to be AC coupled, and matching may also be required. The value of the DC blocking capacitor may be changed, depending on the output frequency. In most cases, it is sufficient to short these together, although there always the option of adding additional poles. C1_LF, C2_LF, and R2_LF are used in conjunction with the internal loop filter to make a fourth order loop filter. This is the fastlock resistor, which can be useful in many cases, since the spurs are often better with low charge pump currents, and the internal loop filter can be adjusted during fastlock. This is the reference oscillator input pin. It needs to be AC coupled. If the device is being driven single-ended, this pin needs to be shunted to ground with a capacitor. www.national.com 6 LMX2531 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Symbol VCC (VccDIG, VccVCO, VccBUF, VccPLL) All other pins (Except Ground) TSTG TL Ratings -0.3 to 3.5 V -0.3 to 3.0 -65 to 150 + 260 °C °C Units Power Supply Voltage Storage Temperature Range Lead Temperature (solder 4 sec.) Recommended Operating Conditions Parameter Power Supply Voltage (VccDig, VccVCO, VccBUF) Serial Interface and Power Control Voltage Ambient Temperature (Note 5) Symbol Vcc Vi TA Min 2.8 0 -40 Typ 3.0 Max 3.2 2.75 +85 Units V V °C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only to the test conditions listed. 7 www.national.com LMX2531 Electrical Characteristics Symbol Parameter (VCC = 3.0 V, -40°C ≤ TA ≤ 85 °C; except as specified.) Conditions Current Consumption LMX2531LQ2265E /2570E Divider Disabled LMX2531LQ2820E /3010E All Other Options LMX2531LQ2265E /2570E Divider Enabled LMX2531LQ2820E /3010E All Other Options 38 38 34 41 44 37 7 100 -100 5 0.5 PLL 80 2.0 32 ICP = 0 90 180 360 1440 2 2 10 8 ICP = 1 ICP = 3 ICP = 15 0.4 V < VCPout < 2.0 V VCPout = 1.2 V TA = 25°C 0.4 V < VCPout < 2.0 V TA = 25°C VCPout = 1.2 V ICP = 1X Charge Pump Gain ICP = 16X Charge Pump Gain ICP = 1X Charge Pump Gain ICP = 16X Charge Pump Gain 44 46 41 49 52 46 µA µA µA MHz Vpp MHz µA µA µA µA nA % mA Min Typ Max Units ICC Power Supply Current Power Supply Current ICCPD IIHOSC IILOSC fOSCin vOSCin fPD Power Down Current Oscillator Input High Current Oscillator Input Low Current Frequency Range Oscillator Sensitivity Phase Detector Frequency Charge Pump Output Current Magnitude CP TRI-STATE Current Charge Pump Sink vs. Source Mismatch Charge Pump Current vs. CP Voltage Variation CP Current vs. Temperature Variation Normalized PLL 1/f Noise LNPLL_flicker(10 kHz) (Note 3) Normalized PLL Noise Floor LNPLL_flat (Note 4) CE = 0 V, Part Initialized Oscillator VIH = 2.75 V VIL = 0 (Note 2) ICPout ICPoutTRI ICPoutMM ICPoutV ICPoutT 4 % 8 -94 -104 -202 -212 % dBc/Hz LN(f) dBc/Hz www.national.com 8 LMX2531 Symbol Parameter Conditions VCO Frequencies LMX2531LQ1146E LMX2531LQ1226E LMX2531LQ1312E LMX2531LQ1415E LMX2531LQ1515E LMX2531LQ1570E Min 1106 1184 1268 1360 1450 1530 1590 1662 1760 1726 1834 1904 2178 2336 2710 2910 Typ Max 1184 1268 1360 1470 1580 1636 1700 1770 1866 1840 2028 2274 2400 2790 2925 3132 Units fFout Operating Frequency Range (All options have a frequency divider, this applies before the divider. The frequency after the divider is half of what is shown) LMX2531LQ1650E LMX2531LQ1700E LMX2531LQ1742 LMX2531LQ1778E LMX2531LQ1910E LMX2531LQ2080E LMX2531LQ2265E LMX2531LQ2570E LMX2531LQ2820E LMX2531LQ3010E MHz 9 www.national.com LMX2531 Symbol Parameter Conditions Other VCO Specifications LMX2531LQ1742 LMX2531LQ1570E/1650E/1146E/1226/1312E/1415E/ 1515E LMX2531LQ1700E/1778E/1910E/2080E/2265E/ 2570E/2820E/3010E LMX2531LQ1146E LMX2531LQ1226E LMX2531LQ1312E LMX2531LQ1415E LMX2531LQ1515E LMX2531LQ1570E LMX2531LQ1650E Divider Disabled LMX2531LQ1700E LMX2531LQ1742 LMX2531LQ1778E LMX2531LQ1910E LMX2531LQ2080E LMX2531LQ2265E LMX2531LQ2570E LMX2531LQ2820E LMX2531LQ3010E LMX2531LQ1146E LMX2531LQ1226E LMX2531LQ1312E LMX2531LQ1415E LMX2531LQ1515E LMX2531LQ1570E LMX2531LQ1650E Divider Enabled LMX2531LQ1700E LMX2531LQ1742 LMX2531LQ1778E LMX2531LQ1910E LMX2531LQ2080E LMX2531LQ2265E LMX2531LQ2570E LMX2531LQ2820E LMX2531LQ3010E Min 65 90 125 1 1 1 0 -1 2 2 1 1 1 1 1 1 0 -0.5 -1.5 -1 -1 -1 -2 -2 1 1 1 1 1 1 0 0 -1 -2.5 -3 Typ Max Units ΔTCL Maximum Allowable Temperature Drift for Continuous Lock (Note 5) °C 4.0 3.5 3.5 3.0 2.5 4.5 4.5 3.5 3.5 3.5 3.5 3.5 3.5 3.0 2.5 1.5 2.0 2.0 1.5 0.5 0.5 3.0 3.0 3.0 3.0 3.0 3.0 2.5 2.5 1.5 0 -0.5 7 7 7 6 5 8 8 7 7 7 7 7 7 6 5.5 4.5 5 5 4 3 3 6 6 6 6 6 6 5 5 4 2.5 2 dBm dBm pFout Output Power to a 50 Ω Load (Applies across entire tuning range.) www.national.com 10 LMX2531 Symbol Parameter Conditions LMX2531LQ1146E LMX2531LQ1226E LMX2531LQ1312E LMX2531LQ1415E Min Typ 2.5 -5.5 3-6 3-6 3.5 -6.5 4-7 4-7 4-7 6-10 4-7 6-10 8-14 9-20 10-16 10-23 12-28 13-29 -35 Max Units KVtune Fine Tuning Sensitivity (When a range is displayed in the typical column, indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range.) LMX2531LQ1515E LMX2531LQ1570E LMX2531LQ1650E LMX2531LQ1700E LMX2531LQ1742 LMX2531LQ1778E LMX2531LQ1910E LMX2531LQ2080E LMX2531LQ2265E LMX2531LQ2570E LMX2531LQ2820E LMX2531LQ3010E LMX2531LQ1146E /1226E/1312E /1415E/1515E LMX2531LQ2820E /3010E All Other Options LMX2531LQ1146E /1226E/1312E /1415E/1515E LMX2531LQ2820E /3010E All Other Options LMX2531LQ1146E /1226E/1312E LMX2531LQ2820E /3010E All Other Options LMX2531LQ1146E /1226E/1312E /1570E/1650E LMX2531LQ2820E /3010E All Other Options MHz/V -25 Divider Disabled 2nd Harmonic 50 Ω Load Divider Enabled HSFout Harmonic Suppression (Applies Across Entire Tuning Range) Divider Disabled 3rd Harmonic 50 Ω Load Divider Enabled -40 -30 -30 -25 -20 -30 -20 -35 -50 -40 -20 -15 -15 -30 dBc -35 -15 -40 -25 300 -20 -20 kHz/V ±600 kHz Ω PUSHFout PULLFout ZFout Frequency Pushing Frequency Pulling Output Impedance Creg = 0.1uF, VDD ± 100mV, Open Loop VSWR = 2:1, Open Loop 50 11 www.national.com LMX2531 Symbol Parameter Conditions VCO Phase Noise (Note 6) 10 kHz Offset fFout = 1146 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 573 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1226 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 613 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1314 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 657 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1415 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 707.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1515 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 757.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1583 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 791.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset Min Typ -96 -121 -142 -156 -101 -126 -147 -156 -95 -121 -142 -155 -101 -126 -147 -155 -95 -121 -140 -154 -101 -126 -146 -154 -95 -121 -141 -154 -100 -126 -146 -154 -96 -122 -142 -153 -99 -125 -145 -154 -93 -118 -140 -154 -99 -122 -144 -155 Max Units L(f)Fout Phase Noise (LMX2531LQ1146E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ1226E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ1312E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ1415E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ1515E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ1570E) dBc/Hz www.national.com 12 LMX2531 Symbol Parameter fFout = 1645 MHz DIV2 = 0 Conditions 10 kHz Offset 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 822.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1716 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 858 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout= 1813 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 906.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1783 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 891.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1931 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 965.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 2089 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1044.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset Min Typ -93 -118 -140 -154 -99 -122 -144 -155 -92 -117 -139 -153 -98 -122 -144 -154 -92 -117 -140 -152 -99 -122 -143 -152 -92 -117 -139 -152 -97 -122 -144 -154 -89 -115 -138 -151 -95 -121 -143 -155 -87 -113 -136 -150 -93 -119 -142 -154 Max Units L(f)Fout Phase Noise (LMX2531LQ1650E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ1700E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ1742) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ1778E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ1910E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ2080E) dBc/Hz 13 www.national.com LMX2531 Symbol Parameter fFout = 2264 MHz DIV2 = 0 Conditions 10 kHz Offset 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1132 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 2563 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1281.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 2818 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1409 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 3021 MHz DIV2 = 0 100 kHz Offset 1 MHz Offset 5 MHz Offset 10 kHz Offset fFout = 1510.5 MHz DIV2 = 1 100 kHz Offset 1 MHz Offset 5 MHz Offset Min Typ -88 -113 -136 -150 -94 -118 -141 -154 -86 -112 -135 -149 -91 -117 -139 -152 -84 -111 -133 -148 -90 -117 -138 -150 -83 -110 -132 -147 -88 -116 -137 -148 Max Units L(f)Fout Phase Noise (LMX2531LQ2265E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ2570E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ2820E) dBc/Hz L(f)Fout Phase Noise (LMX2531LQ3010E) dBc/Hz www.national.com 14 LMX2531 Symbol VIH VIL IIH IIL VOH VOL tCS tCH tCWH tCWL tES tCES tEWH Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Output Voltage Low-Level Output Voltage Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Enable Set Up Time Enable to Clock Set Up Time Enable Pulse Width High Conditions Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout) Min 1.6 Typ Max 2.75 0.4 3.0 3.0 Units V V µA µA V V ns ns ns ns ns ns ns VIH = 1.75 VIL = 0 V IOH = 500 µA IOL = -500 µA MICROWIRE Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing -3.0 -3.0 2.0 2.65 0.0 25 20 25 25 25 25 25 0.4 Note 2: There are program bits that need to be set based on the OSCin frequency. Refer to the following sections: 2.7.8 XTLSEL[2:0] -- Crystal Select, 2.8.1 XTLDIV[1:0] -- Division Ratio for the Crystal Frequency, 2.8.2 XTLMAN[11:0] -- Manual Crystal Mode, 2.9.1 XTLMAN2 -- MANUAL CRYSTAL MODE SECOND ADJUSTMENT, and2.9.2 LOCKMODE -- FREQUENCY CALIBRATION MODE. Not all bit settings can be used for all frequency choices of OSCin. For instance, automatic modes described in 2.7.8 XTLSEL[2:0] -- Crystal Select do not work below 8 MHz. Note 3: One of the specifications for modeling PLL in-band phase noise is the PLL 1/f noise normalized to 1 GHz carrier frequency and 10 kHz offset, LPLL_flicker (10 kHz). From this normalized index of PLL 1/f noise, the PLL 1/f noise can be calculated for any carrier and offset frequency as: LNPLL_flicker(f) = LPLL_flicker(10 kHz) - 10·log(10 kHz / f) + 20·log( Fout / 1 GHz ). Flicker noise can dominate at low offsets from the carrier and has a 10 dB/decade slope and improves with higher charge pump currents and at higher offset frequencies . To accurately measure LPLL_flicker(10 kHz) it is important to use a high phase detector frequency and a clean reference to make it such that this measurement is on the 10 dB/decade slope close to the carrier. LPLL_flicker(f) can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker (f) and LPLL_flat. In other words,LPLL(f) = 10·log(10(LNPLL_flat / 10 ) + 10(LNPLL_flicker (f) / 10 ) Note 4: A specification used for modeling PLL in-band phase noise floor is the Normalized PLL noise floor, LNPLL_flat, and is defined as: LNPLL_flat = L(f) – 20·log(N) – 10·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector frequency of the synthesizer. LPLL_flat contributes to the total noise, L(f). To measure LPLL_flat the offset frequency must be chosen sufficiently smaller then the loop bandwidth of the PLL, and yet large enough to avoid a substantial noise contribution from the reference and PLL flicker noise. LPLL_flat can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat. In other words,LPLL(f) = 10·log(10(LNPLL_flat / 10 ) + 10(LNPLL_flicker (f) / 10 ) Note 5: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of -40°C ≤TA≤ 85°C without violating specifications. Note 6: The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The maximum limits apply only at center frequency and over temperature, assuming that the part is reloaded at each test frequency. Over frequency, the phase noise can vary 1 to 2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies 1 to 2 dB, assuming the part is reloaded. 15 www.national.com LMX2531 Serial Data Timing Diagram 20101103 The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift registers to an actual counter. A slew rate of at least 30 V/μs is recommended for these signals. After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state. Although it is strongly recommended to keep LE low after programming, LE can be kept high if bit R5[23] is changed to 0 (from its default value of 1). If this bit is changed, then the operation of the part is not guaranteed because it is not tested under these conditions. If the CLK and DATA lines are toggled while the in VCO is in lock, as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming. www.national.com 16 LMX2531 Typical Performance Characteristics OSCin Input Impedance 20101106 Frequency (MHz) 1 5 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 Powered Up (kΩ) Real 4.98 3.44 1.42 0.52 0.29 0.18 0.13 0.10 0.09 0.07 0.07 0.06 0.06 0.05 0.05 0.04 0.04 Imaginary -2.70 -3.04 -2.67 -1.63 -1.22 -0.92 -0.74 -0.63 -0.56 -0.50 -0.46 -0.41 -0.37 -0.34 -0.32 -0.29 -0.27 Magnitude 5.66 4.63 3.02 1.71 1.25 0.94 0.75 0.64 0.56 0.50 0.46 0.42 0.38 0.34 0.32 0.30 0.28 Real 6.77 5.73 1.72 0.53 0.26 0.17 0.14 0.10 0.09 0.08 0.07 0.07 0.07 0.06 0.06 0.05 0.05 Powered Down (kΩ) Imaginary -8.14 -6.72 -5.24 -2.94 -2.12 -1.58 -1.24 -1.06 -0.95 -0.86 -0.80 -0.72 -0.65 -0.59 -0.55 -0.50 -0.47 Magnitude 10.59 9.03 5.51 2.98 2.14 1.59 1.25 1.06 0.95 0.87 0.80 0.72 0.65 0.59 0.55 0.50 0.47 17 www.national.com LMX2531 1.0 Functional Description The LMX2531 is a low power, high performance frequency synthesizer system which includes the PLL, VCO, and partially integrated loop filter. The following sections give a discussion of the various blocks of this device. 1.1 REFERENCE OSCILLATOR INPUT Because the VCO frequency calibration algorithm is based on clocks from the OSCin pin, there are certain bits that need to be set depending on the OSCin frequency. XTLSEL (R6[22:20]) and XTLDIV (R7[9:8]) are both need to be set based on the OSCin frequency, fOSCin. For some options and for low OSCin frequencies, the XTLMAN (R7[21:10]) and XTLMAN2 (R8[4]) words need to be set to the correct value. 1.2 R DIVIDER The R divider divides the OSCin frequency down to the phase detector frequency. The R divider value, R, is restricted to the values of 1, 2, 4, 8, 16, and 32. If R is greater than 8, then this also puts restrictions on the fractional denominator, FDEN, than can be used. This is discussed in greater depth in later sections. 1.3 PHASE DETECTOR AND CHARGE PUMP The phase detector compares the outputs of the R and N dividers and puts out a correction current corresponding to the phase error. The phase detector frequency, fPD, can be calculated as follows: fPD = fOSCin / R Choosing R = 1 yields the highest possible phase detector frequency and is optimum for phase noise, although there are restrictions on the maximum phase detector frequency which could force the R value to be larger. The far out PLL noise improves 3 dB for every doubling of the phase detector frequency, but at lower offsets, this effect is much less due to the PLL 1/f noise. Aside from getting the best PLL phase noise, higher phase detector frequencies also make it easier to filter the noise that the delta-sigma modulator produces, which peaks at an offset frequency of fPD/2 from the carrier. The LMX2531 also has 16 levels of charge pump currents and a highly flexible fractional modulus. Increasing the charge pump current improves the phase noise about 3 dB per doubling of the charge pump current, although there are small diminishing returns as the charge pump current increases. From a loop filter design and PLL phase noise perspective, one might think to always design with the highest possible phase detector frequency and charge pump current. However, if one considers the worst case fractional spurs that occur at an output frequency equal to 1 channel spacing away from a multiple of the fOSCin, then this gives reason to reconsider. If the phase detector frequency or charge pump currents are too high, then these spurs could be degraded, and the loop filter may not be able to filter these spurs as well as theoretically predicted. For optimal spur performance, a phase detector frequency around 2.5 MHz and a charge pump current of 1X are recommended. 1.4 N DIVIDER AND FRACTIONAL CIRCUITRY The N divider in the LMX2531 includes fractional compensation and can achieve any fractional denominator between 1 and 4,194,303. The integer portion, NInteger, is the whole part of the N divider value and the fractional portion, NFractional, is the remaining fraction. So in general, the total N divider value, N, is determined by: N = NInteger + NFractional For example, if the phase detector frequency (fPD) was 10 MHz and the VCO frequency (fVCO) was 1736.1 MHz, then N would be 173.61. This would imply that NInteger is 173 and NFractional is 61/100. NInteger has some minimum value restrictions that are arise due to the architecture of this divider. The first restrictions arise because the N divider value is actually formed by a quadruple modulus 16/17/20/21 prescaler, which creates minimum divide values. NInteger is further restricted because the LMX2531 due to the fractional engine of the N divider. The fractional word, NFractional , is a fraction formed with the NUM and DEN words. In the example used here with the fraction of 61/100, NUM = 61 and DEN = 100. The fractional denominator value, DEN, can be set from 2 to 4,194,303. The case of DEN=0 makes no sense, since this would cause an infinite N value; the case of 1 makes no sense either (but could be done), because integer mode should be used in these applications. All other values in this range, like 10, 32, 42, 734, or 4,000,000 are all valid. Once the fractional denominator, DEN, is determined, the fractional numerator, NUM, is intended to be varied from 0 to DEN-1. In general, the fractional denominator, DEN, can be calculated by dividing the phase detector frequency by the greatest common divisor (GCD) of the channel spacing (fCH) and the phase detector frequency. If the channel spacing is not obvious, then it can be calculated as the greatest common divisor of all the desired VCO frequencies. FDEN = k · fPD / GCD(fPD , fCH) k = 1, 2, 3 .. For example, consider the case of a 10 MHz phase detector frequency and a 200 kHz channel spacing at the VCO output. The greatest common divisor of 10 MHz and 200 kHz is just 200 kHz. If one takes 10 MHz divided by 200 kHz, the result is 50. So a fractional denominator of 50, or any multiple of 50 would work in this example. Now consider a case with a 10 MHz phase detector frequency and a 30 kHz channel spacing. The greatest common divisor of 10 MHz and 30 kHz is 10 kHz. The fractional denominator therefore must be a multiple 1000, since this is 10 MHz divided by 10 kHz. For a final example, consider an application with a fixed output frequency of 2110.8 MHz and a OSCin frequency of 19.68 MHz. If the phase detector frequency is chosen to be 19.68 MHz, then the channel spacing can be calculated as the greatest common multiple of 19.68 MHz and 2110.8 MHz, which is 240 kHz. The fractional denominator is therefore a multiple of 41, which is 19.68 MHz / 240 kHz. Refer to application note 1865 for more details on frequency planning. To achieve a fractional N value, an integer N divider is modulated between different values. This gives rise to three main degrees of freedom with the LMX2531 delta sigma engine including the modulator order, dithering, and the way that the fractional portion is expressed. The first degree of freedom is the modulator order, which gives the user the ability to optimize for a particular application. The modulator order can be selected as zero (integer mode), two, three, or four. One simple technique to better understand the impact of the delta sigma fractional engine on noise and spurs is to tune the VCO to an integer channel and observe the impact of changing the modulator order from integer mode to a higher order. The higher the fractional modulator order is, the lower the spurs theoretically are. However, this is not always the case, and the higher order fractional modulator can sometimes give rise to additional spurious tones, but this is dependent on the application. The second degree of freedom with the LMX2531 www.national.com 18 LMX2531 delta sigma engine is dithering. Dithering is often effective in reducing these additional spurious tones, but can add phase noise in some situations. The third degree of freedom is the way that the fraction is expressed. For example, 1/10 can be expressed as 100000/1000000. Expressing the fraction in higher order terms sometimes improves the performance, particularly when dithering is used. In conclusion, there are some guidelines to getting the optimum choice of settings, but these optimum settings are application specific. Refer to application note 1879 for a much more detailed discussion on fractional PLLs and fractional spurs.. 1.5 PARTIALLY INTEGRATED LOOP FILTER The LMX2531 integrates the third pole (formed by R3 and C3) and fourth pole (formed by R4 and C4) of the loop filter. The values for C3, C4, R3, and R4 can also be programmed independently through the MICROWIRE interface and also R3 and R4 can be changed during FastLock™, for minimum lock time. The larger the values of these components, the stronger the attenuation of the internal loop filter. The maximum attenuation can be achieved by setting R3=R4=40 kΩ and C3=C4=100 pF while the minimum attenuation is achieved by disabling the loop filter by setting EN_LPFLTR (R6[15]) to zero. Note that when the internal loop filter is disabled, there is still a small amount of input capacitance on front of the VCO on the order of 200 pF. Since that the internal loop filter is on-chip, it is more effective at reducing certain spurs than the external loop filter. The higher order poles formed by the integrated loop filter are also helpful for attenuating noise due to the delta-sigma modulator. This noise produced by the delta-sigma modulator is outside the loop bandwidth and dependent on the modulator order. Although setting the filtering for maximum attenuation gives the best filtering, it puts increased restrictions on how wide the loop bandwidth of the system can be, which corresponds to the case where the shunt loop filter capacitor, C1, is zero. Increasing the charge pump current and/or the phase detector frequency increases the maximum attainable loop bandwidth when designing with the integrated filter. It is recommended to set the internal loop filter as high as possible without restricting the loop bandwidth of the system more than desired. If some setting between the minimum and maximum value is desired, it is preferable to reduce the resistor values before reducing the capacitor values since this will reduce the thermal noise contribution of the loop filter resistors. For design tools and more information on partially integrated loop filters, go to www.national.com/wireless. 1.6 LOW NOISE, FULLY INTEGRATED VCO The LMX2531 includes a fully integrated VCO, including the inductors. For optimum phase noise performance, this VCO has frequency and phase noise calibration algorithms. The frequency calibration algorithm is necessary because the VCO internally divides up the frequency range into several bands, in order to achieve a lower tuning gain, and therefore better phase noise performance. The frequency calibration routine is activated any time that the R0 register is programmed. There are several bits including LOCKMODE and XTLSEL that need to be set properly for this calibration to be performed in a reliable fashion. If the temperature shifts considerably and the R0 register is not programmed, then it can not drift more than the maximum allowable drift for continuous lock, ΔTCL, or else the VCO is not guaranteed to stay in lock. The phase noise calibration algorithm is necessary in order to achieve the lowest possible phase noise. Each version of the LMX2531, the VCO_ACI_SEL bit (R6[19:16]) needs to be set to the correct value to ensure the best possible phase noise. The gain of the VCO can change considerably over frequency. It is lowest at the minimum frequency and highest at the maximum frequency. This range is specified in the electrical specifications section of the datasheet. When designing the loop filter, the following method is recommended to determine what VCO gain to design to. First, take the geometric mean of the minimum and maximum frequencies that are to be used. Then use a linear approximation to extrapolate the VCO gain. Suppose the application requires the LMX2531LQ2080E PLL to tune from 2100 to 2150 MHz. The geometric mean of these frequencies is sqrt(2100 × 2150) MHz = 2125 MHz. The VCO gain is specified as 9 MHz/V at 1904 MHz and 20 MHz/V at 2274 MHz. Over this range of 370 MHz, the VCO gain changes 11 MHz/V. So at 2125 MHz, the VCO gain would be approximately 9 + (2125-1904)* 11/370 = 15.6 MHz/V. Although the VCO gain can change from part to part, this variation is small compared to how much the VCO gain can change over frequency. The VCO frequency is related to the other frequencies and divider values as follows: fVCO = fPD × N = fOSCin × N / R 1.7 PROGRAMMABLE VCO DIVIDER All options of the LMX2531 offer the option of dividing the VCO output by two to get half of the VCO frequency at the Fout pin. The channel spacing at the Fout pin is also divided by two as well. Because this divide by two is outside feedback path between the VCO and the PLL, enabling does require one to change the N divider, R divider, or loop filter values. When this divider is enabled, there will be some far-out phase noise contribution to the VCO noise. Note that the R0 register should be reprogrammed the first time after the DIV2 bit is enabled or disabled for optimal phase noise performance. The frequency at the Fout pin is related to the VCO frequency and divider value, D, as follows: fFout = fVCO / D 19 www.national.com LMX2531 2.0 General Programming Information The LMX2531 is programmed using 11 24-bit registers used to control the LMX2531 operation. A 24-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a data field and an address field. The last 4 register bits, CTRL[3:0] form the address field, which is used to decode the internal register address. The remaining 20 bits form the data field DATA[19:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock (data is programmed MSB first). When LE goes high, data is transferred from the data field into the selected register bank. Although there are actually 14 registers in this part, only a portion of them should be programmed, since the state of the other hidden registers (R13, R11, and R10) are set during the initialization sequence. Although it is possible to program these hidden registers, as well as a lot of bits that are defined to either '1' or '0', the user should not experiment with these hidden registers and bits, since the parts are not tested under these conditions and doing so will most likely degrade performance. DATA[19:0] MSB D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C3 C2 C1 CONTROL[3:0] LSB C0 2.01 REGISTER LOCATION TRUTH TABLE C3 1 1 1 0 0 0 0 0 0 0 0 2.02 INITIALIZATION SEQUENCE The initial loading sequence from a cold start is described below. The registers must be programmed in order shown. There must be a minimum of 10 ms between the time when R5 is last loaded and R1 is loaded to ensure time for the LDOs to power up properly. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2 1 0 0 1 1 1 1 0 0 0 0 C1 0 0 0 1 1 0 0 1 1 0 0 C0 0 1 0 1 0 1 0 1 0 1 0 Data Address R12 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 REG. R5 INIT1 R5 INIT2 R5 R12 R9 R8 R7 R6 R4 R3 R2 R1 R0 DATA[19:0] 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 C3 C2 C1 C0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 Program R12 as shown in the complete register map. Program R9 as shown in the complete register map. See individual section for Register R8 programming information. Programming of this register is necessary under specific circumstances. See individual section for Register R7 programming information. See individual section for Register R6 programming information. See individual section for Register R4 programming information. Register R4 only needs to be programmed if FastLock is used. See individual section for Register R3 programming information. See individual section for Register R2 programming information. See individual section for Register R1 programming information. See individual section for Register R0 programming information. www.national.com 20 2.03 Complete Register Content Map 17 DATA[19:0] NUM [11:0] 0 0 R [5:0] 0 0 0 1 0 0 DEN [21:12] TOC [13:0] 0 0 1 1 0 0 0 N [10:8] DEN [11:0] FoLD [3:0] NUM [21:12] C3 C2 C1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C0 0 1 0 1 0 This table shows all the programmable bits for the LMX2531. No programming order or initialization sequence is implied by this table, only the location of the programming information. RE GIS TER 23 22 21 20 19 18 R0 N [7:0] R1 0 0 1 ICP [3:0] R2 0 1 R3 DIV 2 FD M DITHER [1:0] ORDER [1:0] R4 0 0 ICPFL [3:0] EN_OSC REG_RST 0 EN_DIGLDO EN_PLLLDO2 R7 0 0 EN_LPFLTR R6 0 EN_PLLLDO1 EN_VCOLD EN_VCO EN_PLL R5 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 LMX2531 21 XTLSEL [2:0] VCO_ACI_SEL [3:0] R4_ADJ [1:0] R4_ADJ_ FL [1:0] R3_ADJ [1:0] XTLDIV [1:0] 0 0 0 R3_ADJ_ FL [1:0] C3_4_ADJ [2:0] 0 1 1 0 XTLMAN [11:0] 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 LOCK MODE 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 R8 0 0 0 0 0 0 0 0 0 0 1 0 XTL MA N2 0 0 1 1 1 0 0 1 0 0 0 0 1 0 R9 0 0 0 0 0 0 R12 0 0 0 0 0 0 www.national.com LMX2531 2.1 REGISTER R0 The action of programming the R0 register activates a frequency calibration routine for the VCO. This calibration is necessary to get the VCO to center the tuning voltage for optimal performance. If the temperature drifts considerably, then the PLL should stay in lock, provided that the temperature drift specification is not violated. 2.1.1 NUM[10:0] and NUM[21:12] -- Fractional Numerator The NUM word is split between the R0 register and R1 register. The Numerator bits determine the fractional numerator for the delta sigma PLL. This value can go from 0 to 4095 when the FDM bit (R3[22]) is 0 (the other bits in this register are ignored), or 0 to 4194303 when the FDM bit is 1. Fractional Numerator 0 ... 409503 4096 ... 4194303 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 NUM[21:12] 0 0 0 0 0 0 0 0 0 0 0 NUM[11:0] 0 0 0 0 0 0 0 Note that there are restrictions on the fractional numerator value depending on the R divider value if it is 16 or 32. 2.1.2 N[7:0] and N[10:8] The N counter is 11 bits. 8 of these bits are located in the R0 register, and the remaining 3 (MSB bits) are located in the R1 register. The LMX2531 consists of an A, B, and C counter, which work in conjunction with the 16/17/20/21 prescaler in order to form the final N counter value. N[10:8] N Value 40 MHz XTLMAN must be programmed if word XTLSEL (2.7.8) is set to manual crystal mode. In the table below, the proper value for XTLMAN is shown based on some common OSCin frequencies (fOSCin) and various LMX2531 options. For any OSCin frequency XTLMAN can be calculated as 16 × fOSCin / Kbit. fOSCin is expressed in MHz and Kbit values for the LMX2531 frequency options can be found in the Kbit table (below). XTLMAN Values for Common OSCin Frequencies Device LMX2531LQ1146E LMX2531LQ1226E LMX2531LQ1312E LMX2531LQ1415E LMX1531LQ1515E LMX2531LQ1570E LMX2531LQ1650E LMX2531LQ1700E LMX2531LQ1742 LMX2531LQ1778E LMX2531LQ1910E LMX2531LQ2265E LMX2531LQ2080E LMX2531LQ2570E LMX2531LQ2820E LMX2531LQ3010E fOSCin 5 MHz 53 53 47 47 40 38 38 35 32 31 27 20 18 13 11 10 10 MHz 107 107 94 94 80 76 76 70 64 62 53 40 36 27 23 20 20 MHz 213 213 188 188 160 152 152 139 128 123 107 80 71 53 46 40 30.72 MHz 327 327 289 289 246 234 234 214 197 189 164 123 109 82 70 61 61.44 MHz 655 655 578 578 492 468 468 427 393 378 328 246 218 164 140 123 76.8 MHz 819 819 722 722 614 585 585 534 492 473 410 307 273 205 178 154 Kbit Values for Various LMX2531 options Device LMX2531LQ1146E LMX2531LQ1226E LMX2531LQ1312E LMX2531LQ1415E LMX2531LQ1515E LMX2531LQ1570E LMX2531LQ1650E LMX2531LQ1700E LMX25311742 LMX2531LQ1778E LMX2531LQ1910E LMX2531LQ2265E 31 Kbit 1.5 1.5 1.7 1.7 2 2.1 2.1 2.3 2.5 2.6 3 4 www.national.com LMX2531 Kbit Values for Various LMX2531 options Device LMX2531LQ2080E LMX2531LQ2570E LMX2531LQ2820E LMX2531LQ3010E 2.9 REGISTER R8 2.9.1 XTLMAN2 -- MANUAL CRYSTAL MODE SECOND ADJUSTMENT This bit also adjusts the calibration timing for lock time. In the case that manual mode for XTLSEL is selected and the OSCin frequency is greater than 40 MHz, this bit should be enabled, otherwise it should be 0. 2.9.2 LOCKMODE -- FREQUENCY CALIBRATION MODE This bit controls the method for which the VCO frequency calibration is done. The two valid modes are linear mode and mixed mode. Linear mode works by searching through the VCO frequency bands in a consecutive manner. Mixed mode works by initially using a divide and conquer approach and then using a linear approach. For small frequency changes, linear mode is faster and for large frequency changes, mixed mode is faster. Linear mode can always be used, but there are restrictions for when Mixed Mode can be used. Kbit 4.5 6 7 8 LOCKMODE 0 1 2 3 2.10 REGISTER R9 Description Reserved Linear Mode Mixed Mode Reserved Conditions on Options Conditions on OSCin Frequency Never use this mode Works over all options and all valid OSCin Frequencies All but the following options LMX2531LQ1146E/1226E/1312E/1415E/1515E Never use this mode fOSCin ≥ 8 MHz All the bits in this register should be programmed as shown in the programming table. 2.11 REGISTER R12 Even though this register does not have user selectable bits, it still needs to be programmed. This register should be loaded as shown the Complete Register Content Map (section 2.03) . www.national.com 32 LMX2531 Physical Dimensions inches (millimeters) unless otherwise noted Leadless Leadframe Package (NS Package Number LQA036D), D Version (Bottom View) (LMX2531LQ1146E/1226E/1312E/1415E/1515E/2820E/3010E) Order Number LMX2531LQX for 2500 Unit Reel Order Number LMX2531LQ for 250 Unit Reel Leadless Leadframe Package (NS Package Number LQA036A), A Version (Bottom View) (All Other Options) Order Number LMX2531LQX for 2500 Unit Reel Order Number LMX2531LQ for 250 Unit Reel 33 www.national.com LMX2531 Part LMX2531LQ1146E LMX2531LQ1226E LMX2531LQ1312E LMX2531LQ1415E LMX2531LQ1515E LMX2531LQ1570E LMX2531LQ1650E LMX2531LQ1700E Marking 311146E 311226E 311312E 311415E 311515E 311570EB 311650EA 311778EB Package LQA036D LQA036D LQA036D LQA036D LQA036D LQA036A LQA036A LQA036A Part LMX2531LQ1742 LMX2531LQ1778E LMX2531LQ1910E LMX2531LQ2080E LMX2531LQ2265E LMX2531LQ2570E LMX2531LQ2820E LMX2531LQ3010E Marking 311742EA 311778EA 311910EB 312080EB 312265ED 312570EC 312820E 313010E Package LQA036A LQA036A LQA036A LQA036A LQA036A LQA036A LQA036D LQA036D www.national.com 34 LMX2531 Notes 35 www.national.com LMX2531 High Performance Frequency Synthesizer System with Integrated VCO Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero PowerWise® Design University Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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