LMX2531LQ1500E_08

LMX2531LQ1500E High Performance Frequency Synthesizer System with Integrated VCO September 4, 2008 LMX2531LQ1500E High Performance Frequency Synthesizer System with Integrated VCO General Description The LMX2531LQ1500E is a low power, high performance frequency synthesizer system which includes a fully integrated delta-sigma PLL and VCO with fully integrated tank circuit. The third and fourth poles are also integrated and also adjustable. Also included are integrated ultra-low noise and high precision LDOs for the PLL and VCO which give higher supply noise immunity and also more consistent performance. When combined with a high quality reference oscillator, the LMX2531LQ1500E generates very stable, low noise local oscillator signals for up and down conversion in wireless communication devices. The LMX2531LQ1500E is a monolithic integrated circuit, fabricated in an advanced BiCMOS process. There are several different versions of this product in order to accomdate different frequency bands. Device programming is facilitated using a three-wire MICROWIRE Interface that can operate down to 1.8 volts. Supply voltage range is 2.8 to 3.2 Volts. The LMX2531LQ1500E is available in a 36 pin 6x6x0.8 mm LeadFree Leadless Leadframe Package (LLP). Features ■ PLL Features — Fractional-N Delta Sigma Modulator Order programmable up to 4th order — FastLock/Cycle Slip Reduction with Timeout Counter — Partially integrated, adjustable Loop Filter — Very low phase noise and spurs ■ VCO Features — Integrated tank inductor — Low phase noise — 1499 - 1510 MHz Output Frequency — 749.5 - 755 MHz Output Frequency (Divide by 2 Mode) ■ Other Features — 2.8 V to 3.2 V Operation — Low Power-Down Current — 1.8V MICROWIRE Support — Package: 36 Lead LLP Target Applications ■ Data Converting Clocking Functional Block Diagram 20195001 © 2008 National Semiconductor Corporation 201950 www.national.com LMX2531LQ1500E Connection Diagram 20195002 Pin Descriptions Pin # 1 3 2,4,5,7, 12, 13, 29, 35 6 8 9 10 Pin Name VccDIG GND NC VregBUF DATA CLK LE I/O I I I Description Power Supply for digital LDO circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. Ground No Connect. Internally regulated voltage for the VCO buffer circuitry. Connect to ground with a capacitor. MICROWIRE serial data input. High impedance CMOS input. This pin must not exceed 2.75V. Data is clocked in MSB first. The last bits clocked in form the control or register select bits. MICROWIRE clock input. High impedance CMOS input. This pin must not exceed 2.75V. Data is clocked into the shift register on the rising edge. MICROWIRE Latch Enable input. High impedance CMOS input. This pin must not exceed 2.75V. Data stored in the shift register is loaded into the selected latch register when LE goes HIGH. Chip Enable Input. High impedance CMOS input. This pin must not exceed 2.75V. When CE is brought high the LMX2531LQ1500E is powered up corresponding to the internal power control bits. It is necessary to reprogram the R0 register to get the part to re-lock. No Connect. Do NOT ground. Power Supply for VCO regulator circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. Internally regulated voltage for VCO circuitry. Not intended to drive an external load. Connect to ground with a capacitor and some series resistance. 11 14, 15 16 17 CE NC VccVCO VregVCO I - www.national.com 2 LMX2531LQ1500E Pin # 18 19 20 21 22 23 24 25 26 27 28 30 31 32 33 34 36 Pin Name VrefVCO GND GND Fout VccBUF Vtune CPout FLout VregPLL1 VccPLL VregPLL2 Ftest/LD OSCin OSCin* Test GND VregDIG I/O O I O O O I I O - Description Internal reference voltage for VCO LDO. Not intended to drive an external load. Connect to ground with a capacitor. Ground for the VCO circuitry. Ground for the VCO Output Buffer circuitry. Buffered RF Output for the VCO. Power Supply for the VCO Buffer circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. Tuning voltage input for the VCO. For connection to the CPout Pin through an external passive loop filter. Charge pump output for PLL. For connection to Vtune through an external passive loop filter. An open drain NMOS output which is used for FastLock or a general purpose output. Internally regulated voltage for PLL charge pump. Not intended to drive an external load. Connect to ground with a capacitor. Power Supply for the PLL. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as close as possible to this pin and ground. Internally regulated voltage for RF digital circuitry. Not intended to drive an external load. Connect to ground with a capacitor. Multiplexed CMOS output. Typically used to monitor PLL lock condition. Oscillator input. Oscillator complimentary input. When a single ended source is used, then a bypass capacitor should be placed as close as possible to this pin and be connected to ground. This pin if for test purposes and should be grounded for normal operation. Ground Internally regulated voltage for LDO digital circuitry. 3 www.national.com LMX2531LQ1500E Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Symbol VCC (VccDIG, VccVCO, VccBUF, VccPLL) All other pins (Except Ground) TSTG TL Ratings -0.3 to 3.5 V -0.3 to 3.0 -65 to 150 + 260 °C °C Units Power Supply Voltage Storage Temperature Range Lead Temperature (solder 4 sec.) Recommended Operating Conditions Parameter Power Supply Voltage (VccDig, VccVCO, VccBUF) Serial Interface and Power Control Voltage Ambient Temperature (Note 3) Symbol Vcc Vi TA Min 2.8 0 -40 Typ 3.0 Max 3.2 2.75 +85 Units V V °C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only to the test conditions listed. www.national.com 4 LMX2531LQ1500E Electrical Characteristics Symbol Parameter (VCC = 3.0 V, -40°C ≤ TA ≤ 85 °C; fFout = 1500 MHz, except as specified.) Conditions Current Consumption Divider Disabled Divider Enabled CE = 0 V, Part Initialized Oscillator VIH = 2.75 V VIL = 0 -100 5 0.5 PLL 80 2.0 32 ICP = 0 90 180 360 1440 2 2 4 8 -202 dBc/Hz -212 10 8 ICP = 1 ICP = 3 ICP = 15 0.4 V < VCPout < 2.0 V VCPout = 1.2 V TA = 25°C 0.4 V < VCPout < 2.0 V TA = 25°C VCPout = 1.2 V ICP = 1X Charge Pump Gain 4 kHz Offset ICP = 16X Charge Pump Gain 4 kHz Offset Min Typ 34 37 7 100 Max 41 46 Units ICC ICCPD IIHOSC IILOSC fOSCin vOSCin fCOMP Power Supply Current Power Down Current Oscillator Input High Current Oscillator Input Low Current Frequency Range Oscillator Sensitivity Phase Detector Frequency Charge Pump Output Current Magnitude CP TRI-STATE Current Charge Pump Sink vs. Source Mismatch Charge Pump Current vs. CP Voltage Variation CP Current vs. Temperature Variation Normalized Phase Noise Contribution (Note 2) mA µA µA µA MHz Vpp MHz µA µA µA µA nA % % % ICPout ICPoutTRI ICPoutMM ICPoutV ICPoutT LN(f) 5 www.national.com LMX2531LQ1500E Symbol fFout Parameter Operating Frequency Range Conditions VCO Frequencies Min 1499 Typ Max 1510 Units MHz dBm dBm Other VCO Specifications pFout Output Power to a 50Ω/5pF Load (Applies across entire tuning range.) Fine Tuning Sensitivity (When a range is displayed in the typical column, indicates the lower sensitivity is typical at the lower end of the tuning range, and the higher tuning sensitivity is typical at the higher end of the tuning range.) Harmonic Suppression (Applies Across Entire Tuning Range) Frequency Pushing Frequency Pulling Output Impedance VCO Phase Noise (Note 4) 10 kHz Offset L(f)Fout Phase Noise fFout = 1500 MHz 100 kHz Offset 1 MHz Offset 5 MHz Offset -97 -120 -142 -155 dBc/Hz 2nd Harmonic, 50Ω / 5pF Load 3rd Harmonic, 50Ω / 5pF Load Divider Disabled Divider Enabled Divider Disabled Divider Enabled Divider Disabled Divider Enabled 1.0 1.0 3.5 3.0 7.0 6.0 KVtune 4-7 MHz/V -30 -20 -40 -25 300 -25 -15 -35 -20 kHz/V ±600 kHz Ω dBc HSFout PUSHFout PULLFout ZFout Creg = 0.1uF, VDD ± 100mV, Open Loop VSWR=2:1, Open Loop 50 www.national.com 6 LMX2531LQ1500E Symbol VIH VIL IIH IIL VOH VOL tCS tCH tCWH tCWL tES tCES tEWH Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Output Voltage Low-Level Output Voltage Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Clock to Enable Set Up Time Enable to Clock Set Up Time Enable Pulse Width High Conditions Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout) Min 1.6 Typ Max 2.75 0.4 3.0 3.0 Units V V µA µA V V ns ns ns ns ns ns ns VIH = 1.75 VIL = 0 V IOH = 500 µA IOL = -500 µA MICROWIRE Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing -3.0 -3.0 2.0 2.65 0.0 25 20 25 25 25 25 25 0.4 Note 2: Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(Fcomp) where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth and Fcomp is the comparison frequency of the synthesizer. The offset frequency, f, must be chosen sufficiently smaller then the loop bandwidth of the PLL, and large enough to avoid a substantial noise contribution from the reference. Note 3: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the part was initially programmed at, the temperature can never drift outside the frequency range of -40°C ≤TA≤ 85°C without violating specifications. Note 4: The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The maximum limits apply only at center frequency and over temperature, assuming that the part is reloaded at each test frequency. Over frequency, the phase noise can vary 1-2 dB, with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies 1-2 dB, assuming the part is reloaded. Serial Data Timing Diagram 20195003 The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift registers to an actual counter. A slew rate of at least 30 V/µs is recommended for these signals. After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state. If the CLK and DATA lines are toggled while the in VCO is in lock , as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming. 7 www.national.com LMX2531LQ1500E 1.0 Functional Description The LMX2531LQ1500E is a low power, high performance frequency synthesizer system which includes the PLL, VCO, and partially integrated loop filter. Section 2.0 on programming describes the bits mentioned in this section in more detail. 1.1 REFERENCE OSCILLATOR INPUT Because the VCO frequency calibration algorithm is based on clocks from the OSCin pin, there are certain bits that need to be set depending on the OSCin frequency. XTLSEL ( R6[22:20] ) and XTLDIV ( R7[9:8] ) are both need to be set based on the OSCin frequency. 1.2 R DIVIDER The R divider divides the OSCin frequency down to the phase detector frequency. The only valid R counter values are 1, 2, 4, 8, 16, and 32. The R divider also has an impact on the fractional modulus that can be used, if it is greater than 8. 1.3 N DIVIDER AND FRACTIONAL CIRCUITRY The N divider on the LMX2531LQ1500E is fractional and can achieve any fractional denominator between 1 and 4,194,303. The integer portion of the N counter value, NInteger, is determined by the value of the N word. Because there is a 16/17/20/21 prescaler, there are restrictions on how small the NInteger value can be. This is because this value is actually formed by several different prescalers in the quadruple modulus prescaler in order to achieve the desired value. The fractional word, NFractional , is a fraction formed with the NUM and DEN words. The fractional denominator value, DEN, can be set from 2 to 4,194,303. The case of DEN=0 makes no sense, since this would cause an infinite N value, and the case of 1 makes no sense (but could be done), because integer mode should be used in these applications. All other values in this range, like 10, 32,734, or 4,000,000 are all valid. Once the fractional denominator, DEN, is determined, the fractional numerator, NUM, is intended to be varied from 0 to DEN-1. Sometimes, expressing the same fraction, like 1/10, in terms of larger fractions, like 100/10000, sometimes yields better fractional spurs, but other times it does not. This can be impacted by the fractional modulator order and the dithering mode selected, as well as the loop bandwidth, and other application specific criteria. So in general, the total N counter value is determined by: N = NInteger + NFractional In order to calculate the minimum necessary fractional denominator, the R counter value needs to be chosen, so that the comparison frequency is known. The minimum necessary fractional denominator can be calculated by dividing the comparison frequency by the greatest common multiple of the comparison frequency and the OSCin frequency. For example, consider the case of a 10 MHz crystal and a 200 kHz channel spacing. If the R counter value is chosen to be 2, then the comparison frequency will be 5 MHz. The greatest common multiple of 200 kHz and 5 MHz is 200 kHz. If one takes 5 MHz divided by 200 kHz, this is 25. So a fractional denominator of 25, or any multiple of 25 would work in this situation. Now consider a second example where the channel spacing is changed to 30 kHz. If it is again assumed that the comparison frequency is 5 MHz, then the greatest common multiple of 30 kHz and 5 MHz is 10 kHz. 5 MHz divided by 10 kHz is 500. In this situation, a fractional denominator of 500, or any multiple of 500 would suffice. For a final example, consider an application with a fixed output frequency of 2110.8 MHz and a crystal frequency of 19.68 MHz. If the R counter is chowww.national.com 8 sen to be 2, then the comparison frequency is 9.84 MHz. The greatest common multiple of 9.84 MHz and 2110.8 MHz is 240 kHz. 9.84 MHz / 240 kHz = 41. So the fractional denominator could be 41, or any multiple of 41. For this last example value, the entire N counter value would be 214 + 21/41. The fractional value is achieved with a delta sigma architecture. In this architecture, an integer N counter is modulated between different values in order to achieve a fractional value. On this part, the modulator order can be zero (integer mode), two, three, or four. The higher the fractional modulator order is, the lower the spurs theoretically are. However, this is not always the case, and the higher order fractional modulator can sometimes give rise to additional spurious tones, but this is dependent on the application. This is why it is an advantage to have the modulator order selectable. Dithering also has an impact on the fractional spurs, but a lesser one. 1.4 PHASE DETECTOR The phase detector compares the outputs of the R and N counters and puts out a correction current corresponding to the phase error. The choice of the phase detector frequency does have an impact on performance. When determining which phase detector frequency to use, the restrictions on the R counter values must be taken into consideration. 1.5 PARTIALLY INTEGRATED LOOP FILTER The LMX2531LQ1500E integrates the third pole (formed by R3 and C3) and fourth pole (formed by R4 and C4) of the loop filter. This loop filter can be enabled or bypassed using the EN_LPFLTR ( R6[15] ). The values for C3, C4, R3, and R4 can also be programmed independently through the MICROWIRE interface . Also, the values for R3 and R4 can be changed during FastLock, for minimum lock time. It is recommended that the integrated loop filter be set to the maximum possible attenuation (R3=R4=40kΩ, C3=C4=100pF), the internal loop filter is more effective at reducing certain spurs than the external loop filter. However, if the attenuation of the internal loop filter is too high, it limits the maximum attainable loop bandwidth that can be achieved, which corresponds to the case where the shunt loop filter capacitor, C1, is zero. Increasing the charge pump current and/or the comparison frequency increases the maximum attainable loop bandwidth when designing with the integrated filter. Furthermore, this often allows the loop filter to be better optimized and have stronger attenuation. If the charge pump current and comparison frequency are already as high as they go, and the maximum attainable loop bandwidth is still too low, the resistor and capacitor values can be decreased or the internal loop filter can even be bypassed. Note that when the internal loop filter is bypassed, there is still a small amount of input capacitance on front of the VCO on the order of 200 pF. For design tools and more information on partially integrated loop filters, go to wireless.national.com. 1.6 LOW NOISE, FULLY INTEGRATED VCO The LMX2531LQ1500E includes a fully integrated VCO, including the inductors. In order for optimum phase noise performance, this VCO has frequency and phase noise calibration algorithms. The frequency calibration algorithm is necessary because the VCO internally divides up the frequency range into several bands, in order to achieve a lower tuning gain, and therefore better phase noise performance. The frequency calibration routine is activated any time that the R0 register is programmed. If the temperature shifts considerably and the R0 register is not programmed, then it can not drift more than the maximum allowable drift for continuous lock, ΔTCL, or else the VCO is not guaranteed to stay in lock. LMX2531LQ1500E The phase noise calibration algorithm is necessary in order to achieve the lowest possible phase noise. The VCO_ACI_SEL bit ( R6[19:16] ) needs to be set to the correct value to ensure the best possible phase noise. The gain of the VCO can change considerably over frequency. It is lowest at the minimum frequency and highest at the maximum frequency. This range is specified in the datasheet. When designing the loop filter, the following method is recommended. First, take the geometric mean of the minimum and maximum frequencies that are to be used. Then use a linear approximation to extrapolate the VCO gain. 1.7 PROGRAMMABLE DIVIDE BY 2 All options of the LMX2531LQ1500E offer a divide by 2 option. This allows the user to get exactly half of the VCO frequency, by dividing the output of the VCO output by two. Because this divide by two is outside feedback path between the VCO and the PLL, the loop filter and counter values are set up for the VCO frequency before it is divide by two. Note that R0 register should be reprogrammed the first time after the DIV2 bit is enabled or disabled for optimal phase noise performance. 1.8 CHOOSING THE CHARGE PUMP CURRENT AND COMPARISON FREQUENCY The LMX2531LQ1500E has 16 levels of charge pump currents and a highly flexible fractional modulus. This gives the user many degrees of freedom. This section discusses some of the design considerations. From the perspective of the PLL noise, choosing the charge pump current and comparison frequency as high as possible are best for optimal phase noise performance. The far out PLL noise improves 3 dB for every doubling of the comparison frequency, but at lower offsets, this effect is much less due to the PLL 1/f noise. Increasing the charge pump current improves the phase noise about 3 dB per doubling of the charge pump current, although there are small diminishing returns as the charge pump current goes higher. From a loop filter design and PLL phase noise perspective, one might think to always design with the highest possible comparison frequency and charge pump current. However, if one considers the worst case fractional spurs that occur at an output frequency equal to 1 channel spacing away from a multiple of the OSCin frequency, then this gives reason to reconsider. If the comparison frequency or charge pump currents are too high, then these spurs could be degraded, and the loop filter may not be able to filter these spurs as well as theoretically predicted. For optimal spur performance, a comparison frequency in the ballpark of 2.5 MHz and a charge pump current of 1X are recommended. 9 www.national.com LMX2531LQ1500E 2.0 General Programming Information The LMX2531LQ1500E is programmed using 11 24-bit registers used to control the LMX2531LQ1500E operation. A 24-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a data field and an address field. The last 4 register bits, CTRL[3:0] form the address field, which is used to decode the internal register address. The remaining 20 bits form the data field DATA[19:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock (data is programmed MSB first). When LE goes high, data is transferred from the data field into the selected register bank. Although there are actually 14 registers in this part, only a portion of them should be programmed, since the state of the other hidden registers (R13, R11, and R10) are set during the initialization sequence. Although it is possible to program these hidden registers, as well as a lot of bits that are defined to either '1' or '0', the user should not experiment with these hidden registers and bits, since doing will most likely degrade performance. Furthermore, this would be inconsistent to how these parts are tested. DATA[19:0] MS B D1 9 D1 8 D1 7 D1 6 D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C3 C2 C1 CONTROL[3:0] LS B C0 2.01 Register Location Truth Table C3 1 1 1 0 0 0 0 0 0 0 0 C2 1 0 0 1 1 1 1 0 0 0 0 C1 0 0 0 1 1 0 0 1 1 0 0 C0 0 1 0 1 0 1 0 1 0 1 0 Data Address R12 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 www.national.com 10 LMX2531LQ1500E 2.02 Initialization Sequence The initial loading sequence from a cold start is described below. The registers must be program in order shown. REGISTE 23 R R5 INIT1 R5 INIT2 R5 R12 R9 R8 R7 R6 R4 R3 R2 R1 R0 1 1 1 0 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA[19:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 C3 C2 C1 C0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 0 1 0 1 0 See individual section for R9 programming information. See individual section for Register R8 programming information. Register R8 only needs to be programmed for a few options of the LMX2531LQ1500E and and only in the case that the OSCin frequency is greater than 40 MHz. See individual section for Register R7 programming information. See individual section for Register R6 programming information. See individual section for Register R4 programming information. Register R4 only needs to be programmed if FastLock is used. See individual section for Register R3 programming information. See individual section for Register R2 programming information. See individual section for Register R1 programming information. See individual section for Register R0 programming information. Note: There must be a minimum of 10 mS between the time when R5 is last loaded and when R1 is loaded to ensure time for the LDOs to power up properly. 11 www.national.com LMX2531LQ1500E 2.03 Complete Register Content Map R1 DEN [11:0] 0 0 0 FoLD [3:0] TOC [13:0] DEN [21:12] R [5:0] 0 0 1 0 0 1 R2 0 EN_OSC REG_RST EN_DIGLDO EN_PLLLDO2 R7 0 0 EN_LPFLTR R6 0 EN_PLLLDO1 EN_VCOLD EN_VCO EN_PLL R9 0 0 1 0 0 0 0 www.national.com This table shows all the programmable bits for the LMX2531LQ1500E. No programming order or initialization sequence is implied by this table, only the location of the programming information. 17 DATA[19:0] NUM [11:0] 0 0 0 0 N [10:8] NUM [21:12] C3 C2 C1 0 0 1 1 0 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C0 0 1 0 1 0 RE GIS TER 23 22 21 20 19 18 R0 N [7:0] ICP [3:0] 1 R3 DIV 2 FD M DITHER [1:0] ORDER [1:0] R4 0 0 ICPFL [3:0] R5 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 12 XTLSEL [2:0] VCO_ACI_SEL [3:0] R4_ADJ [1:0] R4_ADJ_ FL [1:0] R3_ADJ [1:0] XTLDIV [1:0] R3_ADJ_ FL [1:0] 0 C3_4_ADJ [2:0] 0 1 1 0 XTLMAN [11:0] 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 R8 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 0 XTL MA N2 0 0 1 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 R12 0 0 0 0 0 0 LMX2531LQ1500E 2.1 REGISTER R0 The action of programming the R0 register activates a frequency calibration routine for the VCO. This calibration is necessary to get the VCO to center the tuning voltage for optimal performance. If the temperature drifts considerably, then the PLL should stay in lock, provided that the temperature drift specification is not violated. 2.1.1 NUM[10:0] and NUM[21:12] -- Fractional Numerator The NUM word is split between the R0 register and R1 register. The Numerator bits determine the fractional numerator for the delta sigma PLL. This value can go from 0 to 4095 when the FDM bit ( R3[22] ) is 0 (the other bits in this register are ignored), or 0 to 4194303 when the FDM bit is 1. NUM[21:12] Fra ctio nal Nu mer ator 0 ... 409 503 409 6 ... 419 430 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM[11:0] Note that there are restrictions on the fractional numerator value depending on the R counter value if it is 16 or 32. 2.1.2 N[7:0] and N[10:8] The N counter is 11 bits. 8 of these bits are located in the R0 register, and the remaining 3 (MSB bits) are located in the R1 register. The LMX2531LQ1500E consists of an A, B, and C counter, which work in conjunction with the 16/17/20/21 prescaler in order to form the final N counter value. N[10:8] N Value 40 MHz 21 www.national.com LMX2531LQ1500E 2.9 REGISTER R8 2.9.1 XTLMAN2 -- MANUAL CRYSTAL MODE SECOND ADJUSTMENT Set all these bits to zero. 2.10 REGISTER R9 All the bits in this register should be programmed as shown in the programming table. 2.11 REGISTER R12 Even though this register does not have user selectable bits, it still needs to be programmed. This register should be loaded as shown in section 2.02 Complete Register Content Map. www.national.com 22 LMX2531LQ1500E Physical Dimensions inches (millimeters) unless otherwise noted Leadless Leadframe Package (Bottom View) Order Number LMX2531LQ1500EX for 2500 Unit Reel Order Number LMX2531LQ1500E for 250 Unit Reel NS Package Number LQA036AA Package Marking 311500EB 23 www.national.com LMX2531LQ1500E High Performance Frequency Synthesizer System with Integrated VCO Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock Conditioners Data Converters Displays Ethernet Interface LVDS Power Management Switching Regulators LDOs LED Lighting PowerWise Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/displays www.national.com/ethernet www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH Analog University App Notes Distributors Green Compliance Packaging Design Support www.national.com/webench www.national.com/AU www.national.com/appnotes www.national.com/contacts www.national.com/quality/green www.national.com/packaging www.national.com/quality www.national.com/refdesigns www.national.com/feedback Quality and Reliability Reference Designs Feedback THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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