LMX2541SQ2690E

LMX2541 Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO PRELIMINARY LMX2541 July 2, 2009 Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO General Description The LMX2541 is an ultra low noise frequency synthesizer which integrates a high performance delta-sigma fractional N PLL, a VCO with fully integrated tank circuit, and an optional frequency divider. The PLL offers an unprecedented normalized noise floor of -225 dBc/Hz and can be operated with up to 104 MHz of phase-detector rate (comparison frequency) in both integer and fractional modes. The PLL can also be configured to work with an external VCO. The LMX2541 integrates several low-noise, high precision LDOs and output driver matching network to provide higher supply noise immunity and more consistent performance, while reducing the number of external components. When combined with a high quality reference oscillator, the LMX2541 generates a very stable, ultra low noise signal. The LMX2541 is offered in a family of 6 devices with varying VCO frequency range from 1990 MHz up to 4 GHz. Using a flexible divider, the LMX2541 can generate frequencies as low as 31.6 MHz. The LMX2541 is a monolithic integrated circuit, fabricated in a proprietary BiCMOS process. Device programming is facilitated using a three-wire MICROWIRE interface that can operate down to 1.8 volts. Supply voltage ranges from 3.15 to 3.45 volts. The LMX2541 is available in a 36 pin 6x6x0.8 mm Lead-Free Leadless Leadframe Package (LLP). Device LMX2541SQ2060E LMX2541SQ2380E LMX2541SQ2690E LMX2541SQ3030E LMX2541SQ3320E LMX2541SQ3740E VCO Frequency 1990 - 2240 2200 - 2530 2490 - 2865 2810 - 3230 3130 - 3600 3480 - 4000 Features ■ Very Low RMS Noise and Spurs — -225 dBc/Hz Normalized PLL Phase Noise — Integrated RMS Noise (100 Hz - 20 MHz) ■ 2 mrad (100 Hz - 20 MHz) at 2.1 GHz ■ 3.5 mrad (100 Hz - 20 MHz) at 3.5 GHz Ultra Low-Noise Integrated VCO External VCO Option (Internal VCO Bypassed) VCO Frequency Divider 1 to 63 (all values) Programmable Output Power Up to 104 MHz Phase Detector Frequency Integrated Low-Noise LDOs Programmable Charge Pump Output Partially Integrated Loop Filter Digital Frequency Shift Keying (FSK) Modulation Pin Integrated Reference Crystal Oscillator Circuit Hardware and Software Power Down FastLock Mode with Cycle Slip Reduction Analog and Digital Lock Detect 1.6 V Logic Compatibility ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Target Applications ■ ■ ■ ■ Wireless Infrastructure (UMTS, LTE, WiMax) Broadband Wireless Wireless Meter Reading Test and Measurement System Diagram 30073322 © 2009 National Semiconductor Corporation 300733 www.national.com LMX2541 LMX2541 Frequency Chart Divide Value 1 2 3 4 5 6 7 8 … 63 2060E Start 1990.0 995.0 663.3 497.5 398.0 331.7 284.3 248.8 … 31.6 Stop 2240.0 1120.0 746.7 560.0 448.0 373.3 320.0 280.0 … 35.6 2380E Start 2200.0 1100.0 733.3 550.0 440.0 366.7 314.3 275.0 … 34.9 Stop 2530.0 1265.0 843.3 632.5 506.0 421.7 361.4 316.3 … 40.2 2690E Start 2490.0 1245.0 830.0 622.5 498.0 415.0 355.7 311.3 … 39.5 Stop 2865.0 1432.5 955.0 716.3 573.0 477.5 409.3 358.1 … 45.5 3030E Start 2810.0 1405.0 936.7 702.5 562.0 468.3 401.4 351.3 … 44.6 Stop 3230.0 1615.0 1076.7 807.5 646.0 538.3 461.4 403.8 … 51.3 3320E Start 3130.0 1565.0 1043.3 782.5 626.0 521.7 447.1 391.3 … 49.7 Stop 3600.0 1800.0 1200.0 900.0 720.0 600.0 514.3 450.0 … 57.1 3740E Start 3480.0 1740.0 1160.0 870.0 696.0 580.0 497.1 435.0 … 55.2 Stop 4000.0 2000.0 1333.3 1000.0 800.0 666.7 571.4 500.0 … 63.5 All devices have continuous frequency coverage below a divide value of 8 (7 for most devices) down to their minimum frequency achievable with divide by 63. The numbers in bold show the upper end of this minimum continuous frequency range. Below 570 MHz, all devices can be used down to their minimum frequency of Min (fVCO) / 63. www.national.com 2 LMX2541 Functional Block Diagram 30073301 Connection Diagram 36-Pin SQ Package (Top View) 30073302 3 www.national.com LMX2541 Pin Descriptions Pin # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name GND GND VregRFout VccRFout L1 Lmid L2 VccVCO VregVCO VrefVCO GND CE ExtVCOin VccPLL1 VccCP1 Vtune CPout FLout VccCP2 VccPLL2 Ftest/LD OSCin OSCin* VccOSCin RFoutEN VccFRAC VregFRAC GND VccDig VccBias Bypass VccDiv DATA Type GND GND LDO Output Supply (LDO Input) NC NC NC Supply (LDO Input) LDO Output LDO Bypass GND CMOS RF Input Supply Supply High-Z Input Output Output Supply Supply Output High-Z Input High-Z Input Supply Input Supply (LDO Input) LDO Output GND Supply Supply Bypass Supply High-Z Input Supply for digital circuitry, such the MICROWIRE. Supply for Bias circuitry that is for the whole chip. Put a cap to the VccBias pin. Supply for the output divider MICROWIRE serial data input. High impedance CMOS input. This pin must not exceed 3.45 V. MICROWIRE clock input. High impedance CMOS input. This pin is used for the digital FSK modulation feature. This pin must not exceed 3.45 V. MICROWIRE Latch Enable input. High impedance CMOS input. This pin must not exceed 3.45 V. No connect. RF output. Must be AC coupled if used. Chip Enable. The device needs to be programmed for this pin to properly power down the device. Optional input for use with an external VCO. This pin should be AC coupled if used or left open if not used. Power supply for PLL N counter. Power supply for PLL charge pump up current. Tuning voltage input to the VCO. Charge pump output. Fastlock output. Power supply for PLL charge pump down current. Power supply for PLL R Counter Software controllable multiplexed CMOS output. Can be used to monitor PLL lock condition. Oscillator input signal. If not being used with an external crystal, this input should be AC coupled. Complementary oscillator input signal. Can also be used with an external crystal. If not being used with an external crystal, this input should be AC coupled. Supply for the OSCin buffer. Software programmable output enable pin. Power Supply for the fractional circuitry. Regulated power supply used for the fractional delta-sigma circuitry. LDO Output for RF output buffer. Supply for the RF output buffer. Do not connect this pin. Do not connect this pin. Do not connect this pin. Supply for the VCO. LDO Output for RF output buffer. LDO Bypass The DAP pad must be grounded. Description 33 CLK High-Z Input 34 35 36 LE NC RFout High-Z Input NC RF Output www.national.com 4 LMX2541 Absolute Maximum Ratings (Notes 1, 2, 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Power Supply Voltage Input Voltage to pins other than Vcc Pins (Note 4) Storage Temperature Range Lead Temperature (solder 4 sec.) Symbol Vcc VIN TSTG TL Ratings -0.3 to 3.6 -0.3 to (Vcc+0.3) -65 to 150 + 260 Units V VIN °C °C Recommended Operating Conditions Parameter Power Supply Voltage (All Vcc Pins) Ambient Temperature Symbol Vcc TA Min 3.15 -40 Typ 3.3 Max 3.45 +85 Units V °C Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only to for the test conditions listed. Note 2: This Device is a high performance RF integrated circuit with an ESD rating < 2kV and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations. Note 3: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only. Functional operation of the device is only implied at these or any other conditions in excess of those given in the Note 4: Never to exceed 3.6 V. 5 www.national.com LMX2541 Electrical Characteristics at Vcc = 3.3 V, 25 C.) Symbol Parameter (3.15 V ≤ VCC ≤ 3.45 V, -40°C ≤ TA ≤ 85 °C; except as specified. Typical values are Conditions Current Consumption Default Power Mode (Note 5) VCO_DIV>1 VCO_DIV=1 Min Typ 170 130 72 84 100 Max 204 156 85 102 250 mA Units ICC IPLL IDIV ICCPD Entire ChipPower Supply Current with all blocks enabled Current for External VCO Mode (Note 6) Current for Divider Only Mode Power Down Current RFoutEN = LOW VCO_DIV >1 Default Power Mode CE = 0 V, Device Initialized mA mA µA Oscillator (Normal Mode Operation with XO=0) IIHOSC Oscillator Input High Current for OSCin and OSCin* in IILOSCin fOSCin dvOSCin vOSCin Oscillator Input Low Current for OSCin and OSCin* pins Frequency Range Slew Rate Oscillator Sensitivity VIH = 2.75 V VIL = 0 Limited to ½ · fPD when the Oscillator doubler is enabled. Single-Ended Mode Single-Ended Differential Oscillator (Crystal Mode with XO=1) fXTAL ESRXTAL PXTAL COSCin fPD Crystal Frequency Range Crystal Equivalent Series Resistance Power Dissipation in Crystal Input Capacitance of OSCin PLL Phase Detector Frequency CPG = 1X ICPout Charge Pump Output Current Magnitude CPG = 2X CPG = 3X ... CPG=32X ICPoutTRI ICPoutMM CP TRI-STATE Current Charge Pump Sink vs. Source Mismatch Charge Pump Current vs. CP Voltage Variation CP Current vs. Temperature Variation Normalized PLL 1/f Noise LNPLL_flicker(10 kHz) Normalized PLL Noise Floor LNPLL_flat(1 Hz) PLL Input Frequency PLL Input Sensitivity 0.4 V < VCPout < Vcc - 0.4 VCPout = Vcc / 2 TA = 25°C 0.4 V < VCPout < Vcc - 0.4 TA = 25°C VCPout = Vcc / 2 CPG = 1X CPG = 32X CPG = 1X CPG = 32X RFout Buffer Enabled and VCO_DIV > 1 RFout Buffer Disabled and VCO_DIV = 1 fExtVCOin ≤ 4 GHz fExtVCOin > 4 GHz 400 400 -15 -5 100 200 300 ... 3200 1 3 5 10 nA % µA 104 MHz VIH = 2.75 V This a requirement for the crystal, not a characteristic of the LMX2541. This requirement is for the crystal, not a characteristic of the LMX2541. TBD 6 5 20 100 MHz Ω µW pF -100 5 150 0.2 0.4 2.0 3.1 900 300 µA µA MHz V/µs Vpp ICPoutV ICPoutT 4 % 8 -116 -124.5 -220.8 -225.4 4000 6000 3 3 % dBc/Hz dBc/Hz MHz dBm LN(f) (Note 7) fExtVCOin pExtVCOin www.national.com 6 LMX2541 Symbol Parameter Conditions VCO Specifications 2060E 2380E Mode = Full Chip Mode This is the frequency before the VCO divider. 2690E 3030E 3320E 3740E Min 1990 2200 2490 2810 3130 3480 125 2060E 2380E Typ Max 2240 2530 2865 3230 3600 4000 Units fVCO Internal VCO Frequency Range MHz ΔTCL Maximum Allowable Temperature Drift for Continuous Lock (Note 6),(Note 8) °C 3.5 2.8 1.6 1.2 0.2 - 0.3 1 dB 0.5 13 - 23 16 - 30 17 - 32 20 - 37 21 - 37 27 - 42 MHz/V dBm pRFout RF Output Power Maximum Frequency Default Power Mode VCO_DIV=1 2690E 3030E 3320E 3740E ΔPRFout Change in Output Power (Note 6) Fixed Temperature with 100 MHz frequency change at the output Fixed frequency with a change over the entire temperature range The lower number in the range applies when the VCO is at its lowest frequency and the higher number applies when the VCO is at its highest frequency. A linear approximation can be used for frequencies between these two cases. 2060E 2380E 2690E 3030E 3320E 3740E 2060E 2380E VCO_DIV=1 Default Power Mode (Note 5) 50 Ω Load VCO_DIV=3 2690E 3030E 3320E 3740E 2060E 2380E 2690E 3030E 3320E 3740E KVtune Fine Tuning Sensitivity -20 -15 HSRFout Second Harmonic dBc -20 -15 PSHVCO PULLVC O VCO Frequency Pushing VCO Frequency Pulling CVregVCO = 4.7 µF,Open Loop VSWR 1.7 to 1 (6 dB Pad) Integration Bandwidth = 100 Hz to 20 MHz Middle VCO Frequency 100 MHz Wenzel Crystal Reference Integer Mode Optimized Loop Bandwidth VCO_DIV = 1 VCO_DIV > 1 2060E 2380E 2690E 3030E 3320E 3740E 600 ±800 ±60 1.6 1.8 2.1 2.1 2.3 2.6 kHz/V kHz σΦ RMS Phase Error mRad 7 www.national.com LMX2541 Symbol Parameter Conditions VCO Phase Noise (Note 9) 10 kHz Offset fRFout = Min VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset 10 kHz Offset fRFout = Max VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset 10 kHz Offset fRFout = Min VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset 10 kHz Offset fRFout = Max VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset 10 kHz Offset fRFout = Min VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset 10 kHz Offset fRFout = Max VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset 10 kHz Offset fRFout = Min VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset 10 kHz Offset fRFout = Max VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset Min Typ -89.7 -113.7 -134.9 -155.4 -160.3 -86.5 -111.4 -132.8 -153.4 -158.5 -87.9 -112.7 -133.8 -154.2 -159.5 --83.4 -109.1 -130.8 -151.8 -157.5 -86.9 -111.8 -133.3 -154.2 -159.4 -82.3 -108.4 -130.3 -151.1 -156.7 -86.1 -110.5 -132.0 -152.2 -157.1 -82.2 -107.7 -129.4 -150.5 -156.1 Max Units L(f)Fout Phase Noise 2060E dBc/Hz L(f)Fout Phase Noise 2380E dBc/Hz L(f)Fout Phase Noise 2690E dBc/Hz L(f)Fout Phase Noise 3030E dBc/Hz www.national.com 8 LMX2541 Symbol Parameter fRFout = Min VCO Frequency Conditions 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset 10 kHz Offset fRFout = Max VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset 10 kHz Offset fRFout = Min VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz offset 20 MHz Offset 10 kHz Offset fRFout = Max VCO Frequency 100 kHz Offset 1 MHz Offset 10 MHz Offset 20 MHz Offset Min Typ -84.1 -109.1 -130.7 -151.6 -156.9 -82.0 -107.0 -128.5 -149.6 -155.2 -83.9 -108.3 -129.9 -150.6 -156.5 -81.6 -106.5 -127.7 -148.6 -154.2 Max Units L(f)Fout Phase Noise 3320E dBc/Hz L(f)Fout Phase Noise 3740E dBc/Hz 9 www.national.com LMX2541 Symbol VIH VIL IIH IIL VOH VOL ILeak Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current High-Level Output Voltage Low-Level Output Voltage Leakage Current Conditions Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout,RFoutEN) Min 1.6 Typ Max Vcc 0.4 3.0 3.0 Units V V µA µA V V nA nA ns ns ns ns ns ns ns VIH = 1.75, XO = 0 VIL = 0 V , XO = 0 IOH = 500 µA IOL = -500 µA Ftest/LD and FLout Pins Only MICROWIRE Timing Attached to Vcc Attached to GND -3.0 -3.0 2.0 0.0 -10 -10 25 25 20 25 25 25 25 0.4 10 10 tCE tCS tCH tCWH tCWL tCES tEWH Clock to Enable Low Time Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Enable to Clock Set Up Time Enable Pulse Width High See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing See Data Input Timing Note 5: The LMX2541 RFout power level is programmable with the program words of VCOGAIN, OUTTERM, and DIVGAIN. Changing these words can change the output power of the VCO as well as the current consumption of the output buffer. For the purpose of consistency in electrical specifications, "Default Power Mode" is defined to be the settings of VCOGAIN = OUTTERM = DIVGAIN = 12. Note 6: Not tested in production. Guaranteed by characterization. Note 7: Consult the applications section for more details on these parameters. Note 8: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that the R0 register was last programmed, and still have the device stay in lock. The action of programming the R0 register, even to the same value, activates a frequency calibration routine. This implies that the device will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the device was initially programmed at, the temperature can never drift outside the frequency range of -40°C ≤TA≤ 85°C without violating specifications. Note 9: The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The phase noise is measured with AC_TEMP_COMP = 5 and the device is reloaded at each test frequency. The typical performance characteristics section shows how the VCO phase noise varies over temperature and frequency. Note 10: See Typical Performance Characteristics for more information. www.national.com 10 LMX2541 Serial Data Timing Diagram 30073303 The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift registers to an actual counter. A slew rate of at least 30 V/μs is recommended for these signals. After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state. If the CLK and DATA lines are toggled while the in VCO is in lock , as is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming. 11 www.national.com LMX2541 Typical Performance Characteristics (Not Guaranteed) PLL Phase Noise 30073307 The above plot demonstrates the PLL phase noise of the LMX2541SQ3700E operating at 3700 MHz output frequency, phase detector frequency of 100 MHz, and charge pump gain of 32X. The loop bandwidth was made as wide as possible to fully expose the PLL phase noise and reference source was a 100 MHz Wenzel crystal. This measurement was done in integer mode. To better understand the impact of using fractional mode, consult the applications section. The measured noise is the sum of the PLL 1/f noise and noise floor. At offsets below 1 kHz, the PLL 1/f noise is dominates and changes as 10 dB/decade. The noise at 1 kHz is dominated by this 1/f noise and has a value of -103 dBc/Hz. In the 100 - 200 kHz offset range, the noise is -113.7 dBc/Hz and is dominated by the PLL noise floor. It can be shown that if the effects of the loop filter peaking and the 1/f noise are subtracted away from this measurement, it would be about 0.6 dB better. If the phase detector frequency is changed with the VCO frequency held constant, the PLL noise floor will change, but the 1/f noise will remain the same. If the VCO frequency is changed, both the 1/f noise and PLL noise floor change as 20 dB/decade. Divider Noise Floor vs. Divider Value Value (fVCO = 3700 MHz, Various values for VCO_DIV) 30073326 When the divider is engaged (VCO_DIV >0), then the entire system phase noise is reduced by a factor of 20 × log(VCO_DIV). However, the noise floor of the divider will also add to this noise as is visible at far offsets. Note that the noise floor for Bypass mode is lower because the VCO divider is not engaged. www.national.com 12 LMX2541 PLL Normalized Noise Floor vs. Slew Rate (KPD = 32X) PLL Normalized 1/f Noise vs. Slew Rate (KPD = 32X) 30073308 30073309 PLL Normalized Noise Floor vs. Charge Pump Gain (Slew Rate = 2000 V/μs) PLL Normalized 1/f Noise vs. Charge Pump Gain (Slew Rate = 2000 V/μs) 300733010 300733011 13 www.national.com LMX2541 VCO Phase Noise Degradation vs. Temperature and Offset (VCO Relocked at Each Temperature Vcc = 3.3 V, AC_TEMP_COMP = 5) 30073312 The above plot shows how much the VCO phase noise typically change over temperature relative to room temperature. The typical values for represent an average over all frequencies and part options and therefore there are some small variations over part options and frequencies that are not shown .VCO phase noise numbers room temperature are reported in the electrical specifications. A negative value indicates a phase noise improvement. Relative VCO Phase Noise Over Temperature Drift (AC_TEMP_COMP = 25, Vcc = 3.3 V) Temperature Lock -40 -40 -40 25 25 25 85 85 85 Current -40 25 85 -40 25 85 -40 25 85 10 kHz +0.4 +0.3 +0.9 +0.2 +0.6 +0.2 +0.2 +0.6 Phase Noise Change in Celsius for Various Offsets 100 kHz -2.0 +0.5 +2.0 -2.2 +1.5 -2.2 +0.2 +1.8 1 MHz -1.6 +0.5 +2.4 -1.7 +2.0 -1.7 +0.3 +2.2 10 MHz -1.8 +0.5 +2.5 -2.0 +2.0 -1.9 +0.2 +2.3 20 MHz -1.6 +0.4 +2.3 -1.8 +1.9 -1.8 +0.2 +2.1 This is the default condition to which these other numbers are normalized to. The above table shows the typical degradation for VCO phase noise when the VCO is locked at one temperature and the temperature is allowed to drift to another temperature. A negative value indicates a phase noise improvement. www.national.com 14 LMX2541 Output Power vs Voltage (VCO_DIV = 1, VCOGAIN = 12, OUTTERM = 12, TA = 25°C ) Output Power vs. Temperature (VCO_DIV = 1, VCOGAIN = 12, OUTTERM = 12, Vcc = 3.3 V ) 30073316 30073317 Output Power vs. OUTTERM and FREQUENCY (VCO_DIV = 1, TA = 25 °C, Vcc = 3.3 V, VCOGAIN = 12 ) Output Power vs. VCOGAIN and FREQUENCY (VCO_DIV = 1, TA = 25 °C, Vcc = 3.3 V, OUTTERM = 12 ) 30073315 30073314 The above plots show the trends in output power as a function of temperature, voltage, and frequency. For states where VCOGAIN and OUTTERM are not 12, the table below shows how the output power is modified based on these programmable settings. Change in Output Power in Bypass Mode as a Function of VCOGAIN and OUTTERM 3 3 OUTTERM 6 9 12 15 -9.7 -6.6 -5.7 -5.4 -5.3 6 -8.4 -4.5 -3.1 -2.5 -2.2 VCOGAIN 9 -7.9 -3.6 -1.7 -0.8 -0.3 12 -7.8 -3.4 -1.3 0.0 0.8 15 -7.9 -3.6 -1.3 0.1 1.1 15 www.national.com LMX2541 Output Power vs Voltage (VCO_DIV > 1, VCOGAIN = 12, OUTTERM = 12, TA = 25°C ) Output Power vs. Temperature ( VCO_DIV > 1, DIVGAIN = OUTTERM = 12, Vcc = 3.3 V ) 30073320 30073321 Output Power vs. OUTTERM and FREQUENCY (VCO_DIV = 1, TA = 25 °C, Vcc = 3.3 V, VCOGAIN = 12 ) Output Power vs. DIVGAIN and FREQUENCY (VCO_DIV > 1, TA = 25 °C, Vcc = 3.3 V, OUTTERM = 12 ) 30073319 30073318 The table below shows the RELATIVE output power to the case of VCOGAIN = OUTTERM = 12. Change in Output Power in Divided Mode as a Function of DIVGAIN and OUTTERM 3 3 OUTTERM 6 9 12 15 -10.2 -6.1 -5.7 -5.5 -5.5 6 -9.8 -4.4 -2.4 -2.1 -2.0 DIVGAIN 9 -9.8 -4.3 -1.5 -0.7 -0.5 12 -9.9 -4.3 -1.4 0.0 0.2 15 -9.9 -4.4 -1.4 0.3 0.7 www.national.com 16 LMX2541 1.0 Functional Description The LMX2541 is a low power, high performance frequency synthesizer system which includes the PLL, VCO, and partially integrated loop filter. The following sections give a discussion of the various blocks of this device. 1.1 REFERENCE OSCILLATOR INPUT PINS There are three basic ways that the OSCin/OSCin* pins may be configured as shown in the table below: Mode Crystal Single -Ended Description Device is used with a crystal oscillator Device is driven with a singleended source, such as a TCXO. Use this mode when driving with a differential signal, such as an LVDS signal. XO Bit 1 The order of the delta sigma modulator is programmable from integer mode to fourth order. There are also several dithering modes that are also programmable. In order to make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed. 1.5 PARTIALLY INTEGRATED LOOP FILTER The LMX2541 integrates the third pole (formed by R3_LF and C3_LF) and fourth pole (formed by R4_LF and C4_LF) of the loop filter. The values for these integrated components can be programmed independently through the MICROWIRE interface. The larger the values of these components, the stronger the attenuation of the internal loop filter. The maximum attenuation can be achieved by setting the internal resistors and capacitors to their maximum value and the minimum attenuation can be attained by setting all of these to their minimum setting. This partially integrated loop filter can only be used in full chip mode. 0 Differential 0 In addition to the way that the OSCin/OSCin* pins are driven, there are also bits that effect the frequency that the chip uses. The OSC_FREQ word needs to be programmed correctly, or the VCO may have issues locking to the proper frequency, since the VCO frequency calibration is based on this word. Word Name OSC_FREQ Function This needs to be set correctly if the internal VCO is used for proper calibration. This allows the oscillator frequency to be doubled. The R divider is bypassed in this case. 30073304 OSC2X Higher slew rates tend to yield the best fractional spurs and phase noise, so a square wave signal is best for OSCin. Single ended mode and differential mode have similar results if a square wave is used to drive the OSCin pin. If using a sine wave, higher frequencies tend to work better due to their higher slew rates. 1.2 R DIVIDER The R divider divides the OSCin frequency down to the phase detector frequency. If the doubler is enabled, then the R divider is bypassed. 1.3 PHASE DETECTOR AND CHARGE PUMP The phase detector compares the outputs of the R and N dividers and generates a correction current corresponding to the phase error. This charge pump current is software programmable to 32 different levels.The phase detector frequency, fPD, can be calculated as follows: fPD = fOSCin / R 1.4 N DIVIDER AND FRACTIONAL CIRCUITRY The N divider in the LMX2541 includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to 4,194,303. The integer portion, PLL_N, is the whole part of the N divider value and the fractional portion, PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM, and PLL_DEN are software programable. So in general, the total N divider value, N, is determined by: N = PLL_N + PLL_NUM / PLL_DEN 1.6 LOW NOISE, FULLY INTEGRATED VCO The LMX2541 includes a fully integrated VCO, including the inductors. The VCO (Voltage Controlled Oscillator) takes the voltage from the loop filter and converts this into a frequency. The VCO frequency is related to the other frequencies and divider values as follows: fVCO = fPD × N = fOSCin × N / R In order to the reduce the VCO tuning gain and therefore improve the VCO phase noise performance, the VCO frequency range is divided into many different frequency bands. This creates the need for frequency calibration in order to determine the correct frequency band given a desired output frequency. The frequency calibration routine is activated any time that the R0 register is programmed. It is important that the OSC_FREQ word is set correctly to have this work correctly. The time that the frequency calibration takes is dependent on fOSCin and the size of the frequency change. As a general rule of thumb, this time improves for higher OSCin frequencies and is on the order of 200 us for an OSCin freqency of 100 MHz and a small frequency change. For frequency changes on the order of the entire VCO tuning range, this time is closer to 300 us. The VCO also has an internal amplitude calibration algorithm to optimize the phase noise which is also activated any time the R0 register is programmed. The optimum internal settings for this are temperature dependent. If the temperature is allowed to drift too much without being re-calibrated, some minor phase noise degradation could result. For applications where this is an issue, the AC_TEMP_COMP word can be used to sacrifice phase noise at room temperature in order to improve the VCO phase noise over all temperatures. The maximum allowable drift for continuous lock, ΔTCL, is stated 17 www.national.com LMX2541 in the electrical specifications. For this part, a number of +125 C means the part will never lose lock if the part is operated under recommended operating conditions. 1.7 PROGRAMMABLE VCO DIVIDER The VCO divider can programmed to any value from 2 to 63 as well as bypass mode if device is in full chip mode. In external VCO mode or divider mode, all values except bypass mode can be used for the VCO divider. The VCO divider is not in the feedback path between the VCO and the PLL and therefore has no impact on the PLL loop dynamics. After this programmable divider is changed, it may be beneficial to reprogram the R0 register to recallibrate the VCO . The frequency at the RFout pin is related to the VCO frequency and divider value, VCO_DIV, as follows: fRFout = fVCO / VCO_DIV When this divider is enabled, there will be some far-out phase noise contribution to the VCO noise. Also, it may be beneficial for VCO phase noise to reprogram the R0 register to recalibrate the VCO if the VCO_DIV value is changed from bypass to divided, or vise-versa. The duty cycle for this divider is always 50%, even for odd divide values. Because of the architecture of this divider that allows it to work to high frequencies and always have a 50% duty cycle, there are a few extra considerations: • In divider only mode, there must be 5 clock cycles on the CLK pin after the divide value is programmed in order to cause the divide value to properly changed. It is fine to use more than 5 clock cycles for this purpose. • For a divde of 4 or 5 ONLY, the R4 register needs to be programmed one more time after the R0 register is loaded in order to synchronize the divider. Failure to do so will cause the wrong divide values. Furthermore, if the VCO signal ever goes away, as is the case when the part is powered down, it is necessary to reprogram the R4 register again to re-synchronize the divider. 1.8 PROGRAMMABLE RF OUTPUT BUFFER The output power at the RFout pin can be programmed to various levels as well as on and off states. The output state of this pin is controlled by the RFoutEN pin as well as the RFOUT word. The RF output buffer can be disabled while still keeping the PLL in lock. In addition to this, the actual output power level of this pin can be adjusted using the VCOGAIN, DIVGAIN, and OUTTERM programming words. 1.9 POWERDOWN MODES The LMX2541 can be powered up and down using the CE pin or the POWERDOWN bit. When the device is powered down, the programming and VCO calibration information is retained, so it is not necessary to re-program the device when the device comes out of the powered down state (The one exception is when the VCO_DIV value is 4 or 5, which has already been discussed.). The following table shows how to use the bit and pin. CE Pin Low High POWERDOWN Bit Don't Care 0 1 Device State Powered Down Powered Up Powered Down run in the powerdown state. Also, the special programming for VCO_DIV = 4 or 5 has to be done when the part is powered up. In order for the CE pin to properly power the device down when it is held low, the all the registers in the device need to have been programmed at least one time. 1.10 FASTLOCK The LMX2541 includes the Fastlock™ feature that can be used to improve the lock times. When the frequency is changed, a timeout counter is used to engage the fastlock for a programmable amount of time. During the time that the device is in Fastlock, the FLout pin changes from high impedance to low, thus switching in the external resistor R2pLF with R2_LF as well as changing the internal loop filter values for R3_LF and R4_LF. 30073305 The following table showshow the charge pump gain, loop filter resistors, and FLout pin change between normal operation and Fastlock. Parameter Charge Pump Gain Loop Filter Resistor R3_LF Loop Filter Resistor R4_LF FLout Pin Normal Operation CPG R3_LF R4_LF High Impedance Fastlock FL_CPG FL_R3_LF FL_R4_LF Low Once the loop filter values and charge pump gain are known for normal mode operation, they can be determined for fastlock operation as well. In normal operation, one can not use the highest charge pump gain and still use fastlock because there will be no larger current to switch in. If the resistors and the charge pump current are done simultaneously, then the phase margin can be preserved while increasing the loop bandwidth by a factor of K as shown in the following table: Parameter Charge pump gain in Fastlock Loop Bandwidth Multiplier Internal Loop Filter Resistor Internal Loop Filter Resistor External Loop Filter Resistor Symbol FL_CPG K FL_R3_LF FL_R4_LF R2pLF Calculation Typically choose to be the largest value. K= sqrt (FL_CPG/CPG) FL_R3_LF = R3_LF / K FL_R4_LF = R4_LF / K R2pLF = R2_LF / (K - 1) The device can be programmed in the powerdown state. However, the VCO frequency needs to be changed when the device is powered up because the VCO calibration does not www.national.com 18 LMX2541 1.11 LOCK DETECT The Ftest/LD pin of the LMX2541 can be configured to support both analog and digital lock detect. The analog lock detect is generally more of a legacy feature and requires an external RC. When configured for push-pull analog lock detect, the Ftest/LD is high with narrow pulses which corresponds to when the charge pump is on. This waveform can be integrated with an RC filter to generate a lock detect signal. The open drain lock detect is similar pin puts out short low pulses when the charge pump comes on. An external RC filter can be used to integrate this information. Open drain analog lock detect is typically implemented with an RC filter followed by a pull-up resistor. The pull-up resistor can be much larger than the resistor in the RC filter in order to make unbalanced time constants for improved sensitivity. The digital lock detect function can be selected for the Ftest/ LD pin. The digital lock detect circuitry compares the difference between the phase of the inputs to the phase detector with a RC generated delay of ε. To indicate a locked state (Lock = HIGH) the phase error must be less than ε for 5 consecutive phase detector cycles. Once in lock (Lock = HIGH), the RC delay is changed to δ. To indicate an out of lock state (Lock = LOW), the phase error must become greater than δ. The values of ε and δ are programmable with the DLOCK word. 30073306 19 www.national.com LMX2541 2.0 General Programming Information The LMX2541 is programmed using several 32-bit registers used to control the LMX2541 operation. A 32-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a data field and an address field. The last 4 register bits, CTRL[3:0] form the address field, which is used to decode the internal register address. The remaining 28 bits form the data field DATA[27:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock (data is programmed MSB first). When LE goes high, data is transferred from the data field into the selected register bank. For initial device programming the register programming sequence must be done in the order as shown in the register map. The action of programming register R7 resets all the registers to default values, including hidden registers. The programming of register R1 and R0 is also special for the device when operating in full chip mode because the action of programming either one of these registers activates the VCO calibration. For changes after this initial setup, see the Applications Information section. www.national.com 20 2.01 Register Map The following table lists the registers as well as the order that they should be programmed. Register 7 is programmed first and the action of programming register R7 resets all the registers after the LE pin is pulled to a low state. Register R0 is programmed last because it activates the VCO calibration. The one exception to this is when the VCO_DIV value is 4 or 5. Consult the programming section on VCO_DIV for more details. 25 DATA[27:0] 0 0 0 0 FL_R4_LF [2:0] FL_R3_LF[2:0] R3_LF[2:0] FDM DEN[21:0] PLL_N[17:12] PLL_R[11:0] PLL_N[11:0] PLL_NUM[15:0] OSC _2X CPP MUX[3:0] CPG[4:0] VCO_DIV[5:0] FL_TOC[13:0] OSC_FREQ[7:0] XO PWDN MODE [1:0] R4_LF[2:0] DITH [1:0] ORDER[2:0] 0 0 0 0 1 1 1 VCOGAIN[3:0] OUTTERM[3:0] DIVGAIN[3:0] 1 0 0 0 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 AC_TEMP_COMP[4:0] RFOUT [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VCO_DIV_OPT[2:0] 0 1 1 0 0 0 0 0 0 0 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 C3 2 C2 1 1 0 1 1 1 0 0 0 0 1 C1 1 0 0 1 0 0 1 1 0 0 0 C0 1 1 0 0 1 0 1 0 1 0 31 30 29 28 27 26 R7 0 0 0 0 0 0 R13 0 0 0 0 0 0 R8 0 0 0 0 0 0 R6 0 0 0 0 0 0 R5 1 0 1 FL_CPG[4:0] R4 CPT C4_LF[3:0] C3_LF[3:0] R3 FSK 0 0 DLOCK[2:0] R2 0 0 0 0 0 1 LMX2541 21 R1 0 0 0 0 PLL_NUM[21:16] R0 www.national.com LMX2541 2.1 REGISTER R7 Although Register 7 has no elective bits to program, it is very important to program this register because the action of doing so with the bit sequence shown in the register map resets all the registers, including hidden registers with test bits that are not disclosed. Register 7 should always be programmed first, because it will clear out all other programming information. The register reset occurs only after the LE signal has transitioned from low to high and back to low again. 2.1.1 REGISTER R13 This register needs to be programmed only in the event that the RFout pin is being used and VCO_DIV = 1. VCO_DIV_OPT[2:0] This word optimizes the RFout power level based on the VCO divider in the case that VCO_DIV = 1. In this case, this word should be programmed to 15. Otherwise, this word does not need to be programmed. Condition VCO_DIV = 1, RFout pin not disabled All other conditions VCO_DIV_OPT 7 0, but does not need to be programmed. 2.1.2 REGISTER R8 AC_TEMP_COMP[4:0] This word optimizes the VCO phase noise for possible temperature drift. When the VCO frequency is changed, the internal tuning algorithm optimizes the phase noise for the current temperature. In fixed frequency applications, temperature drift may lead to suboptimal phase noise over time. In dynamic frequency applictions, the re-tuning of the VCO frequency overcomes this problem because the phase noise is re-optimized each time the VCO frequency is changed. The AC_TEMP_COMP word can be used to optimize the VCO phase noise for temerature drift for these different scenarios. The following table indicates which values of this word should be used for each scenario. AC_TEMP_COMP 5 24 All Other States 2.2 REGISTER R6 Register R6 has words that impact the output power of the RFout pin. RFOUT[1:0] - RFout enable pin This word works in combination with the EN_RFout Pin to control the state of the RFout pin. RFOUT 0 2 1 or 3 EN_RFout Pin Don't Care Don't Care Low High RFout Pin State Disabled Enabled Disabled Enabled Application Type Dynamic Frequency Fixed Frequency Invalid DIVGAIN[3:0], VCOGAIN[3:0], and OUTTERM[3:0] - Power Controls for RFout These three words may be programmed in a value from 0 to 15 and work in conjunction to control the output power level of the RFout pin. Increasing any of these values increases the output power at the expense of higher current consumption of the buffer. Although there may be more than one way to get the same output power, some combinations may have lower current. The typical performance characteristics show these trade-offs. The default setting for all these bits is 12. The value of VCO_DIV determines which two of these three words have an impact. VCO_DIV 1 (Bypass) >1 (Not Bypass) Bits that Impact Power OUTTERM, VCOGAIN OUTTERM, DIVGAIN www.national.com 22 LMX2541 2.3 REGISTER R5 This register controls the fastlock mode which enables a wider loop bandwidth when the device is changing frequencies. FL_TOC[13:0] -- Time Out Counter for FastLock When the value of this word is 3 or less, FastLock time out counter is disabled, and the FLout pin can be used for general purpose I/O. When this value is 4 or greater, the time out counter is engaged for the amount of phase detector cycles shown in the table below. TOC Value 0 1 2 3 4 . 16383 FLout Pin State High Impedance Low Low High Low . Low Fastlock Engagement Time Disabled Always Engaged Disabled Disabled Engaged for 4 × 2 Phase DetectorCycles . Engaged for 16383 × 2 Phase Detector Cycles When this count is active, the FLout Pin is grounded, the FastLock current is engaged, and the resistors R3 and R4 are also potentially changed. The table below summarizes the bits that control various values in and out of FastLock. FastLock State Not Engaged Engaged FLout High Impedance Grounded Charge Pump Current CPG FL_CPG R3_LF Value R3_LF FL_R3_LF R4_LF Value R4_LF FL_R4_LF FL_R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 During Fastlock FL_R3_LF Value 0 1 2 3 4 5-7 R3 Resistor During Fastlock (kΩ) Low ( 200 Ω ) 1 2 4 16 Reserved FL_R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 During Fastlock FL_R4_LF Value 0 1 2 3 4 5-7 R3 Resistor During Fastlock (kΩ) Low ( 200 Ω ) 1 2 4 16 Reserved 23 www.national.com LMX2541 FL_CPG[4:0] -- Charge Pump Current for Fastlock When FastLock is enabled, this is the charge pump current that is used for faster lock time. Typical Fastlock Charge Pump Current at 3.3 Volts (µA) 100 200 300 400 ... 3200 FL_CPG 0 1 2 3 ... 31 Fastlock Charge Pump State 1X 2X 3X 4X ... 32X www.national.com 24 LMX2541 2.4 REGISTER R4 This register controls miscellaneous functions of the device. The action of programming the R4 register also synchronizes the VCO divider, which is necessary when VCO_DIV = 4 or 5. OSC_FREQ [7:0] -- OSCin Frequency for VCO Calibration Clocking This word is used for the VCO frequency calibration. This word should be set to the OSCin frequency rounded to the nearest MHz. OSC_FREQ 0 1 2 ... 255 VCO_DIV[5:0] - VCO Divider The output of the VCO is divided by the value of VCO_DIV, which can range from 1 (Bypass Mode) to 63 and all values in between. There are a few special considerations. The VCO divider can only be set to bypass mode when the device is operating in full chip mode. Also, there is one extra programming step required to synchronize the VCO divider when it has a value of 4 or 5. This extra programming step is to load all registers as normal and then re-load register R4 with the same value. . When VCO_DIV=4 or 5, it is also necessary to re-synchronize the divider in Fulll chip mode whenever the R0 or R1 registers are reprogrammed, or in External VCO or Divider Only mode whenever the VCO signal goes away temporarily. This re-synchronization is ONLY for VCO_DIV values of 4 and 5. When VCO_DIV is 4 or 5 ONLY, the R4 register needs to be programmed one additional time (after the R0 register is loaded) with the same value after the VCO signal (or ExtVCOin) signal is applied. If the VCO signal ever goes away, as is the case when the chip is powered down, or the VCO signal is taken away in External VCO or Divider Only mode, the R4 register needs to be reloaded again to re-synchronize the divider. VCO_DIV 0 1 2 3 4 5 6 ... 62 63 VCO Output Divide n/a Bypass Mode Divide by 2 Divide by 3 Divide by 4 Divide by 5 Divide by 6 ... Divide by 62 Divide by 63 Extra programming is required for divide by 4 and divide by 5 only. Refer to the functional description for more details. Comments Illegal State This state only available for MODE=Full Chip Mode OSCin Frequency Illegal State 1 MHz 2 MHz ... 255 MHz R3_LF[2:0] -- Value for Internal Loop Filter Resistor R3 This word controls the state of the internal loop filter resistor R3_LF when the device is in Full Chip Mode and Fastlock is not active. R3_LF Value 0 1 2 3 4 5-7 R4_LF[2:0] -- Value for Internal Loop Filter Resistor R4 This word controls the state of the internal loop filter resistor R4_LF when the device is in Full Chip Mode and Fastlock is not active. R3 Resistor During Fastlock (kΩ) Low ( 200 Ω ) 1 2 4 16 Reserved 25 www.national.com LMX2541 R4_LF Value 0 1 2 3 4 5-7 R3 Resistor During Fastlock (kΩ) Low ( 200 Ω ) 1 2 4 16 Reserved C3_LF[3:0] -- VALUE FOR C3 IN THE INTERNAL LOOP FILTER This word controls the state of the internal loop filter resistor C3_LF when the device is Full Chip Mode. C3_LF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C4_LF[3:0] -- VALUE FOR C4 IN THE INTERNAL LOOP FILTER This word controls the state of the internal loop filter resistor C4_LF when the device is Full Chip Mode. C4_LF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C4 (pF) 0 5 20 25 40 45 60 65 100 105 120 125 140 145 160 165 C3 (pF) 0 1 5 6 10 11 15 16 20 21 25 26 30 31 35 26 www.national.com 26 LMX2541 2.5 REGISTER R3 This register controls miscellaneous features of the device. MODE[1:0] -- Operational Mode The LMX2541 can be run in several operational modes as listed in the table below: MODE 0 1 2 3 PWDN -- Powerdown Bit Enabling this bit powers down the entire device, although register and VCO calibration information is retained. XO - Crystal Oscillator Mode Select When this bit is enabled, a crystal with appropriate load capacitors can be attached between the OSCin and OSCin* pins in order to form a crystal oscillator. CPG[4:0] -- Charge Pump Current This word programs the charge pump current gain. The current is programmable between 100 uA and 3.2 mA in 100 uA steps. CPG 0 1 2 3 ... 31 Charge Pump State 1X 2X 3X 4X ... 32X 3200 Typical Charge Pump Current (µA) 100 200 300 ... Name Full External VCO Divider Only Test (Reserved) Divider Enabled Enabled Enabled Enabled PLL Enabled Enabled Disabled Enabled VCO Enabled Disabled Disabled Enabled 27 www.national.com LMX2541 MUX[3:0] -- Multiplexed Output for Ftest/LD Pin The MUX[3:0] word is used to program the output of the Ftest/LD Pin. This pin can be used for a general purpose I/O pin, a lock detect pin, and for diagnostic purposes. When programmed to the digital lock detect state, the output of the Ftest/LD pin will be high when the device is in lock, and low otherwise. The output voltage level of the Ftest/LD is not equal to the supply voltage of the device, but rather is given by VOH and VOL in the electrical characteristics specification. Because the Ftest/LD pin is close to the OSCin pin, the state of this pin can have an impact on the performance of the device. If any of the diagnostic modes (8-13) are used, the OSCin sensitivity can be severely degraded, so these should only be used for diagnoistic purposes. The fractional spurs can also be impacted a little by fractional spurs. The Push-Pull digital lock detect modes, like mode 3, tend to have the best fractional spurs, so these states are recommended, even if the digital lock detect function is not needed. MUX 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14-15 Output Type High Impedance Push-Pull Push-Pull Push-Pull Push-Pull Open Drain Open Drain Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull N/A Function Disabled Logical High State Logical Low State Digital Lock Detect Inverse Digital Lock Detect Digital Lock Detect Analog Lock Detect Analog Lock Detect N Divider N Divider / 2 R Divider R Divider / 2 PFD Up PFD Down Reserved Diagnostic Modes These allow the user to view the outputs of the N divider, R divider, and phase frequency detector (PFD) and are intended only for diagnostic purposes. Typically, the output is narrow pulses, but when the output is divded by 2, there is a 50% duty cycle. The use of these modes (including R Divider) can degrade the OSCin sensitivity. Lock Detect Modes Consult Functional Description for more details State 3 is recommended for optimal spurious performance. General Purpose I/O Modes Comments CPP - Charge Pump Polarity This bit sets the polarity of the phase detector. CPP 0 1 Charge Pump Polarity Positive Negative Typical Applications External VCO Mode Full Chip Mode External VCO Mode with an inverting active filter. OSC2X-- OSCin Frequency Doubler Enabling this bit doubles the OSCin frequency. This is useful in achieving a higher phase detector frequency to improve PLL phase noise, push out noise from the delta sigma modulator, and sometimes reduce fractional spurs . Note that when this bit is enabled, the R divider is bypassed. OSC_2X 0 1 FDM - Extended Fractional Denomoinator Mode Enable Enabling this bit allows the fractional numerator and denominator to be expanded from 10 bits to 22 bits. In 10-bit mode, only the first 10 bits of the fractional numerator and denominator are considered. Disabling this saves about 0.5 mA of current. When using FSK mode, this bit has to be disabled. FDM 0 1 (Default) Fractional Mode 10-bit 22-bit State Normal OSCin frequency is doubled www.national.com 28 LMX2541 ORDER[2:0] -- Delta Sigma Modulator Order This word determines the order of the delta sigma modulator in the PLL. In general, higher order fractional modulators tend to reduce the primary fractional spurs that occur at increments of the channel spacing, but can also create spurs that are at a fraction of the channel spacing. The optimal choice of modulator order is very application specific, however, a third order modulator is a good starting point. The first order modulator has no analog compensation or dithering Delta Sigma Modulator Disabled First Order Second Order Third Order Fourth Order Illegal States n/a n/a Fractional ORDER 0 1 2 3 4 5-7 DITH[1:0] -- Dithering Mode Integer Comments Allows larger N Counter This has no analog compensation or dithering Traditional Delta Sigma Operation Dithering randomizes the delta sigma modulator output. This reduces sub-fractional spurs at the expense of adding phase noise. In general, it is recommended to keep the dithering strength at None or Weak for most applications. Dithering should never be used when the device is used in integer mode or a first order modulator. When using dithering with the other delta sigma modulator orders, it is beneficial to disable it in the case where the fractional numerator is zero, since it can actually create sub-fractional spurs. DITH 0 1 2 3 CPT - Charge Pump Tri-state When this bit is enabled, the charge pump is tri-stated. The Tri-state mode could be useful for open loop modulation applications or as diagnostic tool for measuring the VCO noise, but is generally not used. CPT 0 1 DLOCK[2:0] - Controls for Digital Lock detect This word is controls operation of the digital lock detect function through selection of the window sizes (ε and δ). In order to indicate the PLL is locked, there must be 5 consecutive phase detector output cycles in which the time offset between the R and N counter outputs is less than ε. This will cause the Ftest/LD pin output to go high. Once lock is indicated, it will remain in this state until the time offset between the R and N counter outputs exceeds δ. If the OSCin signal goes away, the digital lock detect circuit will reliably indicate an unlocked condition. Consult the functional description for more details. A larger window size makes the lock detect circuit less sensitive. The window size is limited by the phase detector frequency, fPD. DLOCK 0 (Default) 1 2 3 4 5 6 -7 Maximum fPD All TBD TBD TBD TBD TBD Reserved Window Size (ns) ε 3 5.5 8 10.5 13 15.5 Reserved δ 3 5.5 8 10.5 13 15.5 Reserved Charge Pump Normal Operation Tri-state Dithering Strength Weak Medium Strong Disabled 29 www.national.com LMX2541 FSK - Frequency Shift Keying This bit enables a binary FSK modulation mode using the PLL N counter. Consult the applications section for more details. FSK 0 1 2.6 REGISTER R2 This word contains all the bits of the fractional denominator. These bits apply if the device is being used fractional mode. PLL_DEN[21:0] -- Fractional Denominator These bits determine the fractional denominator. FSK Mode Disabled Enabled PLL_DEN[21:0] Fractional Denominator 0 ... 4194303 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 0 . 1 www.national.com 30 LMX2541 2.7 REGISTERS R1 AND R0 Both registers R1 and R0 contain information for the PLL R counter, N counter, and fractional numerator. The action of programming either one of these registers, even to the same value, runs the VCO calibration when the device has the internal VCO operating. There are some programming words that are split across these two registers. PLL_R[11:0] -- PLL R Divider Value The R divider divides the OSCin signal. Note that if the doubler is enabled, the R divider is bypassed. PLL_R[11:0] 0 1 2 3 ... 4095 0 0 0 ... 1 0 0 0 ... 1 0 0 0 ... 1 0 0 0 ... 1 0 0 0 ... 1 Illegal State 0 0 0 ... 1 0 0 0 ... 1 0 0 0 ... 1 0 0 0 ... 1 0 0 0 ... 1 0 1 1 ... 1 1 0 1 ... 1 PLL_N[17:0] PLL N Divider Value When using integer mode, the PLL N divider value is split up into two different locations. In fractional mode, only the 12 LSB bits of the N counter are used. Based on the order of the modulator, the range is shown in the table below. PLL_N[17:12] LLP footprints in gerber footprint for more complete information on soldering this device reliably. Leadless Leadframe Package (NS Package Number SQA36A), (Bottom View) www.national.com 38 LMX2541 Notes 39 www.national.com LMX2541 Ultra-Low Noise PLLatinum Frequency Synthesizer with Integrated VCO Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero PowerWise® Design University Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/training Serial Digital Interface (SDI) www.national.com/sdi www.national.com/wireless www.national.com/tempsensors SolarMagic™ THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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