LMX3162

LMX3162 Single Chip Radio Transceiver PRELIMINARY March 2000 LMX3162 Single Chip Radio Transceiver General Description The LMX3162 Single Chip Radio Transceiver is a monolithic, integrated radio transceiver optimized for use in ISM 2.45 GHz wireless systems. It is fabricated using National’s ABiC V BiCMOS process (fT = 18 GHz). The LMX3162 contains phase locked loop (PLL), transmit and receive functions. The 1.3 GHz PLL is shared between transmit and receive sections. The transmitter includes a frequency doubler, and a high frequency buffer. The receiver consists of a 2.5 GHz low noise mixer, an intermediate frequency (IF) amplifier, a high gain limiting amplifier, a frequency discriminator, a received signal strength indicator (RSSI), and an analog DC compensation loop. The PLL, doubler, and buffers can be used to implement open loop modulation along with an external VCO and loop filter. The circuit features on-chip voltage regulation to allow supply voltages ranging from 3.0V to 5.5V. Two additional voltage regulators provide a stable supply source to external discrete stages in the Tx and Rx chains. The IF amplifier, high gain limiting amplifier, and discriminator are optimized for 110 MHz operation, with a total IF gain of 85 dB. The single conversion receiver architecture provides a low cost, high performance solution for communications systems. The RSSI output may be used for channel quality monitoring. The Single Chip Radio Transceiver is available in a 48-pin 7mm X 7mm X 1.4mm PQFP surface mount plastic package. Features n Single chip solution for ISM 2.45 GHz RF transceiver n System RF sensitivity to −93 dBm; RSSI sensitivity to −100 dBm n Two regulated voltage outputs for discrete amplifiers n High gain (85 dB) intermediate frequency strip n Allows unregulated 3.0V–5.5V supply voltage n Power down mode for increased current savings n System noise figure 6.5 dB (typ) Applications n n n n ISM 2.45 GHz frequency band wireless systems Personal wireless communications (PCS/PCN) Wireless local area networks (WLANs) Other wireless communications systems Block Diagram DS100929-1 MICROWIRE™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS100929 www.national.com LMX3162 LMX3162 Connection Diagram DS100929-2 Top View Order Number LMX3162VBH or LMX3162VBHX See NS Package Number VBH48A Pin Descriptions Pin No. 1 2 Pin Name VCC MIXEROUT I/O — O Description Power supply for CMOS section of PLL and ESD bussing. IF output from the mixer. 3 4 5 VCC GND RFIN — — I Power supply for mixer section. Ground. RF input to the mixer. 6 GND — Ground. www.national.com 2 LMX3162 Pin Descriptions Pin No. 7 Pin Name Tx VREG (Continued) I/O — Description Regulated power supply for external PA gain stage. 8 9 10 VCC GND TxOUT — — O Power supply for analog sections of PLL and doubler. Ground. Frequency doubler output. 11 12 13 14 15 GND VCC GND GND fIN — — — — I Ground. Power supply for analog sections of PLL and doubler. Ground. Ground. RF Input to PLL and frequency doubler. 16 CE I Chip Enable. Pulling LOW powers down entire chip. Taking CE HIGH powers up the appropriate functional blocks depending on the state of bits F6, F7, F11, and F12 programmed in F-latch. It is necessary to initialize the internal registers once, after the power up reset. The registers’ contents are kept even in power-down condition. 17 VP — Power supply for charge pump. 18 Do O Charge pump output. For connection to a loop filter for driving the input of an external VCO. 19 20 VCC GND — — Power supply for CMOS section of PLL and ESD bussing. Ground. 3 www.national.com LMX3162 Pin Descriptions Pin No. 21 Pin Name OUT 0 (Continued) I/O O Description Programmable CMOS output. Refer to Function Register Programming Description section for details. 22 Rx PD/OUT 1 I/O Receiver power down control input or programmable CMOS output. Refer to Function Register Programming Description section for details. Transmitter power down control input or programmable CMOS output. Refer to Function Register Programming Description section for details. PLL power down control input. LOW for PLL normal operations, and HIGH for PLL power saving. MICROWIRE™ clock input. High impedance CMOS input with Schmitt Trigger. MICROWIRE data input. High impedance CMOS input with Schmitt Trigger. MICROWIRE load enable input. High impedance CMOS input with Schmitt Trigger. Oscillator input. High impedance CMOS input with feedback. 23 Tx PD/OUT 2 I/O 24 PLL PD I 25 26 27 28 CLOCK DATA LE OSCIN I I I I 29 S FIELD I DC compensation circuit enable. While LOW, the DC compensation circuit is enabled and the threshold is updated through the DC compensation loop. While HIGH, the switch is opened, and the comparator threshold is held by the external capacitor. Received signal strength indicator (RSSI) output. 30 RSSIOUT O 31 THRESH O Threshold level to external comparator. www.national.com 4 LMX3162 Pin Descriptions Pin No. 32 Pin Name DC COMPIN (Continued) I/O I Description Input to DC compensation circuit. 33 DISCOUT O Demodulated output of discriminator. 34 35 36 GND VCC QUADIN — — I Ground. Power supply for the discriminator circuit. Quadrature input for tank circuit. 37 38 39 40 41 42 VCC GND VCC GND VCC LIMIN — — — — — I Power supply for limiter output stage. Ground. Power supply for limiter gain stages. Ground. Power supply for IF amplifier gain stages. IF input to the limiter. 43 44 GND IFOUT — O Ground. IF output from IF amplifier. 45 46 VCC GND — — Power supply for IF amplifier output. Ground. 5 www.national.com LMX3162 Pin Descriptions Pin No. 47 Pin Name IFIN (Continued) I/O I Description IF input to IF amplifier. 48 Rx VREG — Regulated power supply for external LNA stages. www.national.com 6 LMX3162 Absolute Maximum Ratings (Notes 1, 2) Power Supply Voltage (VCC) VP Voltage on Any Pin with GND = 0V (VI) Storage Temperature Range (TS) Lead Temp. (solder, 4 sec)(TL) −0.3V to +6.5V −0.3V to +6.5V −0.3V to VCC +0.3V −65˚C to +150˚C +260˚C Recommended Operating Conditions Supply Voltage (VCC) (VP) Operating Temperature (TA) 3.0V to 5.5V VCC to 5.5V −10˚C to +70˚C Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics section. The guaranteed specifications apply only for the test conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating < KeV and is ESD sensitive. Handling and assembly of this device should only be done at ESD work stations. Electrical Characteristics The following specifications are guaranteed for VCC = 3.6V and TA = 25˚C, unless otherwise specified. Symbol ICC, RX ICC, TX ICC, PLL IPD MIXER fRF fIF ZIN ZOUT NF G P1dB OIP3 FIN-RF RF Frequency Range IF Frequency Input Impedance, RFIN Output Impedance, Mixer Out Noise Figure (Single Side Band) Conversion Gain Input 1dB Compression Point Output 3rd Order Intercept Point Fin to RF Isolation (Notes 5, 6) (Note 5) (Note 5) (Note 5) FIN =1170 MHz, RFOUT=1170 MHz FIN =1170 MHz, RFOUT=2340 MHz FIN =1170 MHz, RFOUT=3510 MHz FIN-IF Fin to IF Isolation FIN =1170 MHz, IFOUT=1170 MHz FIN =1170 MHz, IFOUT=2340 MHz FIN =1170 MHz, IFOUT=3510 MHz RF–IF NF AV ZIN ZOUT Sens IFIN RF to IF Isolation Noise Figure Gain Input Impedance Output Impedance fIN = 110 MHz BER=10−3 (Note 16) fIN = 110 MHz 1X Mode 3X Mode 1X Mode (Note 8) 3X Mode (Note 8) Nominal (Note 10) — — 80 400 1.2 — 10 33 160 580 — 300 — — — — 1.82 — mV/˚ mV/˚ mV mV V Ω — — −65 100–j300 Parameter Current Consumption -Open-Loop Receive Mode -Open-Loop Transmit Mode -PLL only Mode -Power Down Mode Conditions PLL & TX chain powered down PLL & RX chain powered down RX & TX chain powered down fRF = 2.45 GHz, fIF = 110 MHz, f (Note 3) (Note 4) Min — — — — LO Typ 50 27 6 — — 110 12+j6 160−j65 Max 65 40 9 70 2.5 — — — 16 — — — — — — — — — — 11 — — — — — Unit mA mA mA µA GHz MHz Ω Ω dB dB dBm dBm dB dB dB dB dB dB dB dB dB Ω Ω dBm Ω = 2340 MHz (fIN = 1170 MHz) 2.4 — — — — 13 — — — — — — — — — — 15 — — 11.8 17 −20 7.5 −30 −20 −30 −30 −30 −30 −30 8 24 35–j180 210–j50 PIN =0 to −85 dB fIN = 110 MHz (Note 7) (Note 7) IF AMPLIFIER IF LIMITER Limiter/Discriminator Sensitivity IF Limiter Input Impedance Disc Gain (mV/˚ of Phase Shift from Tank Circuit) VOUT VOS Discriminator Output Peak to Peak Voltage Disc. Output DC Voltage DISCOUT Disc. Output Impedance DISCRIMINATOR 7 www.national.com LMX3162 Electrical Characteristics Symbol RSSI (Note 11) RSSIout Output Voltage Slope RSSI VOS VI/O RSH fIN PIN fOSC VOSC Dynamic Range Input Offset Voltage Input/Output Voltage Swing Sample and Hold Resistor Input Frequency Range Input Signal Level Oscillator Frequency Range Oscillator Sensitivity DC COMPENSATION CIRCUIT Parameter (Continued) The following specifications are guaranteed for VCC = 3.6V and TA = 25˚C, unless otherwise specified. Conditions fIN = 110 MHz PIN =−80 dBm@IFIN input pin PIN =−20 dBm@IFIN input pin PIN = −85 to −25 dBm@IFIN input pin PIN min= −90 dBm@IFIN input pin 0.12 0.9 10 — −6 Centered at 1.5V — 2000 (Note 9) ZIN =200Ω (Note 15) (Note 12) (Note 12) Vdo = V P/2, Icpo = LOW (Note 14) Vdo = V P/2, Icpo = LOW (Note 14) Vdo = V P/2, Icpo = HIGH (Note 14) Vdo = V P/2, ICPO = HIGH (Note 14) 0.5 ≤ Vdo ≤ Vp − 0.5 TA = 25˚C fIN = 1225 MHz, fOUT = 2.45 GHz (Note 13) PIN = −11.5 dBm, fOUT = 2.45 GHz PIN = −11.5 dBm, fOUT = 1225 MHz PIN = −11.5 dBm, fOUT = 3.675 GHz ILOAD = 5 mA 2250 −12 — — 2.55 2.4 — GND < VIN < VCC IOH =−0.5 mA IOL =0.5 mA −10 2.4 — — −7.5 −17 −30 2.75 — — — — — 2500 — −10 −15.5 2.90 — 0.8 10 — 0.4 MHz dBm dBm dBm V V V µA V V Output Frequency Range Output Signal Level Fundamental Output Power Harmonic Output Power VOLTAGE REGULATOR VO VIH VIL IIH VOH VOL Output Voltage High Level Input Voltage Low Level Input Voltage Input Current High Level Output Voltage Low Level Output Voltage DIGITAL INPUT/OUTPUT PINS 1100 — 5 0.5 — — — — −1.0 0.2 1.2 18 60 — 1.0 3000 — −11.5 — 1.0 −1.5 1.5 −6.0 6.0 — 0.6 — 25 — +6 — 3600 1300 — 20 — — — — — 1.0 V V mV/dB dB mV VPP Ω MHz dBm MHz Vpp mA mA mA mA nA Min Typ Max Unit FREQUENCY SYNTHESIZER IDo-source Charge Pump Output Current IDo-sink IDo-source IDo-sink IDo-Tri FREQUENCY DOUBLER(Note 17) fOUT POUT Note 3: The mixer section is tested at 2.45 GHz. Note 4: The IF section of this device is designed for optimum performance at 110 MHz. Note 5: The matching network used on RFIN for this measurement consists of a series 3.3 pF capacitance into the pin. The matching circuit used on MIXEROUT consists of a series 150 nH inductance and a shunt 15 pF capacitance into the pin. Note 6: Noise figure measurements are made with matching networks on RFIN and MIXEROUT. See (Note 5). Note 7: The matching network used on pin IFIN for this measurement conists of a series 330 nH inductance and a shunt 2.7 pF capacitance into the pin. The matching network used on pin IFOUT consists of a series 120 nH inductance and a shunt 12 pF into the pin.. Note 8: The discriminator is with the DC level centered at 1.5V. The unloaded Q of the tank is 40. Note 9: The frequency synthesizer section is tested at 1.225 GHz. Note 10: Nominal refers to zero DC offsets programmed for the discriminator. Note 11: It depends on loss of the inter-stage filter. These specifications are for an inter-stage loss of 8 dB. Note 12: The frequency synthesizer section is guaranteed by design to operate for OSCIN input frequency within 5–20 MHz range and minimum amplitude of 0.5 VPP. Note 13: The doubler section is tested at 2.45 GHz. Note 14: See Function Register Programming Description for Icpo description. www.national.com 8 LMX3162 Electrical Characteristics Note 15: Tested in a 50Ω environment. (Continued) Note 16: The matching network used on pin LIMIN for this measurement consists of a series 330 nH inductance and a shunt 1.8 pF into the pin. Note 17: The optimum load as seen by the TX OUT pin should be between 50 and 100 ohms. Typical Performance Characteristics Mixer POUT vs FIN Power with RFIN = −51 dBm, @ 2450 MHz, 25˚C Mixer POUT vs FIN Power with RFIN = −51 dBm, @ 2450 MHz, VCC =3.6V DS100929-16 DS100929-17 RSSI Output vs Input Power to IFIN with VCC as Parameter IDO TRI-STATE™ vs DO Voltage, VCC =5.5V DS100929-19 DS100929-18 9 www.national.com LMX3162 Typical Performance Characteristics Charge Pump Current vs DO Voltage VCC =3.6V, 25˚C (Continued) Charge Pump Current vs DO Voltage, VCC =3.0V, 25˚C DS100929-20 DS100929-21 Mixer OIP3 vs FIN Power Mixer Gain vs FIN Power DS100929-43 DS100929-44 Mixer Output Power vs Mixer Input Power Mixer Gain vs RFIN Frequency DS100929-45 DS100929-46 www.national.com 10 LMX3162 Typical Performance Characteristics SSB Mixer Noise Figure vs RFIN Frequency (Continued) SSB Mixer Noise Figure vs FIN Power DS100929-48 DS100929-47 TX Power Out vs FIN Power TX Power Out vs FIN Frequency DS100929-49 DS100929-50 AC Timing Characteristics Serial Data Input Timing TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an skew rate of 0.6 V / ns. DS100929-3 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. 11 www.national.com LMX3162 Serial Data Input Timing Symbol MICROWIRE™ Interface tCS tCH tCWH tCWL tES tEW Data to Clock Set Up Time Data to Clock Hold Time Clock Pulse Width High Clock Pulse Width Low Parameter (Continued) Conditions Refer to Test Condition. Refer to Test Condition. Refer to Test Condition. Refer to Test Condition. Refer to Test Condition. Refer to Test Condition. Min 50 10 50 50 50 50 Typ — — — — — — Max — — — — — — Unit ns ns ns ns ns ns Clock to Load Enable Set Up Time Load Enable Pulse Width PLL Functional Description The simplified block diagram below shows the building blocks of frequency synthesizer and all internal registers, which are 20-bit data register, 18-bit F-latch, 13-bit N-counter, and 5-bit R-counter. DS100929-4 The DATA stream is clocked into the data register on the rising edge of CLOCK signal, MSB first. The last two bits are the control bits to indicate which register to be written. Upon the rising edge of the LE (Load Enable) signal, the rest of data bits is transferred to the addressed register accordingly. The decoding scheme of the two control bits is as follows: Control Bits C2 0 1 X Note: X = Don’t Care Condition Register C1 0 0 1 N-Counter R-Counter F-Latch Programmable Feedback Divider (N-Counter) The N-counter consists of the 6-bit swallow counter (A-counter) and the 7-bit programmable counter (B-counter). When the control bits are “00”, data is transferred from the 20-bit shift register into two latches. One latch sets the A-counter while the other sets the B-counter. The serial data format is shown below. MSB 19 X 18 X 17 X 16 X 15 X 14 N13 13 N12 12 N11 REGISTER’S BIT MAPPING 11 N10 10 N9 9 N8 8 N7 7 N6 6 N5 5 N4 4 N3 3 N2 2 N1 1 LSB 0 RESERVED Note: X = Don’t Care Condition N-COUNTER’s Divide Ratio C2 0 C1 0 Swallow Counter Divide Ratio (A-Counter) Divide Ratio, A 0 1 * N6 0 0 * N5 0 0 * N4 0 0 * N3 0 0 * N2 0 0 * N1 0 1 * 63 www.national.com 1 1 12 1 1 1 1 LMX3162 Swallow Counter Divide Ratio (A-Counter) Note: Divide ratio must be from 0 to 63, and B must be ≥ A. (Continued) Programmable Counter Divide Ratio (B-Counter) Divide Ratio, B 3 4 * N13 0 0 * N12 0 0 * N11 0 0 * N10 0 0 * N9 0 1 * N8 1 0 * N7 1 0 * 127 1 1 1 1 1 1 1 Note: Divide ratio must be from 3 to 127, and B must be ≥ A. Programmable Reference Divider (R-Counter) If the control bits are “10”, data is transferred from the 20-bit shift register into a latch, which sets the 5-bit R-counter. The serial data format is shown below. MSB 19 18 17 16 15 14 13 REGISTER’S BIT MAPPING 12 11 10 9 8 7 6 5 4 3 2 1 LSB 0 RESERVED X X X X X X X X X X X X X R-COUNTER’s Divide Ratio R5 R4 R3 R2 R1 C2 1 C1 0 Note: X = Don’t Care Condition Reference Counter Divide Ratio (R-Counter) Divide Ratio, R 3 4 * R5 0 0 * R4 0 0 * R3 0 1 * R2 1 0 * R1 1 0 * 31 1 1 1 1 1 Note: Divide ratio must be from 3 to 31. Pulse Swallow Function fvco: B: A: fOSC: R: P: Output frequency of external voltage controlled oscillator (VCO) Preset divide ratio of binary 7-bit programmable counter (3 to 127) Preset divide ratio of binary 6-bit swallow counter (0 ≤ A ≤ P, A ≤ B) Output frequency of the external reference frequency oscillator Preset divide ratio of binary 5-bit programmable reference counter (3 to 31) Preset modulus of dual modulus prescaler (32 or 64) Receiver Functional Description The simplified block diagram below shows the mixer, IF amplifier, limiter, and discriminator. In addition, the DC compensation circuit, doubler, and voltage regulator for an external LNA stage are shown. 13 www.national.com LMX3162 Receiver Functional Description (Continued) DS100929-5 Note 18: The receiver can be powered down, either by hardware through the Rx PD pin, or by software through the programming of F6 bit in the F-Latch. The power down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.) Note 19: The internal capacitor of the discriminator has a value of 1 pF, and has been optimized for operation at 110 MHz. Transmitter Functional Description The simplified block diagram below shows the doubler and voltage regulator for an external transmit gain stage. DS100929-6 Note: The transmitter can be powered down, either by hardware through the Tx PD pin, or by software through the programming of F7 bith in F-Latch. The power down control method is determined by the settings of F11 and F12 in F-Latch. (Refer to Function Register Programming Description section for details.) Function Register Programming Description (F-Latch) If the control bits are “1X”, data is transferred from the 20-bit shift register into the 18-bit F-latch. Serial data format is shown below. MSB 19 F18 18 F17 17 F16 16 F15 15 F14 14 F13 13 F12 REGISTER’S BIT MAPPING 12 F11 11 F10 10 F9 9 F8 8 F7 7 F6 6 F5 5 F4 4 F3 3 F2 2 F1 1 LSB 0 MODE CONTROL WORD Note: X = Don’t Care Condition C2 X C1 1 Various modes of operation can be programmed with the function register bits F1–F18, including the phase detector polarity, charge pump TRI-STATE and CMOS outputs. In addition, software or hardwire power down modes can be specified with bits F11 and F12. www.national.com 14 LMX3162 Function Register Programming Description (F-Latch) Mode Control Bit F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 Mode Control Description Prescaler modules select. Phase detector polarity. It is used to reverse the polarity of the phase detector according to the VCO characteristics. Charge pump current gain select. TRI-STATE charge pump output. Reserved. Setting to “0” always. Receive chain power down control. Software power down can only be activated when both F11 and F12 are set to “0”. Transmit chain power down control. Software power down can only be activated when both F11 and F12 are set to “0”. Out 0 CMOS output. Out 1 CMOS output. Functions only in software power down mode, when both F11 and F12 are set to “0”. Out 2 CMOS output. Functions only in software power down mode, when both F11 and F12 are set to “0”. Power down mode select. Set both F11 and F12 to “0” for software power down mode. Set both F11 and F12 to “1” for hardwire power down mode. Other combinations are reserved for test mode. Demodulator gain select Demodulator DC level shift +/− level shifting polarity Demodulator DC level shift of 1.000V Demodulator DC level shift of 0.500V Demodulator DC level shift of 0.250V Demodulator DC level shift of 0.125V (Continued) Setting to “1” to Select 64/65 Positive VCO Characteristics HIGH Charge Pump Current (4X Icpo). Force to TRI-STATE — Power Down RX Chain Power Down TX Chain OUT 0 = HIGH OUT 1 = HIGH OUT 2 = HIGH Hardware Power Down Setting to “0” to Select 32/33 Negative VCO Characteristics LOW Charge Pump Current (1X Icpo). Normal Operation — Power Up RX Chain Power Up TX Chain OUT 0 = LOW OUT 1 = LOW OUT 2 = LOW Software Power Down F13 F14 F15 F16 F17 F18 1X Gain Mode Set Negative Polarity No Shift No Shift No Shift No Shift 3X Gain Mode Set Positive Polarity Shift the DC Level by 1.000V Shift the DC Level by 0.500V Shift the DC Level by 0.250V Shift the DC Level by 0.125V Power Down Mode/Control Table Software Power Down Mode (F11=F12=0) Pin/Bit F6 F7 PLL PD CE Setting to “0” means Receiver ON Transmitter ON PLL ON LMX3162 OFF Setting to “1” means Receiver OFF Transmitter OFF PLL OFF LMX3162 ON Hardwire Power Down Mode (F11=F12=1) Pin/Bit Rx PD Tx PD PLL PD CE Setting to “0” means Receiver OFF Transmitter OFF PLL ON LMX3162 OFF Setting to “1” means Receiver ON Transmitter ON PLL OFF LMX3162 ON 15 www.national.com LMX3162 Typical Application DS100929-7 www.national.com 16 LMX3162 Loop Filter Design Consideration DS100929-8 FIGURE 1. Conventional PLL Architecture Loop Gain Equations A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 2. The open loop gain is the product of the phase comparator gain (K φ ), the VCO gain (Kvco/s), and the loop filter gain Z(s) divided by the gain of the feedback counter modulus (N). The passive loop filter configuration used is displayed in Figure 3, while the complex impedance of the filter is given in Equation (2). PASSIVE LOOP FILTER Open loop gain = H(s) G(s) = θi/θe = Kφ Z(s)K VCO/Ns (1) (2) The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as (3) and DS100929-9 FIGURE 2. PLL Linear Model T2 = R2 • C2 (4) The 3rd order PLL Open Loop Gain can be calculated in terms of frequency, ω, the filter time constants T1 and T2, and the design constants Kφ, Kvco, and N. DS100929-10 (5) From Equations (3), (4) we can see that the phase term will be dependent on the single pole and zero such that the phase margin is determined in Equation (6). φ (ω) = tan −1 FIGURE 3. Passive Loop Filter (ω • T 2) − tan−1 (ω • T 1) + 180˚ (6) 17 www.national.com LMX3162 Single Chip Radio Transceiver Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead (7mm x 7mm) Molded Plastic Quad Flat Package, JEDEC For Tape and Reel (2500 Units per Reel) Order Number LMX3162VBH or LMX3162VBHX NS Package Number VBH48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.