LP2994M

LP2994 DDR Termination Regulator May 2002 LP2994 DDR Termination Regulator General Description The LP2994 regulator is designed to provide a linear solution to meet the JEDEC SSTL-2 and SSTL-3 specifications (Series Stub Termination Logic) for active termination of DDRSDRAM. The device utilizes an internal operational amplifier to provide linear regulation of VTT without the need for expensive external components. The output stage prevents shoot through while delivering 1.5A continuous current and maintaining excellent load regulation. The LP2994 also incorporates an active low shutdown pin to tri-state the output during Suspend To Ram (STR) states. Patents Pending Features n n n n n n n Source and sink current Low external component count Independent analog and power rails Linear topology Small package SO-8 Low cost and easy to use Shutdown pin Applications n n n n SSTL-2 SSTL-3 DDR-SDRAM Termination DDR-II Termination Typical Application Circuit 20045904 FIGURE 1. SSTL-2 VTT Termination © 2002 National Semiconductor Corporation DS200459 www.national.com LP2994 Connection Diagram SO-8 (M08A) Package 20045902 Top View Pin Description SO-8 Pin 1 2 3 4 5 6 7 8 Name NC GND VSENSE SD VDDQ AVIN PVIN VTT No internal connection Ground Feedback pin for regulating VTT Active low shutdown pin Input for internal reference equal to VDDQ/2 Analog input pin Power input pin Output voltage for connection to termination resistors Function Ordering Information Order Number LP2994M LP2994MX Package Type SO-8 SO-8 NSC Package Drawing M08A M08A Supplied As 95 Units per Rail 2500 Units Tape and Reel www.national.com 2 LP2994 Absolute Maximum Ratings (Note 1) Operating Range Junction Temp. Range (Note 3) AVIN Supply Voltage PVIN Supply Voltage SD Input Voltage VTT Output Voltage SO-8 Thermal Resistance (θJA) 0˚C to +125˚C 2.2V to 5.5V -0.3V to (AVIN + 0.3V) -0.3V to (AVIN + 0.3V) -0.3V to (PVIN + 0.3V) 151˚C/W If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. PVIN, AVIN, VTT, VDDQ, SD to GND Storage Temp. Range Junction Temperature Lead Temperature (Soldering, 10 sec) ESD Rating (Note 2) −0.3V to +6V −65˚C to +150˚C 150˚C 260˚C 2kV Electrical Characteristics Symbol VTT Parameter VTT Output Voltage IOUT = 0A (Note 5) Quiescent Current Specifications with standard typeface are for TJ = 25˚C and limits in boldface type apply over the full Operating Temperature Range (TJ = 0˚C to +125˚C). Unless otherwise specified, AVIN = PVIN = 2.5V, VDDQ = 2.5V (Note 4). Conditions VIN=VDDQ = 2.3V VIN=VDDQ = 2.5V VIN=VDDQ = 2.7V IOUT = 0A (Note 6) 86 Min 1.108 1.210 1.305 Typ 1.138 1.236 1.334 272 100 21 SD = 0V SD = 2.5V 1.9 0.8 IOUT = 0 to 1.5A IOUT = 0 to −1.5A -0.4 +0.4 100 pA 2 2 45 5 Max 1.168 1.260 1.360 400 µA kΩ µA µA nA V V % V Units Iq ZVDDQ IQSD ISD VIH VIL ∆VTT/VTT ISENSE VDDQ Input Impedance Quiescent current in shutdown Shutdown Leakage Current Minimum Shutdown High Level Maximum Shutdown Low Level Load Regulation (Note 7) SENSE Input Current Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating range indicates conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and test conditions see Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Note 3: At elevated temperatures, devices must be derated based on thermal resistance. The device in the SO-8 package must be derated at θJA = 151.2˚ C/W junction to ambient with no heat sink. Note 4: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 5: VIN is defined as the VIN = AVIN = PVIN Note 6: Quiescent current defined as the current flow into AVIN. Note 7: Load regulation is tested by using a 10ms current pulse and measuring VTT. 3 www.national.com LP2994 Typical Performance Characteristics Iq vs VIN (25˚C) Iq vs VIN (0, 25, and 125˚C) 20045914 20045915 Iq vs Temperature ( VIN = 2.5V) ISD vs VIN (25˚C) 20045916 20045917 ISD vs VIN (0, 25, and 125˚C) ISD vs Temperature ( VIN = 2.5V) 20045918 20045919 www.national.com 4 LP2994 Typical Performance Characteristics VIL and VIHvs AVIN (25˚C) (Continued) Maximum Sourcing Current vs AVIN (VDDQ = 2.5V, PVIN = 1.8V) 20045920 20045921 Maximum Sourcing Current vs AVIN (VDDQ = 2.5V, PVIN = 2.5V) Maximum Sourcing Current vs AVIN (VDDQ = 2.5V, PVIN = 3.3V) 20045922 20045923 Maximum Sinking Current vs AVIN (VDDQ = 2.5V) Maximum Sourcing Current vs AVIN (VDDQ = 1.8V, PVIN = 1.8V) 20045924 20045925 5 www.national.com LP2994 Typical Performance Characteristics Maximum Sinking Current vs AVIN (VDDQ = 1.8V) (Continued) Maximum Sourcing Current vs AVIN (VDDQ = 1.8V, PVIN = 3.3V) 20045926 20045927 VTT vs IOUT (0, 25, 85, and 125˚C) VTT vs IOUT 20045929 20045930 www.national.com 6 LP2994 Block Diagram 20045903 Description The LP2994 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2 and SSTL-3. The output, VTT is capable of sinking and sourcing current while regulating the output voltage equal to VDDQ / 2. The output stage has been designed to maintain excellent load regulation while preventing shoot through. The LP2994 also incorporates two distinct power rails which separates the analog circuitry from the power output stage. This allows a split rail approach to be utilized to decrease internal power dissipation. It also permits the LP2994 to provide a termination solution for the next generation of DDR-SDRAM memory (DDRII). Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission across the memory bus. This termination scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM. The most common form of termination is Class II single parallel termination. This involves one RS series resistor from the chipset to the memory and one RT termination resistor. Typical values for RS and RT are 25 Ohms, although these can be changed to scale the current requirements from the LP2994. This implementation can be seen below in Figure 2. 20045931 FIGURE 2. SSTL Termination Scheme 7 www.national.com LP2994 Pin Descriptions AVIN and PVIN AVIN and PVIN are the input supply pins for the LP2994. AVIN is used to supply all the internal control circuitry. PVIN, however, is used exclusively to provide the rail voltage for the output stage used to create VTT. These pins have the capability to work off separate supplies depending on the application. Higher voltages on PVIN will increase the maximum continuous output current because of output RDSON limitations at voltages close to VTT. The disadvantage of high values of PVIN is that the internal power loss will also increase, thermally limiting the design. For SSTL-2 applications, a good compromise would be to connect the AVIN and PVIN directly together at 2.5V. This eliminates the need for bypassing the two supply pins separately. The only limitation on input voltage selection is that PVIN must be equal to or lower than AVIN. VDDQ VDDQ is the input used to create the internal reference voltage for regulating VTT. The reference voltage is generated from a resistor divider of two internal 50kΩ resistors. This guarantees that VTT will track VDDQ / 2 precisely. The optimal implementation of VDDQ is as a remote sense. This can be achieved by connecting VDDQ directly to the 2.5V rail at the DIMM instead of AVIN and PVIN. This ensures that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from the power lines. For SSTL-2 applications VDDQ will be a 2.5V signal, which will create a 1.25V termination voltage at VTT (See Electrical Characteristics Table for exact values of VTT over temperature). VSENSE The purpose of the sense pin is to provide improved remote load regulation. In most motherboard applications the termination resistors will connect to VTT in a long plane. If the output voltage was regulated only at the output of the LP2994 then the long trace will cause a significant IR drop resulting in a termination voltage lower at one end of the bus than the other. The VSENSE pin can be used to improve this performance, by connecting it to the middle of the bus. This will provide a better distribution across the entire termination bus. If remote load regulation is not used then the VSENSE pin must still be connected to VTT. Care should be taken when a long VSENSE trace is implemented in close proximity to the memory. Noise pickup in the VSENSE trace can cause problems with precise regulation of VTT. A small 0.1uF ceramic capacitor placed next to the VSENSE pin can help filter any high frequency signals and preventing errors. Shutdown The LP2994 contains an active low shutdown pin that can be used to tri-state VTT. During shutdown VTT should not be exposed to voltages that exceed PVIN. With the shutdown pin asserted low the quiescent current of the LP2994 will drop, however, VDDQ will always maintain its constant impedance of 100kΩ for generating the internal reference. Therefore to calculate the total power loss in shutdown both currents need to be considered. For more information refer to the Thermal Dissipation section. The shutdown pin also has an internal pull-up current, therefore to turn the part on the shutdown pin can either be connected to AVIN or left open. VTT VTT is the regulated output that is used to terminate the bus resistors. It is capable of sinking and sourcing current while regulating the output precisely to VDDQ / 2. The LP2994 is designed to handle peak transient currents of up to +/- 3A with excellent load regulation. The maximum continuous current is a function of AVIN and PVIN and several curves can be seen in the Typical Performance Characteristics section. If a transient is expected to last above the maximum continuous current rating for a significant amount of time, then the bulk output capacitor should be sized large enough to prevent an excessive voltage drop. Despite the fact that the LP2994 is designed to handle large transient output currents it is not capable of handling these for long durations under all conditions. The reason for this is that the SO-8 package is not able to thermally dissipate an infinite amount of heat as a result of internal power loss. If large currents are required for longer durations, then care should be taken to ensure that the maximum junction temperature is not exceeded. Proper thermal de-rating should always be used (Please refer to the Thermal Dissipation section). Component Selection Input Capacitor The LP2994 does not require a capacitor for input stability, but it is recommended for improved performance during large load transients to prevent the input rail from dropping. The input capacitor should be located as close as possible to the PVIN pin. Several recommendations exist dependent on the application required. A typical value recommended for AL electrolytic capacitors is 47uF. Ceramic capacitors can also be used, a value in the range of 10uF with X5R dielectric or better would be an ideal choice. The input capacitance can be reduced if the LP2994 is placed close to the bulk capacitance from the output of the 2.5V DC-DC converter. If the two supply rails (AVIN and PVIN) are separated then the 47uF capacitor should be placed as close to possible to the PVIN rail. An additional 0.1uF ceramic capacitor can be placed on the AVIN rail to prevent excessive noise from coupling into the device. Output Capacitor The LP2994 has been designed to be insensitive of output capacitor size or ESR (Equivalent Series Resistance). This allows the flexibility to use any capacitor desired. The choice for output capacitor will be determined solely on the application and the requirements for load transient response of VTT. As a general recommendation, the output capacitor should be sized above 100uF with a low ESR for SSTL applications with DDR-SDRAM. The value of ESR should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. Several capacitor options are available on the market and a few of these are highlighted below: AL - It should be noted that many aluminum electrolytics only specify impedance at a frequency of 120Hz, which indicates they have poor high frequency performance. Only aluminum electrolytics that have an impedance specified at a higher frequency (approximately 100kHz) should be used for the LP2994. To improve the ESR several AL electrolytics can be combined in parallel for an overall reduction. An important note to be aware of is the extent at which the ESR will change over temperature. Aluminum electrolytic capacitors can have their ESR rapidly increase at cold temperatures. Ceramic - Ceramic capacitors typically have a low capacitance, in the range of 10 to 100uF range, but they have excellent AC performance for bypassing noise because of very low ESR (typically less than 10mOhm). However, some 8 www.national.com LP2994 Component Selection (Continued) dielectric types have poor capacitance characteristics as a function of voltage and temperature. Because of the typically low value of capacitance it is recommended to use ceramic capacitors in parallel with another capacitor such as an aluminum electrolytic. A dielectric of X5R or better is recommended for all ceramic capacitors. Hybrid - Several hybrid capacitors such as OS-CON and SP are available from several manufacturers. These offer a large capacitance while maintaining a low ESR. These are the best solution when size and performance are critical, although their cost is typically higher than other capacitors. Thermal Dissipation Since the LP2994 is a linear regulator any current flow from VTT will result in internal power dissipation generating heat. To prevent damaging the part from exceeding the maximum allowable junction temperature, care should be taken to derate the part dependent on the maximum expected ambient temperature and power dissipation. The maximum allowable internal temperature rise (TRmax) can be calculated given the maximum ambient temperature (TAmax) of the application and the maximum allowable junction temperature (TJmax). TRmax = TJmax − TAmax From this equation, the maximum power dissipation (PD) of the part can be calculated: PDmax = TRmax / θJA The θJA of the LP2994 will be dependent on several variables: the package used; the thickness of copper; the number of vias and the airflow. For instance, the θJA of the SO-8 is 163˚C/W with the package mounted to a standard 8x4 2-layer board with 1oz. copper, no airflow, and 0.5W dissipation at room temperature. This value can be reduced to 151.2˚C/W by changing to a 3x4 board with 2 oz. copper that is the JEDEC standard. Figure 3 shows how the θJA varies with airflow for the two boards mentioned. 20045928 FIGURE 3. θJA vs Airflow Additional improvements can be made by the judicious use of vias to connect the part and dissipate heat to an internal ground plane. Using larger traces and more copper on the top side of the board can also help. With careful layout, it is possible to reduce the θJA further than the nominal values shown in Figure 3. Optimizing the θJA and placing the LP2994 in a section of a board exposed to lower ambient temperature allows the part to operate with higher power dissipation. The internal power dissipation can be calculated by summing the three main sources of loss: output current at VTT, either sinking or sourcing, and quiescent current at AVIN and VDDQ. During the active state (when Shutdown is not held low) the total internal power dissipation can be calculated from the following equations: PD = PAVIN + PVDDQ + PVTT where, PAVIN = IAVIN x VAVIN PVDDQ = VVDDQ x IVDDQ = VVDDQ2 x RVDDQ To calculate the maximum power dissipation at VTT, both sinking and sourcing current conditions at VTT need to be examined. Although only one equation will add into the total, VTT cannot source and sink current simultaneously. PVTT = VVTT x ILOAD (Sinking) or PVTT = ( VPVIN - VVTT) x ILOAD (Sourcing) The power dissipation of the LP2994 can also be calculated during the shutdown state. During this condition the output VTT will tri-state, therefore that term in the power equation will disappear as it cannot sink or source any current (leakage is negligible). The only losses during shutdown will be the reduced quiescent current at AVIN and the constant impedance that is seen at the VDDQ pin. PD = PAVIN + PVDDQ Where, PAVIN = IAVIN x VAVIN PVDDQ = VVDDQ x IVDDQ = VVDDQ2 x RVDDQ 9 www.national.com LP2994 Typical Application Circuits Several different application circuits have been shown in Figure 4 through Figure 13 to illustrate some of the options that are possible in configuring the LP2994. Graphs of the individual circuit performance can be found in the Typical Performance Characteristics section in the beginning of the datasheet. These curves illustrate how the maximum output current is affected by changes in AVIN and PVIN. SSTL-2 Applications For the majority of applications that implement the SSTL-2 termination scheme, it is recommended to connect all the input rails to the 2.5V rail. This provides an optimal trade-off between power dissipation and component count and selection. An example of this circuit can be seen in Figure 4. 20045904 FIGURE 4. Recommended SSTL-2 Implementation If power dissipation or efficiency is a major concern then the LP2994 has the ability to operate on split power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog circuitry (AVIN) can be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power dissipation to be lowered when sourcing current from VTT. The disadvantage of this circuit is that the maximum continuous current is reduced because of the lower rail voltage, although it is adequate for all motherboard SSTL-2 applications. Increasing the output capacitance can also help if periods of large load transients will be encountered. 20045905 FIGURE 5. Lower Power Dissipation SSTL-2 Implementation The third option for SSTL-2 applications in the situation that a 1.8V rail is not available and it is not desirable to use 2.5V, is to connect the LP2994 power rail to 3.3V. In this situation AVIN will be limited to operation on the 3.3V or 5V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the maximum continuous output current at the downside of higher thermal dissipation. Care should be taken to prevent the LP2994 from experiencing large current levels which cause the junction temperature to exceed the maximum. Because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3V rail. www.national.com 10 LP2994 Typical Application Circuits (Continued) 20045906 FIGURE 6. SSTL-2 Implementation with higher voltage rails DDR-II Applications With the separate VDDQ pin and an internal resistor divider it is possible to use the LP2994 in applications utilizing DDR-II memory. Figure 7 and Figure 8 show several implementations of recommended circuits with output curves displayed in the Typical Performance Characteristics. Figure 7 shows the recommended circuit configuration for DDR-II applications. The output stage is connected to the 1.8V rail and the AVIN pin can be connected to either a 3.3V or 5V rail. 20045907 FIGURE 7. Recommended DDR-II Termination If it is not desirable to use the 1.8V rail it is possible to connect the output stage to a 3.3V rail. Care should be taken to not exceed the maximum junction temperature as the thermal dissipation increases with lower VTT output voltages. For this reason, it is not recommended to power PVIN off a rail higher than the nominal 3.3V. The advantage of this configuration is that it has the ability to source and sink a higher maximum continuous current. 20045908 FIGURE 8. DDR-II Termination with higher voltage rails If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different scaling factor than 0.5 times VDDQ for regulating the output voltage. Several options are available to scale the output to any voltage 11 required. One method is to level shift the output by using feedback resistors from VTT to the VSENSE pin. This has been illustrated in Figure 9 and Figure 10. Figure 9 shows www.national.com LP2994 Typical Application Circuits (Continued) how to use two resistors to level shift VTT above the internal reference voltage of VDDQ/2. To calculate the exact voltage at VTT the following equation can be used. VTT = (VDDQ/2) x ( 1 + R1/R2) 20045909 FIGURE 9. Increasing VTT by Level Shifting Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than the internal reference voltage of VDDQ/2. The equations relating VTT and the resistors can be seen below: VTT = (VDDQ/2) x ( 1 - R1/R2) 20045910 FIGURE 10. Decreasing VTT by Level Shifting Reference Voltage DDR-SDRAM and the motherboard chipsets usually require a reference voltage which tracks VTT. To implement this feature in most applications it is advisable to use two equal resistors as a resistor divider. This prevents long VREF traces from running across the motherboard picking up noise which can interfere with performance. However, in a few applications it may be desirable to use the VTT output on the LP2994 to generate the VREF signal. The can be accomplished by using an RC filter on the output of VTT to create a VREF signal. Typically, the reference voltage required by chipsets and memory is well under 1µA combined, therefore, a fairly large resistor such as 1kΩ or larger can be used. A recommended capacitor would be a 1uF X7R ceramic capacitor. www.national.com 12 LP2994 Typical Application Circuits (Continued) 20045911 FIGURE 11. Creating a Reference Voltage for Memory and Chipsets Output Capacitor Selection For applications utilizing the LP2994 to terminate SSTL-2 I/O signals the typical application circuit shown in Figure 12 can be implemented. 20045912 FIGURE 12. Typical SSTL-2 Application Circuit This circuit permits termination in a minimum amount of board space and component count. Capacitor selection can be varied depending on the number of lines terminated and the maximum load transient. However, with motherboards and other applications where VTT is distributed across a long plane it is advisable to use multiple bulk capacitors and addition to high frequency decoupling. Figure 13 shown below depicts an example circuit where 2 bulk output capacitors could be situated at both ends of the VTT plane for optimal placement. Large aluminum electrolytic capacitors are used for their low ESR and low cost. 20045913 FIGURE 13. Typical SSTL-2 Application Circuit for Motherboards In most PC applications an extensive amount of decoupling is required because of the long interconnects encountered 13 www.national.com LP2994 Typical Application Circuits (Continued) with the DDR-SDRAM DIMMs mounted on modules. As a result bulk aluminum electrolytic capacitors in the range of 1000uF are typically used. 4. For improved thermal performance excessive top side copper should be used to dissipate heat from the package. Numerous vias from the ground connection to the internal ground plane will help. Additionally these can be located underneath the package if manufacturing standards permit. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A 0.1uF ceramic capacitor located close to the VSENSE can also be used to filter any unwanted high frequency signal. This can be an issue especially if long VSENSE traces are used. 5. PCB Layout Considerations 1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin. 2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For motherboard applications an ideal location would be at the center of the termination bus. 3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides the most accurate point for creating the reference voltage. www.national.com 14 LP2994 DDR Termination Regulator Physical Dimensions unless otherwise noted inches (millimeters) 8-Lead Small Outline Package (M8) NS Package Number M08 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.