LP38511-ADJ

LP38511-ADJ 800mA Fast-Transient Response Adjustable Low-Dropout Linear Voltage Regulator February 12, 2009 LP38511-ADJ 800mA Fast-Transient Response Adjustable Low-Dropout Linear Voltage Regulator General Description The LP38511-ADJ Fast-Transient Response Low-Dropout Voltage Regulator offers the highest-performance in meeting AC and DC accuracy requirements for powering Digital Cores. The LP38511-ADJ uses a proprietary control loop that enables extremely fast response to change in line conditions and load demands. Output Voltage DC accuracy is guaranteed at 2.5% over line, load and full temperature range from -40°C to +125°C. The LP38511-ADJ is designed for inputs from the 2.5V, 3.3V, and 5.0V rail, is stable with 10 uF ceramic capacitors, and has an adjustable output voltage. The LP38511-ADJ provides excellent transient performance to meet the demand of high performance digital core ASICs, DSPs, and FPGAs found in highly-intensive applications such as servers, routers/switches, and base stations. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 2.25V to 5.5V Input Voltage Range Adjustable Output Voltage Range of 0.5V to 3.3V 800mA Output Load Current ±2.0% Accuracy over Line, Load, and Full-Temperature Range from -40°C to +125°C Stable with tiny 10 uF ceramic capacitors Enable pin Typically less than 1uA of Ground pin current with Enable pin low 25dB of PSRR at 100 kHz Over-Temperature and Over-Current Protection PSOP-8 and TO-263 THIN Surface Mount Packages Applications ■ ■ ■ ■ ■ ■ Digital Core ASICs, FPGAs, and DSPs Servers Routers and Switches Base Stations Storage Area Networks DDR2 Memory Typical Application Circuit 30040801 © 2009 National Semiconductor Corporation 300408 www.national.com LP38511-ADJ Ordering Information Output Voltage ADJ Order Number LP38511MR-ADJ LP38511MRX-ADJ LP38511TJ-ADJ Package Type PSOP-8 PSOP-8 TO-263 THIN Package Marking LP38511MR-ADJ LP38511MR-ADJ LP38511TJ-ADJ Supplied As Rail Tape and Reel Tape and Reel Connection Diagrams 30040805 Top View TO-263 THIN Package 30040806 Top View PSOP 8 Pin Package Pin Descriptions for TO-263 THIN (TJ) Package Pin # 1 2 3 4 5 Pin Name EN IN GND OUT ADJ Function Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and must be tied to the input voltage, or actively driven. Input Supply Pin. Ground Regulated Output Voltage Pin. The feedback to the internal Error Amplifier to set the output voltage. The Thin TO-263 DAP is used as a thermal connection to remove heat from the device to an external heat-sink in the form of the copper area on the printed circuit board. The DAP is physically connected to backside of the die. The DAP is internally connected to device ground. The DAP should be soldered to the Ground Plane copper. DAP DAP Pin Descriptions for PSOP-8 (MR) Package Pin # 1, 2 3 4 5 6 7, 8 Pin Name OUT ADJ N/C GND EN IN Function Regulated Output Voltage Pins. Pins 1 and 2 share current and must be connected together. The feedback to the internal Error Amplifier to set the output voltage. No internal connection Ground Enable. Pull high to enable the output, low to disable the output. This pin has no internal bias and must be tied to the input voltage, or actively driven. Input Supply Pin. Pins 7 and 8 share current and must be connected together. The PSOP-8 DAP is used as a thermal connection to remove heat from the device to an external heat-sink in the form of the copper area on the printed circuit board. The DAP is physically connected to backside of the die, but is not internally connected to device ground. The DAP should be soldered to the Ground Plane copper. DAP DAP www.national.com 2 LP38511-ADJ Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range Soldering Temperature (Note 3) Thin TO-263 PSOP-8 ESD Rating (Note 2) Power Dissipation (Note 4) Input Pin Voltage (Survival) Enable Pin Voltage (Survival) Output Pin Voltage (Survival) ADJ Pin Voltage (Survival) IOUT (Survival) −65°C to +150°C 260°C, 10s 260°C, 10s ±2 kV Internally Limited -0.3V to +6.0V -0.3V to +6.0V -0.3V to +6.0V -0.3V to +6.0V Internally Limited Operating Ratings Input Supply Voltage, VIN Output Voltage, VOUT Enable Input Voltage, VEN Output Current (DC) Junction Temperature (Note 4) (Note 1) 2.25V to 5.5V VADJ to 5V 0.0V to 5.5V 1 mA to 800 mA −40°C to +125°C Electrical Characteristics Unless otherwise specified: VIN= 2.50V, VOUT= VADJ, IOUT= 10 mA, CIN= 10 µF, COUT= 10 µF, VEN= 2.0V. Limits in standard type are for TJ= 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Symbol VADJ IADJ ΔVADJ/ΔVIN ΔVADJ/ΔIOUT VDO Parameter VADJ Accuracy (Note 7) ADJ Pin Bias Current VADJ Line Regulation (Notes 5, 7) VADJ Load Regulation (Notes 6, 7) Dropout Voltage (Note 8) Ground Pin Current, Output Enabled Ground Pin Current, Output Disabled ISC Enable Input VEN(ON) VEN(OFF) VEN(HYS) IEN td(OFF) td(ON) Enable ON Voltage Threshold Enable OFF Voltage Threshold Enable Voltage Hysteresis Enable Pin Current Turn-off delay Turn-on delay VEN rising from VEN(ON) to VOUT = ON, ILOAD = 800 mA 0.90 0.80 0.60 0.50 1.20 1.00 200 1 -1 1 25 1.50 1.60 1.40 1.50 µs V V mV nA Short Circuit Current Conditions 2.25V ≤ VIN ≤ 5.5V 2.25V ≤ VIN ≤ 5.5V 2.25V ≤ VIN ≤ 5.5V 10 mA ≤ IOUT ≤ 800 mA IOUT = 800 mA IOUT = 10 mA IOUT = 800 mA VEN = 0.50V VOUT = 0V 10 mA ≤ IOUT ≤ 800 mA Min 495.0 490.0 Typ 500. 1 0.03 0.06 0.10 0.20 7.5 9 0.1 1.5 Max 505.0 510.0 260 11 12 11 13 3.5 12 Units mV nA %/V %/A mV mA IGND µA A 3 www.national.com LP38511-ADJ Symbol AC Parameters Parameter VIN = 2.5V f = 120Hz VIN = 2.5V f = 1 kHz f = 120Hz Conditions Min Typ Max Units - 73 70 0.4 25 165 10 168 67 11 2 dB °C/W µV/√Hz µVRMS PSRR Ripple Rejection ρn(l/f) en TSD ΔTSD θJ-A θJ-C Output Noise Density Output Noise Voltage Thermal Shutdown Thermal Resistance Junction to Ambient (Note 4) Thermal Resistance Junction to Case BW = 10Hz - 100kHz TJ rising PSOP-8 TO-263 THIN PSOP-8 TO-263 THIN Thermal Characteristics Thermal Shutdown Hysteresis TJ falling from TSD °C °C/W Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22-A114. Note 3: Refer to JEDEC J-STD-020C for surface mount device (SMD) package reflow profiles and conditions. Unless otherwise stated, the temperatures and times are for Sn-Pb (STD) only. Note 4: Device operation must be evaluated, and derated as needed, based on ambient temperature (TA), power dissipation (PD), maximum allowable operating junction temperature (TJ(MAX)), and package thermal resistance (θJA). The typical θJA ratings given are worst case based on minimum land area on two-layer PCB (EIA/JESD51-3). See POWER DISSIPATION/HEAT-SINKING for details. Note 5: Line regulation is defined as the change in VADJ from the nominal value due to change in the voltage at the input. Note 6: Load regulation is defined as the change in VADJ from the nominal value due to change in the load current at the output. Note 7: The line and load regulation specification contains only the typical number. However, the limits for line and load regulation are included in the output voltage tolerance specification. Note 8: Dropout voltage (VDO) is typically defined as the input to output voltage differential (VIN - VOUT) where the input voltage is low enough to cause the output voltage to drop 2%. For the LP38511-ADJ, the minimum operating voltage of 2.25V is the limiting factor when the programed output voltage is less than typically 1.80V. www.national.com 4 LP38511-ADJ Typical Performance Characteristics VEN = 2.0V, CIN = 10 µF, COUT = 10 µF, IOUT = 10 mA. VADJ vs Temperature Unless otherwise specified: TJ = 25°C, VIN = 2.50V, VOUT= VADJ, VOUT vs VIN 30040811 30040815 Ground Pin Current (IGND) vs VIN Ground Pin Current (IGND) vs Temperature 30040812 30040813 Ground Pin Current (IGND) vs Temperature Enable Threshold vs Temperature 30040814 30040816 5 www.national.com LP38511-ADJ VOUT vs VEN Load regulation vs Temperature 30040832 30040820 Line Regulation vs Temperature Current Limit vs Temperature 30040821 30040822 Load Transient, 10 mA to 800 mA VOUT = VADJ, COUT = 10 μF Ceramic Load Transient, 10 mA to 800 mA VOUT = 1.20V, COUT = 10 μF Ceramic 30040823 30040824 www.national.com 6 LP38511-ADJ Load Transient, 250 mA to 800 mA VOUT = 1.20V, COUT = 10 μF Ceramic Line Transient VOUT = VADJ, COUT = 10 μF Ceramic 30040825 30040826 Line Transient VOUT = 1.20V, COUT = 10 μF Ceramic PSRR, IOUT = 100 mA VOUT = VADJ, COUT = 10 μF Ceramic 30040827 30040829 PSRR, IOUT = 800 mA VOUT = VADJ, COUT = 10μF Ceramic Output Noise Density VOUT = VADJ, COUT = 10 μF Ceramic 30040830 30040831 7 www.national.com LP38511-ADJ Block Diagram 30040807 Application Information EXTERNAL CAPACITORS Like any low-dropout regulator, external capacitors are required to assure stability. These capacitors must be correctly selected for proper performance. Input Capacitor A ceramic input capacitor of at least 10 µF is required. For general usage across all load currents and operating conditions, a 10 µF ceramic input capacitor will provide satisfactory performance. Output Capacitor A ceramic capacitor with a minimum value of 10 µF is required at the output pin for loop stability. It must be located less than 1 cm from the device and connected directly to the output and ground pin using traces which have no other currents flowing through them. As long as the minimum of 10 µF ceramic is met, there is no limitation on any additional capacitance. X7R and X5R dielectric ceramic capacitors are strongly recommended, as they typically maintain a capacitance range within ±20% of nominal over full operating ratings of temperature and voltage. Of course, they are typically larger and more costly than Z5U/Y5U types for a given voltage and capacitance. Z5U and Y5V dielectric ceramics are not recommended as the capacitance will drop severely with applied voltage. A typical Z5U or Y5V capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. The Z5U and Y5V also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. REVERSE VOLTAGE A reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. Typically this will happen when VIN is abruptly taken low and COUT continues to hold a sufficient charge such that the input to output voltage becomes reversed. A less common condition is when an alternate voltage source is connected to the output. There are two possible paths for current to flow from the output pin back to the input during a reverse voltage condition. While VIN is high enough to keep the control circuity alive, and the Enable pin is above the VEN(ON) threshold, the control circuitry will attempt to regulate the output voltage. Since the input voltage is less than the programmed output voltage, the control circuit will drive the gate of the pass element to the full on condition when the output voltage begins to fall. In this condition, reverse current will flow from the output pin to the input pin, limited only by the RDS(ON) of the pass element and the output to input voltage differential. Discharging an output capacitor up to 1000 µF in this manner will not damage the device as the current will rapidly decay. However, continuous reverse current should be avoided. When the Enable is low this condition will be prevented. The internal PFET pass element in the LP38511-ADJ has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output voltage to input voltage differential is more than 500 mV (typical) the parasitic diode becomes forward biased and current flows from the output pin to the input pin through the diode. The current in the parasitic diode should be limited to less than 1A continuous and 5A peak. If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground. A Schottky diode is recommended for this protective clamp. SHORT-CIRCUIT PROTECTION The LP38511-ADJ is short circuit protected, and in the event of a peak over-current condition the short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation 8 www.national.com LP38511-ADJ causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the POWER DISSIPATION/HEAT-SINKING section for power dissipation calculations. SETTING THE OUTPUT VOLTAGE The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the formula: VOUT = VADJ x (1 + (R1/R2)) (1) on this compensation technique alone is adequate only for higher output voltages. Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10% capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give similar results. TABLE 1. VOUT 0.80V 1.00V 1.20V 1.50V 1.80V 2.00V 2.50V 3.00V 3.30V R1 1.07 kΩ 1.00 kΩ 1.40 kΩ 2.00 kΩ 2.94 kΩ 1.02 kΩ 1.02 kΩ 1.00 kΩ 2.00 kΩ R2 1.78 kΩ 1.00 kΩ 1.00 kΩ 1.00 kΩ 1.13 kΩ 340Ω 255Ω 200Ω 357Ω CFF 4700 pF 4700 pF 3300 pF 2700 pF 1500 pF 4700 pF 4700 pF 4700 pF 2700 pF FZ 31.6 kHz 33.8 kHz 34.4 kHz 29.5 kHz 36.1 kHz 33.2 kHz 33.2 kHz 33.8 kHz 29.5 kHz The resistors used for R1 and R2 should be high quality, tight tolerance, and with matching temperature coefficients. It is important to remember that, although the value of VADJ is guaranteed, the final value of VOUT is not. The use of low quality resistors for R1 and R2 can easily produce a VOUT value that is unacceptable. It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 1.00 kΩ. This is to reduce the possibility of any internal parasitic capacitances on the ADJ pin from creating an undesirable phase shift that may interfere with device stability. ( (R1 x R2) / (R1 + R2) ) ≤ 1.00 kΩ (2) Please refer to Application Note AN-1378 Method For Calculating Output Voltage Tolerances in Adjustable Regulators for additional information on how resistor tolerances affect the calculated VOUT value. ENABLE OPERATION The Enable ON threshold is typically 1.2V, and the OFF threshold is typically 1.0V. To ensure reliable operation the Enable pin voltage must rise above the maximum VEN(ON) threshold and must fall below the minimum VEN(OFF) threshold. The Enable threshold has typically 200 mV of hysteresis to improve noise immunity. The Enable pin (EN) has no internal pull-up or pull-down to establish a default condition and, as a result, this pin must be terminated either actively or passively. If the Enable pin is driven from a single ended device (such as the collector of a discrete transistor) a pull-up resistor to VIN, or a pull-down resistor to ground, will be required for proper operation. A 1 kΩ to 100 kΩ resistor can be used as the pull-up or pull-down resistor to establish default condition for the EN pin. The resistor value selected should be appropriate to swamp out any leakage in the external single ended device, as well as any stray capacitance. If the Enable pin is driven from a source that actively pulls high and low (such as a CMOS rail to rail comparator output), the pull-up, or pull-down, resistor is not required. If the application does not require the Enable function, the pin should be connected directly to the adjacent VIN pin. POWER DISSIPATION/HEAT-SINKING A heat-sink may be required depending on the maximum power dissipation (PD(MAX)), maximum ambient temperature (TA(MAX))of the application, and the thermal resistance (θJA) of the package. Under all possible conditions, the junction temperature (TJ) must be within the range specified in the Operating Ratings. The total power dissipation of the device is given by: PD = ( (VIN−VOUT) x IOUT) + ((VIN) x IGND) (7) FEED FORWARD CAPACITOR, CFF When using a ceramic capacitor for COUT, the typical ESR value will be too small to provide any meaningful positive phase compensation, FZ, to offset the internal negative phase shifts in the gain loop. FZ = 1 / (2 x π x COUT x ESR) (3) A capacitor placed across the gain resistor R1 will provide additional phase margin to improve load transient response of the device. This capacitor, CFF, in parallel with R1, will form a zero in the loop response given by the formula: FZ = 1 / (2 x π x CFF x R1) (4) For optimum load transient response select CFF so the zero frequency, FZ, falls between 20 kHz and 40 kHz. CFF = 1 / (2 x π x R1 x FZ) (5) The phase lead provided by CFF diminishes as the DC gain approaches unity, or VOUT approaches VADJ. This is because CFF also forms a pole with a frequency of: FP = 1 / (2 x π x CFF x (R1 || R2) ) (6) It's important to note that at higher output voltages, where R1 is much larger than R2, the pole and zero are far apart in frequency. At lower output voltages the frequency of the pole and the zero mover closer together. The phase lead provided from CFF diminishes quickly as the output voltage is reduced, and has no effect when VOUT = VADJ. For this reason, relying where IGND is the operating ground current of the device (specified under Electrical Characteristics). 9 www.national.com LP38511-ADJ The maximum allowable junction temperature rise (ΔTJ) depends on the maximum expected ambient temperature (TA (MAX)) of the application, and the maximum allowable junction temperature (TJ(MAX)): ΔTJ = TJ(MAX) − TA(MAX) (8) The maximum allowable value for junction to ambient Thermal Resistance, θJA, can be calculated using the formula: θJA = ΔTJ / PD(MAX) (9) LP38511-ADJ is available in TO-263 THIN and PSOP-8 surface mount packages. For a comparison of the TO-263 THIN package to the standard TO-263 package see Application Note AN-1797 TO-263 THIN Package. The thermal resistance depends on amount of copper area, or heat sink, and on air flow. See Application Note AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages for guidelines. Heat-Sinking the TO-263 THIN (TJ) Package The DAP of the TO-263 THIN package is soldered to the copper plane for heat sinking. The TO-263 THIN package has a θJA rating of 67°C/W, and a θJC rating of 2°C/W. The θJA rating of 67°C/W includes the device DAP soldered to an area of 0.055 square inches (0.22 in x 0.25 in) of 1 ounce copper on a two sided PCB, with no airflow. See JEDEC standard EIA/ JESD51-3 for more information. Figure 1 shows a curve for the θJA of TO-263 THIN package for different thermal via counts under the exposed DAP, using a four layer PCB for heat sinking. The thermal vias connect the copper area directly under the exposed DAP to the first internal copper plane only. See JEDEC standards EIA/ JESD51-5 and EIA/JESD51-7 for more information. 30040836 FIGURE 2. θJA vs Copper Area for the TO-263 THIN Package Heat-Sinking The PSOP-8 Package The DAP of the PSOP-8 package is soldered to the copper plane for heat sinking. The LP38511MR package has a θJA rating of 168°C/W, and a θJC rating of 11°C/W. The θJA rating of 168°C/W includes the device DAP soldered to an area of 0.008 square inches (0.09 in x 0.09 in) of 1 ounce copper on a two sided PCB, with no airflow. See JEDEC standard EIA/ JESD51-3 for more information. Figure 3 shows a curve for different thermal via counts under the exposed DAP, using a four layer PCB for heat sinking. The thermal vias connect the copper area directly under the exposed DAP to the first internal copper plane only. See JEDEC standards EIA/JESD51-5 and EIA/JESD51-7 for more information. 30040837 30040835 FIGURE 1. θJA vs Thermal Via Count for the TO-263 THIN Package on 4–Layer PCB Figure 2 shows the thermal performance when the TO-263 THIN is mounted to a two layer PCB where the copper area is predominately directly under the exposed DAP. As shown in the figure, increasing the copper area beyond 1 square inch produces very little improvement. FIGURE 3. θJA vs Thermal Via Count for the PSOP-8 Package on 4–Layer PCB Figure 4 shows thermal performance for a two layer board using thermal vias to a copper area on the bottom of the PCB. The copper area on the top of the PCB, which is soldered to the exposed DAP, is 0.10in x 0.20in, which is approximately the same dimensions as the body of the PSOP-8 package. The copper area on the bottom of the PCB is a square area and is centered directly under the PSOP-8 package. 10 www.national.com LP38511-ADJ Increasing the copper area soldered to the DAP to 1 square inch of 1 ounce copper, using a dog-bone type layout, will produce a typical θJA rating of 98°C/W. 30040839 FIGURE 4. θJA vs Thermal Via Count for the PSOP-8 Package on 2–Layer PCB with Copper Area on BottomSide Figure 5 shows thermal performance for a two layer board with the DAP soldered to copper area on the of the PCB only. 30040838 FIGURE 5. θJA vs Copper Area for the PSOP-8 Package on 2–Layer PCB with Copper Area on Top-Side 11 www.national.com LP38511-ADJ Physical Dimensions inches (millimeters) unless otherwise noted TO-263 THIN, 5 Lead, Molded, 1.7mm Pitch, Surface Mount NS Package Number TJ5A PSOP, 8 Lead, Molded, 0.050in Pitch, Surface Mount NS Package Number MRA08A www.national.com 12 LP38511-ADJ Notes 13 www.national.com LP38511-ADJ 800mA Fast-Transient Response Adjustable Low-Dropout Linear Voltage Regulator Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/AU Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero SolarMagic™ Analog University® THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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