LP38841MR-ADJ

LP38841-ADJ 0.8A Ultra Low Dropout Linear Regulators Stable with Ceramic Output Capacitors December 2006 LP38841-ADJ 0.8A Ultra Low Dropout Adjustable Linear Regulators Stable with Ceramic Output Capacitors General Description The LP38841-ADJ is a high current, fast response regulator which can maintain output voltage regulation with minimum input to output voltage drop. Fabricated on a CMOS process, the device operates from two input voltages: Vbias provides voltage to drive the gate of the N-MOS power transistor, while Vin is the input voltage which supplies power to the load. The use of an external bias rail allows the part to operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability. The fast transient response of these devices makes them suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The parts are available in the PSOP package. Dropout Voltage: 75 mV (typ) @ 0.8A load current. Quiescent Current: 30 mA (typ) at full load. Shutdown Current: 30 nA (typ) when S/D pin is low. Precision Reference Voltage: 1.5% room temperature accuracy. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Ideal for conversion from 1.8V or 1.5V inputs Designed for use with low ESR ceramic capacitors Ultra low dropout voltage (75mV @ 0.8A typ) 0.56V to 1.5V adjustable output range Load regulation of 0.1%/A (typ) 30nA quiescent current in shutdown (typ) Low ground pin current at all loads Over temperature/over current protection Available in 8 lead PSOP package −40°C to +125°C junction temperature range UVLO disables output when VBIAS < 3.8V Applications ■ ASIC Power Supplies In: - Desktops, Notebooks, and Graphics Cards, Servers - Gaming Set Top Boxes, Printers and Copiers ■ Server Core and I/O Supplies ■ DSP and FPGA Power Supplies ■ SMPS Post-Regulators Typical Application Circuit 20117701 * Minimum value required if Tantalum capacitor is used (see Application Hints). © 2007 National Semiconductor Corporation 201177 www.national.com LP38841-ADJ Connection Diagram 20117735 PSOP-8, Top View Pin Description Pin Number 1 2 3 4, 5 6 Pin Name ADJ OUTPUT BIAS GND SHUTDOWN Pin Description The Adjust pin is used to set the regulated output voltage by connecting it to the external resistors R1 and R2 (see Typical Application Circuit). The regulated output voltage is connected to this pin. The Bias pin is used to provide the low current bias voltage to the chip which operates the internal circuitry and provides drive voltage for the N-FET. These are the power and analog grounds for the IC. Connect both pins to ground. This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if this function is not used. The high current input voltage which is regulated down to the nominal output voltage must be connected to this pin. Because the bias voltage to operate the chip is provided separately, the input voltage can be as low as a few hundred millivolts above the output voltage. This pin is floating, it has no internal connection. The PSOP DAP is a thermal connection that is physically connected to the backside of the die, and is used as a thermal connection to the PC Board copper. The DAP is not a ground pin connection, but should be connected to ground potential. 7 INPUT 8 DAP N/C DAP Ordering Information Order Number LP38841MR-ADJ LP38841MRX-ADJ Package Type PSOP-8 PSOP-8 Package Drawing MRA08A MRA08A Supplied As 95 Units Tape and Reel 2500 Units Tape and Reel Block Diagram 20117724 www.national.com 2 LP38841-ADJ Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Range Lead Temp. (Soldering, 5 seconds) ESD Rating Human Body Model (Note 3) Machine Model (Note 9) Power Dissipation (Note 2) VIN Supply Voltage (Survival) VBIAS Supply Voltage (Survival) Shutdown Input Voltage (Survival) VADJ −65°C to +150°C 260°C 2 kV 200V Internally Limited −0.3V to +6V −0.3V to +7V −0.3V to +7V -0.3V to +6V IOUT (Survival) Output Voltage (Survival) Junction Temperature Internally Limited −0.3V to +6V −40°C to +150°C Operating Ratings VIN Supply Voltage Shutdown Input Voltage IOUT Operating Junction Temperature Range VBIAS Supply Voltage VOUT (VOUT + VDO) to 5.5V 0 to +5.5V 0.8A −40°C to +125°C 4.5V to 5.5V 0.56V to 1.5V Limits in standard typeface are for TJ = 25°C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = VO(NOM) + 1V, VBIAS = 4.5V, IL = 10 mA, CIN = 10 µF CER, COUT = 22 µF CER, VS/D = VBIAS. Min/Max limits are guaranteed through testing, statistical correlation, or design. Symbol VADJ Parameter Adjust Pin Voltage Conditions 10 mA < IL < 0.8A MIN 0.552 0.543 TYP (Note 4) 0.56 MAX 0.568 0.577 Units Electrical Characteristics VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 5.5V Adjust Pin Bias Current 10 mA < IL < 0.8A V IADJ VO(NOM) + 1V ≤ VIN ≤ 5.5V 4.5V ≤ VBIAS ≤ 5.5V Output Voltage Line Regulation (Note 6) Output Voltage Load Regulation (Note 7) Dropout Voltage (Note 8) Quiescent Current Drawn from VIN Supply VO(NOM) + 1V ≤ VIN ≤ 5.5V 10 mA < IL < 0.8A IL = 0.8A 10 mA < IL < 0.8A V S/D ≤ 0.3V 1 µA ΔVO/ΔVIN ΔVO/ΔIL VDO IQ(VIN) 0.01 0.1 75 30 0.06 2 0.03 3.8 0.4 1.3 120 205 35 40 1 30 4 6 1 30 %/V %/A mV mA µA mA µA V A 1.3 IQ(VBIAS) Quiescent Current Drawn from VBIAS Supply 10 mA < IL < 0.8A V S/D ≤ 0.3V UVLO ISC VSDT Td (OFF) Td (ON) IS/D θJ-A VBIAS Voltage Where Regulator Output Is Enabled Short-Circuit Current Output Turn-off Threshold Turn-OFF Delay Turn-ON Delay S/D Input Current VOUT = 0V Output = ON Output = OFF RLOAD X COUT