LP3918TLX-L

LP3918 Battery Charge Management and Regulator Unit October 2007 LP3918 Battery Charge Management and Regulator Unit General Description The LP3918 is a fully integrated charger and multi-regulator unit designed for CDMA cellular phones. The LP3918 contains a Li-Ion battery charger, 7 low noise low dropout (LDO) voltage regulators and a high-speed serial interface to program on/off conditions and output voltages of individual regulators, and also to read status information from the PMU. The Li-Ion charger integrates a power FET, reverse current blocking diode, sense resistor with current monitor output, and requires only a few external components. Charging is thermally regulated to obtain the most efficient charging rate for a given ambient temperature. LDO regulators provide high PSRR and low noise ideally suited for supplying power to both analog and digital loads. Features ■ Fully integrated Li-Ion battery charger with thermal regulation ■ USB Charge Mode. ■ 7 Low Noise LDO’s 2 x 300 mA 3 x 150 mA 2 x 80 mA I2C compatible interface for controlling LDO outputs and charger operation Thermal shutdown Under Voltage Lockout 25-bump Thin micro-SMD package 2.5 x 2.5 mm Options available on request, please contact sales office for further information; - Level detect on HF_PWR & PWR_ON - LDO Charging mode - Custom Default Settings on Charger, and LDO O/P's. ■ ■ ■ ■ ■ Applications ■ ■ ■ ■ ■ CDMA Phone Handsets Low Power Wireless Handsets Handheld Information Appliances Personal Media Players Digital Cameras Key Specifications ■ ■ ■ ■ 50mA to 950mA Programmable Charge Current 3.0V to 5.5V Input Voltage Range 200mV typ. Dropout Voltage on 300 mA LDO’s 2% (typ) Output Voltage Accuracy on LDO’s Simplified Functional Block Diagram 20211601 © 2007 National Semiconductor Corporation 202116 www.national.com LP3918 Device Pin Diagram LP3918 25 pin micro-SMD Package TOP VIEW 20211634 Package Marking Information 20211604 — — — — The physical placement of the package marking will vary from part to part. Date Code. XYTT format. ‘XY’ 2 digit date code; ‘TT’ – dierun code MNK - Package Marking See National web page for more info - http://www.national.com/quality/marking_conventions.html Ordering Information Order Number LP3918TL LP3918TLX LP3918TL-L LP3918TLX-L LP3918TL-A LP3918TLX-A YES NO 3918A NO YES 3918L Connector Debounce NO LDO MODE NO Package Marking 3918 Supplied As 250 units, Tape & Reel 1000 units, Tape & Reel 250 units, Tape & Reel 1000 units, Tape & Reel 250 units, Tape & Reel 1000 units, Tape & Reel www.national.com 2 LP3918 LP3918 Pin Descriptions Pin # A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 Name IMON PS_HOLD VSS RESET_N ACOK_N CHG_IN PWR_ON SCL PON_N LDO7 BATT HF_PWR SDA TX_EN LDO6 VIN1 TCXO_EN GNDA RX_EN LDO5 LDO1 LDO2 LDO3 LDO4 VIN2 D: Digital. O: Output. Type A DI G DO DO P DI DI DO A P DI DI/O DI A P DI G DI A A A A A P Description Charge current monitor output. This pin presents an analog voltage representation of the input charging current. VIMON(mV) = (2.47 x ICHG)(mA). Input for power control from external processor/controller. Digital Ground pin Reset Output. Pin stays LOW during power up sequence. 60ms after LDO1 (CORE) is stable this pin is asserted HIGH. AC Adapter indicator, LOW when 4.5V – 6.0V present at CHG_IN. DC power input to charger block from wall or car power adapters. Power up sequence starts when this pin is set HIGH. Internal 500kΩ pull-down resistor. Serial Interface Clock input. External pull up resistor is needed, typ 1.5kΩ Active low signal is PWR_ON inverted LDO7 Output (GP) Main battery connection. Used as a power connection for current delivery to the battery. Power up sequence starts when this pin is set HIGH. Internal 500kΩ pull-down resistor. Serial Interface, Data Input/Output Open Drain output, external pull up resistor is needed, typ 1.5kΩ. Enable control for LDO6 (TX). HIGH = Enable, LOW = Disable. LDO6 Output (TX) Battery Input for LDO1 - 2 Enable control for LDO4 (TCXO). HIGH = Enable, LOW = Disable. Analog Ground pin Enable control for LDO5 (RX). HIGH = Enable, LOW = Disable. LDO5 Output (RX) LDO1 Output (CORE) LDO2 Output (DIGI) LDO3 Output (ANA) LDO4 Output (TCXO) Battery Input for LDO3 - 7 A: Analog. G: Ground. I: Input. DI/O: Digital Input/Output. P: Power. 3 www.national.com LP3918 Applications Schematic Diagram 20211605 Device Description The LP3918 Charge Management and Regulator Unit is designed to supply charger and voltage output capabilities for mobile systems, e.g. CDMA handsets. The device provides a Li-Ion charging function and 7 regulated outputs. Communication with the device is via an I2C compatible serial interface that allows function control and status read-back. The battery charge management section provides a programmable CC/CV linear charge capability. Following a normal charge cycle a maintenance mode keeps battery voltage between programmable levels. Power levels are thermally regulated to obtain optimum charge levels over the ambient temperature range. Charger Features • Pre-charge, CC, CV and Maintenance modes • USB Charge 100mA/450mA • Integrated FET • Integrated Reverse Current Blocking Diode • Integrated Sense Resistor • Thermal regulation • Charge Current Monitor Output • Programmable charge current 50mA - 950mA with 50mA steps • Default CC mode current 100mA • • • • • • • • Pre-charge current fixed 50mA Termination voltage 4.1V, 4.2V (default), 4.3V, and 4.4V, accuracy better than +/- 0.5% (typ) Restart level 50mV, 100mV, 150mV (default) and 200mV below Termination voltage End of Charge 0.1C (default), 0.15C, 0.2C and 0.25C Programmable Enable Control Safety timer Input voltage operating range 4.5V - 6.0V LDO mode on LP3918TL-L option. REGULATORS 7 Low dropout linear regulators provide programmable voltage outputs with current capabilities of 80mA, 150mA and 300mA as given in the table below. LDO1, LDO2 and LDO3 are powered up by default with LDO1 reaching regulation before LDO2 and LDO3 are started. LDO1, LDO3 and LDO7 can be disabled/enabled via the serial interface. During power up LDO1 and LDO2 must reach their regulation voltage detection point for the device to power up and remain powered. LDO4, LDO5 and LDO6 have external enable pins and may power up following LDO2 as determined by their respective enable. Under voltage lockout oversees device start up with preset level of 2.85V(typ). www.national.com 4 LP3918 POWER SUPPLY CONFIGURATIONS At PMU start up, LDO1, LDO2 and LDO3 are always started with their default voltages. The start up sequence of the LDO's is given below. Startup Sequence LDO1 -> LDO2 -> LDO3 LDO's with external enable control (LDO4, LDO5, LDO6) start immediately after LDO2 if enabled by logic high at their respective control inputs. LDO7 (and LDO1 and 3) may be programmed to enable/disable once PS_HOLD has been asserted. Default voltages for the LDOs are shown in Table 1 and Table 2 shows the voltages that may be programmed via the Serial Interface. DEVICE PROGRAMMABILITY An I2C compatible Serial Interface is used to communicate with the device to program a series of registers and also to read status registers. These internal registers allow control over LDO outputs and their levels. The charger functions may also be programmed to alter termination voltage, end of charge current, charger restart voltage, full rate charge current, and also the charging mode. This device internal logic is powered from LDO2. TABLE 1. LDO Default Voltages LDO 1 2 3 4 5 6 7 Function CORE DIGI ANA TCXO RX TX GP mA 300 300 80 80 150 150 150 Default Voltage (V) 1.8 3.0 3.0 3.0 3.0 3.0 3.0 Startup Default ON ON ON OFF OFF OFF OFF Enable Control SI SI TCXO_EN RX_EN TX_EN SI TABLE 2. LDO Output Voltages Selectable via Serial Interface LDO 1 2 3 4 5 6 7 CORE DIGI ANA TCXO RX TX GP mA 300 300 80 80 150 150 150 + + + + + + + + + + 1.5 + 1.8 + 1.85 + 2.5 + + 2.6 + + 2.7 + + + + + + + 2.75 + + + + + + + 2.8 + + + + + + + 2.85 + + + + + + + 2.9 + + + + + + + 2.95 + + + + + + + 3.0 + + + + + + + 3.05 + + + + + + + + + + + + + 3.1 + + 3.2 + + 3.3 + + 5 www.national.com LP3918 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. CHG-IN, VBATT =VIN1/2, BATT,HF_PWR All other Inputs Junction Temperature (TJ-MAX) Storage Temperature Max Continuous Power Dissipation (PD-MAX) (Note 3) ESD (Note 4) Batt, VIN1, VIN2, HF_PWR, CHG_IN, PWR_ON All other pins −0.3 to +6.5V −0.3 to +6V −0.3 to VBATT +0.3V, max 6.0V 150°C −40°C to +150°C Internally Limited HF_PWR, PWR_ON ACOK_N, SDA, SCL, RX_EN, TX_EN, TCXO_EN, PS_HOLD, RESET_N All other pins Junction Temperature (TJ) Ambient Temperature (TA) 0V to 5.5V 0V to (VLDO2 + 0.3V) 0V to (VBATT + 0.3V) −40°C to +125°C -40 to 85°C (Note 9) Thermal Properties Junction to Ambient Thermal Resistance θJA Jedec Standard Thermal PCB 4L Cellphone Board 37°C/W 66°C/W 8kV HBM 2kV HBM Operating Ratings CHG_IN VBATT =VIN1/2, BATT (Notes 1, 2) 4.5 to 6.0V 3.0 to 5.5V General Electrical Characteristics Unless otherwise noted, VIN ( = VIN1 = VIN2 = BATT) = 3.6V, GND = 0V, CVIN1-2=10µF, CLDOX=1µF. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, Ta = TJ = −40°C to +125°C. (Note 6) Symbol IQ(STANDBY) Parameter Standby Supply Current Condition VIN= 3.6V, UVLO on, internal logic circuit on, all other circuits off Typ 2 Limit Min Max 10 Units µA Power Monitor Functions Battery Under-Voltage Lockout VUVLO-R Under Voltage Lock-out TSD Threshold VIN Rising (Note 7) 2.85 160 2.7 3.0 V °C Thermal Shutdown www.national.com 6 LP3918 Symbol Parameter Condition Typ Limit Min Max 0.25* VLDO2 0.25* VBATT 0.75* VLDO2 0.75* VBATT -5 +5 Units LOGIC AND CONTROL INPUTS (LDO2 at 3.0V) VIL Input Low Level PS_HOLD, SDA, SCL, RX_EN, TCXO_EN, TX_EN PWR_ON, HF_PWR VIH Input High Level PS_HOLD, SDA, SCL, RX_EN, TCXO_EN, TX_EN PWR_ON, HF_PWR IIL Logic Input Current All logic inputs except PWR_ON and HF_PWR 0V ≤ VINPUT ≤ VBATT RIN Input Resistance PWR_ON, HF_PWR Pull-Down resistance to GND(Note 7) PON_N, RESET_N, SDA, ACOK_N IOUT = 2mA PON_N, RESET_N, ACOK_N IOUT = 2mA (Not applicable to Open Drain Output SDA) 0.75* VLDO2 500 kΩ V V V V µA LOGIC AND CONTROL OUTPUTS (LDO2 at 3.0V) VOL Output Low Level 0.25* VLDO2 V V VOH Output High Level LDO1 (CORE) Electrical Characteristics Unless otherwise noted, VIN ( = VIN1 = VIN2 = BATT) = 3.6V, GND = 0V, CVIN1-2=10µF, CLDOX=1µF. VOUT1 set to 3.0V output. Note VINMIN is the greater of 3.0V or VOUT1+ 0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, Ta = TJ = −40°C to +125°C. (Note 6) Symbol VOUT1 Parameter Output Voltage Accuracy Output Voltage IOUT1 VDO1 ΔVOUT1 Output Current Output Current Limit Dropout Voltage Line Regulation Load Regulation en1 PSRR tSTART-UP TTransient Output Noise Voltage Power Supply Rejection Ratio Start-Up Time from Shut-down Start-Up Transient Overshoot Condition IOUT1 = 1mA, VOUT1= 3.0V Default VINMIN ≤ VIN ≤ 5.5V VOUT1 = 0V IOUT1 = 300mA, (Note 8) VINMIN ≤ VIN ≤ 5.5V IOUT1 = 1mA 1mA ≤ IOUT1 ≤ 300mA 10Hz ≤ f ≤ 100KHz, COUT = 1µF (Note 7) F = 10kHz, COUT = 1µF IOUT1 = 20mA (Note 7) COUT = 1µF, IOUT1 = 300mA (Note 7) COUT = 1µF, IOUT1 = 300mA (Note 7) 60 120 mV 60 170 µs 65 dB 20 45 mV µVRMS 600 200 2 280 mV mV 1.8 300 Typ Limit Min −2 −3 Max +2 +3 V mA Units % 7 www.national.com LP3918 LDO2 (DIGI) Electrical Characteristics Unless otherwise noted, VIN ( = VIN1 = VIN2 = BATT) = 3.6V, GND = 0V, CVIN1-2=10µF, CLDOX=1µF. Note VINMIN is the greater of 3.0V or VOUT2+ 0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, Ta = TJ = −40°C to +125°C.(Note 6) Symbol VOUT2 Parameter Output Voltage Accuracy Output Voltage IOUT2 VDO2 ΔVOUT2 Output Current Output Current Limit Dropout Voltage Line Regulation Load Regulation en2 PSRR tSTART-UP tTransient Output Noise Voltage Power Supply Rejection Ratio Start-Up Time from Shut-down Start-Up Transient Overshoot Condition IOUT2 = 1mA, VOUT2= 3.0V Default VINMIN ≤ VIN ≤ 5.5V VOUT2 = 0V IOUT2 = 300mA (Note 8) VINMIN ≤ VIN ≤ 5.5V IOUT2 = 1mA 1mA ≤ IOUT2 ≤ 300mA 10Hz ≤ f ≤ 100KHz, COUT = 1µF (Note 7) F = 10kHz, COUT = 1µF IOUT2 = 20mA (Note 7) COUT = 1µF, IOUT2 = 300mA (Note 7) COUT = 1µF, IOUT2 = 300mA (Note 7) 5 30 mV 40 60 µs 65 dB 20 45 mV µVRMS 600 200 2 280 mV mV 3.0 300 Typ Limit Min −2 −3 Max +2 +3 V mA Units % LDO3 (ANA), LDO4 (TCXO) Electrical Characteristics Unless otherwise noted, VIN ( = VIN1 = VIN2 = BATT) = 3.6V, GND = 0V, CVIN1-2=10µF, CLDOX=1µF. TCXO_EN high. Note VINMIN is the greater of 3.0V or VOUT3/4 + 0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, Ta = TJ = −40°C to +125°C. (Note 6) Symbol VOUT3, VOUT4 Parameter Output Voltage Accuracy Output Voltage IOUT3, IOUT4 VDO3, VDO4 ΔVOUT3 , ΔVOUT4 Load Regulation en3,en4 PSRR tSTART-UP tTransient Output Noise Voltage Power Supply Rejection Ratio Start-Up Time from Shut-down Start-Up Transient Overshoot Output Current Output Current Limit Dropout Voltage Line Regulation Condition IOUT3/4 = 1mA, VOUT3/4= 3.0V LDO3 default LDO4 default VINMIN ≤ VIN ≤ 5.5V VOUT3/4 = 0V IOUT3/4 = 80mA (Note 8) VINMIN ≤ VIN ≤ 5.5V IOUT3/4 = 1mA 1mA ≤ IOUT3/4 ≤ 80mA 10Hz ≤ f ≤ 100kHz, COUT = 1µF (Note 7) F = 10kHz, COUT = 1µF IOUT3/4 = 20mA (Note 7) COUT = 1µF, IOUT3/4 = 80mA (Note 7) COUT = 1µF, IOUT3/4 = 80mA (Note 7) 40 5 60 30 µs mV 20 45 65 mV µVRMS dB 160 180 2 220 mV mV 3.0 3.0 80 mA Typ Limit Min −2 −3 Max +2 +3 V Units % www.national.com 8 LP3918 LDO5 (RX), LDO6 (TX), LDO7 (GP) Electrical Characteristics Unless otherwise noted, VIN ( = VIN1 = VIN2 = BATT) = 3.6V, GND = 0V, CVIN1-2=10µF, CLDOX=1µF. RX_EN, TX_EN high. LDO7 Enabled via Serial Interface. Note VINMIN is the greater of 3.0V or VOUT5/6/7 + 0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, Ta = TJ = −40°C to +125°C. (Note 6) Symbol Parameter Condition IOUT5/6/7 = 1mA, VOUT5/6/7= 3.0V LDO5 default LDO6 default LDO7 default IOUT5, IOUT6, Output Current IOUT7 Output Current Limit VDO5, VDO6, VDO7 ΔVOUT5, ΔVOUT6, ΔVOUT7 en5, en6, en7 PSRR tSTART-UP tTransient Load Regulation Output Noise Voltage Power Supply Rejection Ratio Start-Up Time from Shut-down Start-Up Transient Overshoot Dropout Voltage Line Regulation VINMIN ≤ VIN ≤ 5.5V VOUT5/6/7 = 0V IOUT5/6/7 = 150mA (Note 8) VINMIN ≤ VIN ≤ 5.5V IOUT5/6/7 = 1mA 1mA ≤ IOUT5/6/7 ≤ 150mA 10Hz ≤ f ≤ 100kHz, COUT = 1µF (Note 7) F = 10kHz, COUT = 1µF IOUT5/6/7 = 20mA (Note 7) COUT = 1µF, IOUT5/6/7 = 150mA (Note 7) COUT = 1µF, IOUT5/6/7 = 150mA (Note 7) 40 5 60 30 µs mV 20 45 65 mV µVRMS dB 300 180 2 240 mV mV 3.0 3.0 3.0 150 mA Typ Limit Min −2 −3 Max +2 +3 V Units % VOUT5, Output Voltage VOUT6, VOUT7 Output Voltage 9 www.national.com LP3918 Charger Electrical Characteristics Unless otherwise noted, VCHG-IN = 5V, VIN ( = VIN1 = VIN2 = BATT) = 3.6V.CCHG_IN = 10µF, CBATT = 30µF. Charger set to default settings unless otherwise noted. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, Ta = TJ = −25°C to +85°C. (Notes 6, 9) Symbol VCHG-IN VOK_CHG VTERM Parameter Input Voltage Range Operating Range CHG_IN OK trip-point Battery Charge Termination voltage VTERM voltage tolerance ICHG Fast Charge Current Accuracy Programmable full-rate charge current range (default 100mA) VCHG_IN - VBATT (Rising) VCHG_IN - VBATT (Falling) Default TJ = 25°C TJ = 0°C to 85°C ICHG = 450mA 6.0V ≥ VCHG_IN ≥ 4.5V VBATT < (VCHG_IN - VOK_CHG) VFULL_RATE < VBATT < VTERM (Note 10) Default Charge current programming step IPREQUAL ICHG_USB Pre-qualification current CHG_IN programmable current in USB mode VBATT = 2V 5.5V ≥ VCHG_IN ≥ 4.5V VBATT < (VCHG_IN - VOK_CHG) VFULL_RATE < VBATT < VTERM High Default = 100mA VFULL_RATE IEOC VRESTART Full-rate qualification threshold VBATT rising, transition from pre-qual to full-rate charging Low 100 50 50 100 450 100 3.0 10 4.05 3.97 4.13 V 0.247 1.112 115 0.947 1.277 2.9 3.1 V % mA 40 60 mA 200 50 4.2 -0.35 -1 -10 50 +0.35 +1 +10 950 % mA V % Condition Typ Limit Min 4.5 4.5 Max 6.5 6 Units V mV End of Charge Current, % 0.1C option selected of full-rate current Restart threshold voltage VBATT falling, transition from EOC to full-rate charge mode. Default options selected - 4.05V IMON Voltage 1 IMON Voltage 2 Regulated junction temperature Power OK deglitch time Deglitch time Charge timer ICHG = 100mA ICHG = 450mA (Note 7) IMON TREG V °C Detection and Timing (Note 7) TPOK TPQ_FULL TCHG VBATT < (VCC - VOK_CHG) Pre-qualification to full-rate charge transition Precharge mode Full Rate Charging Timeout Constant Voltage Timeout TEOC Deglitch time for end-ofcharge transition 32 230 1 5 5 230 mS mS mS Hrs www.national.com 10 LP3918 Serial Interface Unless otherwise noted, VIN ( = VIN1 = VIN2 = BATT) = 3.6V, GND = 0V, CVIN1-2=10µF, CLDOX=1µF, and VLDO2 (DIG) = 3.0V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, Ta = TJ = −40°C to +125°C. (Notes 6, 7) Symbol fCLK tBF tHOLD tCLK-LP tCLK-HP tSU tDATA-HOLD tDATA-SU tSU tTRANS Parameter Clock Frequency Bus-Free Time between START and STOP Hold Time Repeated START Condition CLK Low Period CLK High Period Set-Up Time Repeated START Condition Data Hold Time Data Set-Up Time Set-Up Time for STOP Condition Maximum Pulse Width of Spikes that Must be Suppressed by the Input Filter of both DATA & CLK Signals 50 1.3 0.6 1.3 0.6 0.6 50 100 0.6 Condition Typ Limit Min Max 400 Units kHz µs µs µs µs µs ns ns µs ns Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: Internal Thermal Shutdown circuitry protects the device from permanent damage. Note 4: The human-body model is 100pF discharged through 1.5kΩ. The machine model is a 200pF capacitor discharged directly into each pin, MIL-STD-883 3015.7. Note 5: Care must be exercised where high power dissipation is likely. The maximum ambient temperature may have to be derated. Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. In applications where high power dissipation and/or poor thermal dissipation exists, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA_MAX) is dependent on the maximum power dissipation of the device in the application (PD_MAX), and the junction to ambient thermal resistance of the device/package in the application (θJA), as given by the following equation: TA_MAX = TJ_MAX-OP – (θJA X PDMAX ). Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 7: Guaranteed by design. Note 8: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply in cases it implies operation with an input voltage below the 3.0V minimum appearing under Operating Ratings. For example, this specification does not apply for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V. Note 9: Junction-to-ambient thermal resistance (θJA) is taken from thermal modelling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The value of (θJA) of this product could fall within a wide range, depending on PWB material, layout, and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues in board design. Note 10: Full charge current is guaranteed for CHG_IN = 4.5 to 6.0V. At higher input voltages, increased power dissipation may cause the thermal regulation to limit the current to a safe level, resulting in longer charging time. 11 www.national.com LP3918 Register Information, Slave Address Code 7h’7E TABLE 3. Control Registers Addr 8h'00 8h'01 8h'02 8h'03 8h'04 8h'05 8h'06 8h'07 8h'0C 8h'10 8h'11 8h'12 Register (default value) OP_EN (0000 0101) LDO1PGM O/P (0000 0001) LDO2PGM O/P (0000 1011) LDO3PGM O/P (0000 1011) LDO4PGM O/P (0000 1011) LDO5PGM O/P (0000 1011) LDO6PGM O/P (0000 1011) LDO7PGM O/P (0000 1011) STATUS (0000 0000) CHGCNTL1 (0000 1001) CHGCNTL2 (0000 0001) CHGCNTL3 (0001 0010) Batt_Over _Out CHGIN_ OK_Out VTERM[1] EOC D7 X X X X X X X X PWR_ON _TRIG D6 X X X X X X X X HF_PWR _TRIG D5 X X X X X X X X CHG_IN _TRIG D4 X X X X X X X X X TOUT_ doubling Prog_ ICHG[4] VTERM[0] Tout_ Fullrate D3 LDO7_EN V1_OP[3] V2_OP[3] V3_OP[3] V4_OP[3] V5_OP[3] V6_OP[3] V7_OP[3] X EN_Tout Prog_ ICHG[3] Prog_ EOC[1] Tout_ Prechg D2 LDO3_EN V1_OP[2] V2_OP[2] V3_OP[2] V4_OP[2] V5_OP[2] V6_OP[2] V7_OP[2] X En_EOC Prog_ ICHG[2] Prog_ EOC[0] LDO Mode D1 X V1_OP[1] V2_OP[1] V3_OP[1] V4_OP[1] V5_OP[1] V6_OP[1] V7_OP[1] X X Prog_ ICHG[1] Prog_ VRSTRT[1] Fullrate Tout_ ConstV APU_TSD_EN D0 LDO1_EN V1_OP[0] V2_OP[0] V3_OP[0] V4_OP[0] V5_OP[0] V6_OP[0] V7_OP[0] X EN_CHG Prog_ ICHG[0] Prog_ VRSTRT[0] PRECHG Bad_Batt PS_HOLD _DELAY USBMODE CHGMODE Force EOC _EN _EN 8h'13 CHGSTATUS1 8h'14 CHGSTATUS2 8h'1C MISC Control1 X (R/O) Not Used Bits are Read Only type. Codes other than those shown in the table are disallowed. Note that for Serial Interface operation and thus register control, LDO2 must be active to provide the power for the internal logic. www.national.com 12 LP3918 LDO Output Voltage Programming The following table summarizes the supported output voltages for the LP3918. Default voltages after startup are highlighted in bold. TABLE 4. Data Code (Reg 01 - 07) 8h'00 8h'01 8h'02 8h'03 8h'04 8h'05 8h'06 8h'07 8h'08 8h'09 8h'0A 8h'0B 8h'0C 8h'0D 8h'0E 8h'0F LDO1 V 1.5 1.8 1.85 2.5 2.6 2.7 2.75 2.8 2.85 2.9 2.95 3.0 3.05 3.1 3.2 3.3 2.5 2.6 2.7 2.75 2.8 2.85 2.9 2.95 3.0 3.05 3.1 3.2 3.3 2.7 2.75 2.8 2.85 2.9 2.95 3.0 3.05 LDO2 V VLDO3 V LDO4 V 1.5 1.8 1.85 2.5 2.6 2.7 2.75 2.8 2.85 2.9 2.95 3.0 3.05 3.1 3.2 3.3 2.7 2.75 2.8 2.85 2.9 2.95 3.0 3.05 2.7 2.75 2.8 2.85 2.9 2.95 3.0 3.05 LDO5 V LDO6 V LDO7 V 1.5 1.8 1.85 2.5 2.6 2.7 2.75 2.8 2.85 2.9 2.95 3.0 3.05 3.1 3.2 3.3 Charger Control Register 2 Note that Bits 7,6,5 are not used and must be set to 0 during write to this register. CHARGER CURRENT PROGRAMMING The following table summarizes the supported charging current values for the LP3918. Default charge current after startup is highlighted in bold TABLE 5. LP3918 Charger Current Programming Address 8h'11 Address 8h'11 Address 8h'11 Register ID CHGCNTL2 Register ID CHGCNTL2 Register ID CHGCNTL2 01110 750mA 00111 400mA 00000 50mA Current Selection Prog_ICHG Bit 0 to Bit 4 00001 100mA 01000 450mA 01111 800mA 00010 150mA 01001 500mA 10000 850mA 00011 200mA 01010 550mA 10001 900mA 00100 250mA 01011 600mA 10010 950mA 00101 300mA 01100 650mA 00110 350mA 01101 700mA Current Selection Prog_ICHG Bit 0 to Bit 4 Current Selection Prog_ICHG Bit 0 to Bit 4 13 www.national.com LP3918 Charger Control Register 3 CHARGER TERMINATION VOLTAGE PROGRAMMING TABLE 6. LP3918 Charger Termination Voltage Control Address Register ID VTERM[1] CHGCNTL3 8h'12 CHGCNTL3 0 0 1 1 END OF CHARGE CURRENT PROGRAMMING TABLE 7. LP3918 EOC Current Control Address Register ID PROG_EOC[1] CHGCNTL3 8h'12 CHGCNTL3 0 0 1 1 CHARGING RESTART VOLTAGE PROGRAMMING TABLE 8. LP3918 Charging Restart Voltage Address Register ID PROG_VRSTRT[1] CHGCNTL3 8h'12 CHGCNTL3 0 0 1 1 Charging Restart Voltage Selection Bits PROG_VRSTRT[1] CHGCNTL3 0 1 0 1 VTERM - 50mV VTERM - 100mV VTERM - 150mV VTERM - 200mV Restart Voltage(V) End Of Charge Current Selection Bits PROG_EOC[0] CHGCNTL3 0 1 0 1 0.1 (Default) 0.15C 0.2C 0.25C End Of Charge Current VTERM Selection Bits VTERM[0] CHGCNTL3 0 1 0 1 4.1 4.2 (Default) 4.3 4.4 Termination Voltage(V) Charger Control Register 1 CHARGING MODE SELECTION Charging mode selection changes will only take place when the battery voltage is above the 3.0V pre-charge/Full-rate charge threshold. TABLE 9. LP3918 USB Charging Selection Address Register ID USB_Mode_En CHGCNTL1 8h'10 CHGCNTL1 0 1 0 1 USB Charge Mode Control Bits CHG_Mode_En CHGCNTL1 0 0 1 1 Fast Charge Fast Charge USB USB Default or Selection Default or Selection 100mA 450mA Mode Current www.national.com 14 LP3918 Device Power Up and Shutdown Timing Device Power Up Logic Timing. PWR_ON 20211637 15 www.national.com LP3918 Device Power Up Logic Timing. CHG_IN, HF_PWR 20211607 www.national.com 16 LP3918 LP3918 Power On Behaviour (Failed PS_Hold) 20211608 LP3918 Normal Shutdown Behaviour 20211633 17 www.national.com LP3918 Functional Block Diagram 20211602 LP3918 Functional Block Diagram www.national.com 18 LP3918 Technical Description BATTERY CHARGE MANAGEMENT A charge management system allowing the safe charge and maintenance of a Li-Ion battery is implemented on the LP3918. This has a CC/CV linear charge capability with programmable battery regulation voltage and end of charge current threshold. The charge current in the constant current mode is programmable and a maintenance mode monitors for battery voltage drop to restart charging at a preset level. A USB charging mode is also available with 2 charge current levels. CHARGER FUNCTION Following the correct detection of an input voltage at the charger pin the charger enters a pre-charge mode. In this mode a constant current of 50mA is available to charge the battery to 3.0V. At this voltage level the charge management applies the default (100mA) full rate constant current to raise the battery voltage to the termination voltage level (default 4.2V). The full rate charge current may be programmed to a different level at this stage. When termination voltage (VTERM) is reached, the charger is in constant voltage mode and a constant voltage of 4.2V is maintained. This mode is complete when the end of charge current (default 0.1C) is detected and the charge management enters the maintenance mode. In maintenance mode the battery voltage is monitored for the restart level (4.05V at the default settings) and the charge cycle is re-initiated to re-establish the termination voltage level. For start up the EOC function is disabled. This function should be enabled once start up is complete and a battery has been detected. EOC is enabled via register CHGCNTL1, Table 10. The full rate constant current rate of charge may be programmed to 19 levels from 50mA to 950mA. These values are given in Table 5, and Table 12 The charge mode may be programmed to USB mode when the charger input is applied and the battery voltage is above 3.0V. This provides two programmable current levels of 100mA and 450mA for a USB sourced supply input at CHG_IN. Table 9 LDO Mode on device option LP3918TL-L The charger circuit automatically enters an LDO mode if no battery is detected on insertion of the charger input voltage. In LDO mode the battery pin is regulated to 4.2V and can source up to 1.0A of current. Normal operation with a battery connected can be re-established via the serial interface. The serial interface allows the device to switch between modes as required however care is required to ensure that LDO mode is not initiated while a battery is present. 20211638 FIGURE 1. LDO Mode Diagram EOC EOC is disabled by default and should be enabled when the system processor is awake and the system detects that a battery is present. Programming Information TABLE 10. Register Address 8h'10: CHGCNTL1 BIT 2 NAME En_EOC FUNCTION Enables the End Of Charge current level threshold detection. When set to '0' the EOC is disabled. The End Of Charge current threshold default setting is at 0.1C. This EOC value is set relative to C the set full rate constant current. This threshold can be set to 0.1C, 0.15C, 0.2C or 0.25C bychanging the contents of the PROG_EOC[1:0] register bits. TABLE 11. Register Address 8h'12: CHGCNTL3 BIT 2 3 NAME Prog_EOC[0] Prog_EOC[1] FUNCTION Set the End Of Charge Current. See Table 9 19 www.national.com LP3918 CHARGER FULL RATE CURRENT Programming Information TABLE 12. Register Address 8h'11: CHGCNTL2 Data BITs 000[00000] 000[00001] 000[00010] 000[00011] 000[00100] 000[00101] 000[00110] 000[00111] 000[01000] 000[01001] 000[01010] 000[01011] 000[01100] 000[01101] 000[01110] 000[01111] 000[10000] 000[10001] 000[10010] Charger Operation HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 NAME Prog_ICHG FUNCTION 50mA 100mA 150mA 200mA 250mA 300mA 350mA 400mA 450mA 500mA 550mA 600mA 650mA 700mA 750mA 800mA 850mA 900mA 950mA TERMINATION AND RESTART The termination and restart voltage levels are determined by the data in the VTERM[1:0] and PROG_VSTRT[1:0] bits in the control register. The restart voltage is programmed relative to the selected termination voltage. The Termination voltages available are 4.1V, 4.2V (default), 4.3V, and 4.4V. The Restart voltages are determined relative to the termination voltage level and may be set to 50mV, 100mV, 150mV (default), and 200mV below the set termination voltage level. Programming Information TABLE 13. Register Address 8h'12: CHGCNTL3 BIT 4 5 NAME VTERM[0] VTERM[1] FUNCTION Set the charging termination voltage. See Table 6 TABLE 14. Register Address 8h'12: CHGCNTL3 BIT 0 1 NAME VRSTRT[0] VRSTRT[1] FUNCTION Set the charging restart voltage. See Table 8 The operation of the charger with EOC enabled is shown in this simplified flow diagram. www.national.com 20 LP3918 20211636 FIGURE 2. Simplified Charger Functional Flow Diagram (EOC is enabled) The charger operation may be depicted by the following graphical representation of the voltage and current profiles. 20211635 FIGURE 3. Charge Cycle Diagram 21 www.national.com LP3918 Further Charger Register Information Charger Control Register 1 TABLE 15. Register Address 8h'10: CHGCNTL1 BIT 7 6 NAME USB_MODE _EN CHG_MODE _EN FUNCTION (if bit = '1') Sets the Current Level in USB mode. Forces the charger into USB mode when active high. If low, charger is in normal charge mode. Forces an EOC event. TABLE 16. Register Address 8h'13: CHGSTATUS1 BIT 7 6 5 NAME BAT_OVER _OUT CHGIN_ OK_Out EOC FUNCTION (if bit = '1') Is set when battery voltage exceeds 4.7V. Is set when a valid input voltage is detected at CHG_IN pin. Is set when the charging current decreases below the programmed End Of Charge levlel. Set after timeout on full rate charge. Set after timeout for precharge mode. Only available on LP3918TL_L. Set when the charger is in CC/CV mode. Set during precharge. 4 3 5 4 3 FORCE _EOC TOUT_ Doubling EN_Tout Tout_ Fullrate Tout_ Precharge LDO_Mode Fullrate PRECHG Doubles the timeout delays for all timeout signals. Enables the timeout counters. When set to '0' the timeout counters are disabled. Enables the End of Charge current level threshold detection. When set to '0' the functions are disabled. Forces the charger into LDO mode. Function available on LP3918TL_L. Charger enable. 2 1 0 2 EN_EOC Charger Status Register 2 Read only TABLE 17. Register Address 8h'13: CHGSTATUS2 BIT 1 0 NAME Tout_ ConstV BAD_ BATT FUNCTION (if bit = '1') Set after timeout in CV phase. Set at bad battery state. 1 Set_ LDOmode EN_CHG 0 Charger Status Register 1 Read only www.national.com 22 LP3918 IMON CHARGE CURRENT MONITOR Charge current is monitored within the charger section and a proportional voltage representation of the charge current is presented at the IMON output pin. The output voltage relationship to the actual charge current is represented in the following graph and by the equation: VIMON(mV) = (2.47 x ICHG)(mA) Note that the default setting for this Register is [0000 0101]. This shows that LDO1 and 3 are enabled by default whereas LDO7 is not enabled by default on start up. LDO OUTPUT PROGRAMMING TABLE 19. Regi ster Add (hex) 01 02 03 04 05 06 NAME Data Range (hex) Output Voltage LDO1PGM O/P LDO2PGM O/P LDO3PGM O/P LDO4PGM O/P LDO5PGM O/P LDO6PGM O/P LDO7PGM O/P 03 - 0F 00 - 0F 05 - 0C 00 - 0F 05 - 0C 05 - 0C 00 - 0F 1.5V to 3.3V (def. 1.8V) 2.5V to 3.3V (def 3.0V) 2.7V to 3.05V (def 3.0V) 1.5V to 3.3V (def 3.0V) 2.7V to 3.05V (def 3.0V) 2.7V to 3.05V (def 3.0V) 1.5V to 3.3V (def 3.0V) 20211611 07 FIGURE 4. IMON Voltage vs Charge Current Note that this function is not available if there is no input at CHG_IN or if the charger is off due to the input at CHG_IN being outwith the operating voltage range. See Table 2 for full programmable range of values. LDO Information OPERATIONAL INFORMATION The LP3918 has 7 LDO's of which 3 are enabled by default, LDO's 1,2 and 3 are powered up during the power up sequence. LDO4, 5 and 6 are separately, externally enabled and will follow LDO2 in start up if their respective enable pin is pulled high. LDO2, LDO3 and LDO7 can be enabled/disabled via the serial interface. LDO2 must remain in regulation otherwise the device will power down. While LDO1 is enabled this must also be in regulation for the device to remain powered. If LDO1 is disabled via I2C interface the device will not shut down. INPUT VOLTAGES There are two input voltage pins used to power the 7LDO's on the LP3918. VIN2is the supply for LDO3, LDO4, LDO5, LDO6 and LDO7. VIN1is the supply for LDO1 and LDO2. These input voltages should be tied to the Batt pin in the application. PROGRAMMING INFORMATION Enable via Serial Interface TABLE 18. Register Address 8h'00: OP_EN BIT 0 2 3 NAME LDO1_EN LDO3_EN LDO7_EN FUNCTION Bit set to '0' - LDO disabled Bit set to '1' - LDO enabled EXTERNAL CAPACITORS The Low Drop Out Linear Voltage regulators on the LP3918 require external capacitors to ensure stable outputs. The LDO's on the LP3918 are specifically designed to use small surface mount ceramic capacitors which require minimum board space. These capacitors must be correctly selected for good performance INPUT CAPACITOR Input capacitors are required for correct operation. It is recommended that a 10µF capacitor be connected between each of the voltage input pins and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analogue ground. A ceramic capacitor is recommended although a good quality tantalum or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have surge current rating sufficent for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temparature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain within its operational range over the entire operating temperature range and conditions. Output Capacitor Correct selection of the output capacitor is critical to ensure stable operation in the intended application.The output capacitor must meet all the requirements specified in the recommended capacitor table over all conditions in the application. These conditions include DC-bias, frequency and temperature. Unstable operation will result if the capacitance 23 www.national.com LP3918 drops below the minimum specified value. The LP3918 is designed specifically to work with very small ceramic output capacitors. The LDO's on the LP3918 are specifically designed to be used with X7R and X5R type capacitors. With these capacitors selection of the capacitor for the application is dependant on the range of operating conditions and temperature range for that application. (See section on Capacitor Characteristics). It is also recommended that the output capacitor be placed within 1cm from the output pin and returned to a clean ground line. Capacitor Characteristics The LDO's on the LP3918 are designed to work with ceramic capacitors on the input and output to take advantage of the benifits they offer. For capacitance values around 1µF, ceramic capacitors give the circuit designer the best design options in terms of low cost and minimal area. For both input and output capacitors careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly dependant on the conditions of operation and capacitor type. In particular to ensure stability, the output capacitor selection should take account of all the capacitor parameters to ensure that the specification is met within the application. Capacitance value can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size with smaller sizes giving poorer performance figures in general. As an example Figure 5 shows a typical graph showing a comparison of capacitor case sizes in a Capacitance vs DC Bias plot. As shown in the graph, as a result of DC Bias condition the capacitance value may drop below minimum capacitance value given in the recommended capacitor table (0.7µF in this case). Note that the graph shows the capacitance out of spec for 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers specifications for the nominal value capacitor are consulted for all conditions as some capacitor sizes (e.g 0402) may not be suitable in the actual application. Ceramic capacitors have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1µF ceramic capacitor is in the range of 20mΩ to 40mΩ, and also meets the ESR requirements for stability. The temperature performance of ceramic capacitors varies by type. Capacitor type X7R is specified with a tolerance of ±15% over temperature range -55ºC to +125ºC. The X5R has similar tolerance over the reduced temperature range -55ºC to +85ºC. Most large value ceramic capacitors ( Data from master [ ] Data from slave 20211629 FIGURE 9. Register Write Format 27 www.national.com LP3918 20211630 FIGURE 10. Register Read Format www.national.com 28 LP3918 Physical Dimensions inches (millimeters) unless otherwise noted Thin micro-SMD25 Package NS Package Number MKT-TLA2511A X1 = 2.465mm ± 0.030mm X2 = 2.465mm ± 0.030mm X3 = 0.600mm ± 0.075mm 29 www.national.com LP3918 Battery Charge Management and Regulator Unit Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. 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All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2007 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530-85-86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com