LP3928TL-1828

LP3928 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator October 2002 LP3928 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator General Description The LP3928 is designed for portable and wireless applications with demanding performance and space requirements. The LP3928 provides level shifting and power conversion needed for applications interfacing differing voltage levels. The part contains a bi-directional level shifter for three signals to translate the levels between 1.8V and 2.85V and an ultra low-dropout CMOS 2.85V voltage regulator. The three level shifted signals are individually direction controlled. Signals going from 2.85V to 1.8V can also be latched using an external clock source. The latches are powered from internal 2.85V. There is also an option to by-pass the latches. The built-in low-dropout voltage regulator is ideal for mobile phone and battery powered wireless applications. It provides up to 150 mA from a 3.05V to 6.0V input, and is characterized by extremely low dropout voltage, low quiescent current and low output noise voltage. It is stable with small 1.5 µF ± 30% ceramic and high quality tantalum output capacitors, requiring smallest possible PC board area. A shutdown mode is available for the level shifters and the regulator. High performance is achieved over various load conditions with very low rise and fall times. n 2 ns rise and fall times (typ.) n 20 ns direction switch response time n 2 µA input/output leakage current Low-Dropout Regulator: n 3.05V to 6.0V input range n 150 mA guaranteed output n Fast Turn-On time: 200 µs (typ.) n 100 mV maximum dropout with 150 mA load Features n Ultra small micro SMD package n Bi-directional level-shifter for three individual signals: 1.8V to 2.85V and 2.85V to 1.8V signal level translation n Logic controlled enable pins: 4 different operation modes n LDO stable with ceramic and high quality tantalum capacitors n Thermal shutdown Applications n n n n Multi-Media Cards for Cellular Phones SD Cards for Cellular Handsets Logic Level Translation Portable Information Appliances Key Specifications Level Shifter: n 4 ns propagation delay (typ.) © 2002 National Semiconductor Corporation DS200391 www.national.com LP3928 Typical Application Circuit 20039101 Block Diagram 20039102 www.national.com 2 LP3928 Package Outline and Connection Diagrams 20039104 Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” will designate the date code, “TT” is a NSC internal code for die traceability. Both will vary considerably. L8B identifies the device. Top View 20039103 Bottom View 16 Bump micro SMD Package See NSC Package Number TLA16AAA Pin Description Pin Name A1 A2 A3 B1 B2 B3 DIR1 DIR2 DIR3 VCCA VCCB VBAT GND EN1 EN2 LatchClk micro SMD Bump Identifier C4 D4 D3 C1 D1 D2 B3 B2 C3 B4 B1 A1 A3 A4 A2 C2 1.8V 1.8V 2.85V Logic Level 1.8V 1.8V 1.8V 2.85V 2.85V 2.85V 1.8V 1.8V 1.8V 1.8V I/O Channel, (Note 1) 1.8V I/O Channel, (Note 1) 1.8V I/O Channel, (Note 1) 2.85V I/O Channel, (Note 1) 2.85V I/O Channel, (Note 1) 2.85V I/O Channel, (Note 1) Direction control input Channel 1: ‘1’: A→B; 0; B→A Direction control input Channel 2: ‘1’: A→B; 0; B→A Direction control input Channel 3: ‘1’: A→B; 0; B→A IC supply to the 1.8V side IC supply, 2.85V output from LDO LDO supply, Battery voltage Power ground connection Mode pin 1, see Table 1 for modes and settings Mode pin 2, see Table 1 for modes and settings Clock input: rising edge latches B inputs (DIR=0, normal mode) Function Note 1: Pin pairs A1–B1, A2–B2 and A3–B3 form 3 independent bi-directional level-shifting channels. TABLE 1. Operation Modes Inputs EN1 0 0 1 1 EN2 0 1 0 1 Level shifter off: High Z state on A1–A3, B1–B3, LDO off Level shifter off: High Z state on A1–A3, B1–B3, LDO on Latch bypassed in B to A direction, LDO=on (Note 2) ON, normal mode (latch active) State Note 2: LatchClk is not used here. It should not be left floating. 3 www.national.com LP3928 Pin Description (Continued) TABLE 2. Direction Control and LatchCLK (Normal Mode) Inputs Outputs and Direction LatchClk X ↓ ↑ DIRx 1 0 0 Ax to Bx No change (on Ax) Bx to Ax, see example Example for Latch Mode, DIR1 = ‘0’, EN1 = EN2 = ‘1’ (delay not shown): 20039105 Ordering Information For micro SMD Package Output Voltage (V) 2.85 Grade STD LP3928 Supplied As 250 Units, Tape & Reel LP3928TL-1828 LP3928 Supplied As 3000 Units, Tape & Reel LP3928TLX-1828 www.national.com 4 LP3928 Absolute Maximum Ratings 4) (Notes 3, Maximum Power Dissipation micro SMD ESD Rating (Note 6) Human Body Model 360 mW 2 kV If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VBAT, VCCB VCCA A1–A3, EN, DIR B1–B3, LatchClk Junction Temperature Storage Temperature Lead Temperature (Note 27) Pad Temperature (Note 27) Power Dissipation (Note 5) θJA (micro SMD), typical −0.2V to +6.5V −0.2V to +3.3V −0.2V to VCCA + 0.2V −0.2V to VCCB + 0.2V 150˚C −65˚C to +150˚C 235˚C 235˚C 180˚C/W Operating Conditions (Notes 3, 4) VBAT VCCA VCCB Junction Temperature Ambient Temperature Maximum Power Dissipation (Note 8) 3.05V to 6.0V 1.65V to 1.95V (Note 7) −40˚C to +125˚C −40˚C to +85˚C 220 mW Electrical Characteristics Unless otherwise specified: H = VIH min, L = VIL max, CVBAT = 1 µF, IOUT = 1 mA, CVCCB = 1 µF, CVCCA = 1 µF. Typical values and limits appearing in standard typeface apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Note 9) Level Shifter DC Voltage Levels Unless otherwise specified: EN1 = H, EN2 = X; 3.05V ≤ VBAT ≤ 6V, 1.65V ≤ VCCA ≤ 1.95V. Symbol VIHA VILA VOHA VOLA VIHB VILB VOHB VOLB VIHEN-DIR VILEN-DIR VIHLatClk VILLatClk Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Voltage Conditions For A Pins For A Pins For B Pins For B Pins IOH =4 mA IOL =4 mA IOH =4 mA IOL =4 mA Min VCCA*0.65 0 VCCA−0.45 0 VCCB*0.7 0 VCCB*0.7 0 VCCA*0.75 0 VCCB*0.7 0 2.75 0.1 1.5 0.1 Typ Max VCCA+0.2 VCCA*0.35 VCCA+0.2 VCCA*0.25 VCCB+0.2 VCCB*0.3 VCCB+0.2 VCCB*0.2 VCCA+0.2 VCCA*0.27 VCCB+0.2 VCCA*0.3 Units V V V V V V V V V V V V For EN and DIR Pins For LatchClk Pin Level Shifter DC Current Levels Unless otherwise specified: EN1 = H, EN2 = X; VBAT = 6V or VCCA = 1.95V as applicable to B or A respectively. Symbol IIA IIDIR_EN Parameter Input Leakage Current Ai Input Leakage Current DIR/EN (Note 11) Input Leakage Current Bi, LatchClk (Note 12) Static ICCB Current/Channel Static ICCB Current Total (Notes 13, 17) Static ICCB Current/Channel Static ICCB Current Total (Notes 14, 17) Conditions ViA =0/1.9V, DIRi=H (VCCA = 1.8V when ViA = 1.9V) Vi=0/1.9V (VCCA = 1.8V when Vi = 1.9V) ViB =0/2.95V, DIRi=L EN2=H, DIRi=H, Total Includes IBCOM EN2=L, DIRi=L Total Includes IBCOM Min Typ 0.001 0.001 Max Units µA µA ±2 ±2 IIB ICHA→B 0.001 550 2050 2 406 ±2 875 3330 30 840 µA µA ICHB→A µA 5 www.national.com LP3928 Electrical Characteristics Unless otherwise specified: H = VIH min, L = VIL max, CVBAT = 1 µF, IOUT = 1 mA, CVCCB = 1 µF, CVCCA = 1 µF. Typical values and limits appearing in standard typeface apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Note 9) (Continued) Level Shifter DC Current Levels Symbol IBCOM IA ICCBEXT IOFFA IOFFBAT IOZA IOZB Parameter Common Static Level-Shifter ICCB Current (Notes 15, 17) Static Level-Shifter ICCA Current (Notes 16, 17) Off State ICCB Current with External VCCB (Note 7) Off State VCCA Current Off State VBAT Current Output Leakage Current Ai Output Leakage Current Bi VBAT =3.6V, EN1=L, EN2=L VCCA =1.9V, EN1,2=0, Ai=0V, Bi=0V, DIRi=0V, LatchClk=0V EN1,2=L VCCA =1.9V, ViA =0/1.9V, EN1=L ViB =0V, VBAT =3.35V, VCCB =0, EN1=L ViB =2.95V, VBAT =3.35V, VCCB =2.95V, EN1=L ISCA Short Circuit Current/ Channel Ai Output, VCCA =1.9V, DIRi=L, EN2=L Short Circuit Current/ Channel Bi Output, VBAT =2.95V, DIRi=H Ai=0V, Bi=H Ai=VCCA, Bi=L Bi=0V, Ai=H Bi=2.95V, Ai=L −90 −27 (Continued) Unless otherwise specified: EN1 = H, EN2 = X; VBAT = 6V or VCCA = 1.95V as applicable to B or A respectively. Conditions Min Typ 400 90 15 1.5 0.005 0.001 0.001 0.001 −17 36 −58 60 90 56 5 3 Max 750 165 Units µA µA µA µA µA µA µA µA mA mA mA mA ±2 ±2 ±2 ISCB Level Shifter AC Electrical Characteristics Unless otherwise specified: EN1 = H, 3.05V ≤ VBAT ≤ 6V, 1.65V ≤ VCCA = 1.95V. ((Note 28), (Note 29)) Symbol tPHL tPLH tR tF tMATCH tSL tHL tLS tDIR Rise Time Fall Time Delay Differences between Channel Outputs at Identical Input Signals Latch Set Up Time Latch Hold Time Level-Shifter Mode Switch Response Time Level-Shifter Direction Switch Response Time (Note 18) (Note 19) 1 1 Parameter Propagation Delay An to Bn or Bn to An Conditions CLB = 35 pF, CLA = 15 pF CLB = 35 pF, CLA = 15 pF CLB = 35 pF, CLA = 15 pF CLB = 35 pF, CLA = 15 pF Min Typ 4 4 2 2 Max 7 7 4 4 1.5 2 2 100 20 Units ns ns ns ns ns ns ns ns ns LDO Electrical Characteristics Unless otherwise specified: EN1 = L, EN2 = H; VOUTnom = 2.85V, VBAT = VOUT(nom) + 0.5V. Symbol Parameter Output Voltage Tolerance Line Regulation Error (Note 20) ∆VOUT Load Regulation Error (Note 21) Output AC Line Regulation IOUT = 1 mA VBAT = (VOUT(nom) + 0.5V) to 6.0V, IOUT = 1 mA IOUT = 1 mA to 150 mA VBAT = VOUT(nom) + 1V, IOUT = 100 mA, COUT = 4.7 µF (Figure 1) 1.5 Conditions Typical Limit Min −2 −3 −0.10 Max 2 3 0.10 0.005 Units % of VOUT(nom) %/V %/mA mVPP www.national.com 6 LP3928 Electrical Characteristics Unless otherwise specified: H = VIH min, L = VIL max, CVBAT = 1 µF, IOUT = 1 mA, CVCCB = 1 µF, CVCCA = 1 µF. Typical values and limits appearing in standard typeface apply for TJ = 25˚C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40˚C to +125˚C. (Note 9) (Continued) LDO Electrical Characteristics Symbol Parameter Power Supply Rejection Ratio (Note 29) (Continued) Unless otherwise specified: EN1 = L, EN2 = H; VOUTnom = 2.85V, VBAT = VOUT(nom) + 0.5V. Conditions VBAT = VOUT(nom) + 1V, f = 1 kHz, IOUT = 50 mA, (Figure 2) VBAT = VOUT(nom) + 1V, f = 50 kHz, IOUT = 50 mA, (Figure 2) Quiescent Current Dropout Voltage (Note 22) ∆VDO IOUT = 1mA IOUT = 1 mA to 150 mA IOUT = 1 mA IOUT = 50 mA IOUT = 100 mA IOUT = 150 mA ISC IOUT(PK) TON ρn (1/f) en Output Capacitor Short Circuit Current Limit Peak Output Current Turn-On Time (Note 23) (Note 29) Output Noise Density Output Noise Voltage Output Filter Capacitance (Note 24) Output Filter Capacitance ESR (Note 25) Thermal Shutdown Thermal Shutdown Temperature (Note 26) Thermal Shutdown Hysteresis f = 1 kHz, COUT = 1 µF BW = 10 Hz to 100 kHz, COUT = 1 µF VBAT = 3.05V to 6V, IOUT = 1mA to 150 mA VBAT = 3.05V to 6V, IOUT = 1mA to 150 mA 160 20 VBAT = 6V, Output Grounded (Steady State) VOUT ≥ VOUT(nom) − 5%, VBAT = 6V Typical 40 20 85 130 0.4 20 45 60 500 460 200 0.6 45 1 5 22 500 200 130 430 150 200 2 35 70 100 mA mA µs µV/√Hz µVrms µF mΩ ˚C ˚C mV µA Limit Min Max Units dB PSRR IQ Note 3: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test condition, see Electrical Characteristics tables. Note 4: All voltages are with respect to the potential at the GND pin. Note 5: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula P = (TJ − TA)/θJA, (1) Where TJ is the junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The 360 mW rating appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150˚C, for TJ, 85˚C for TA, and 180˚C/W for θJA. More power can be dissipated safely at ambient temperatures below 85˚C. The thermal resistance can be better or worse than 180˚C/W depending on board layout. Larger copper planes and thermal vias should be used to conduct heat away from the micro SMD solder bumps. Note 6: The Human Body Model is 100 pF discharged through 1.5 kΩ resistor into each pin. Note 7: VCCB can be supplied from an external voltage source in the range of 1.65V to 3.6V, as long as both VBAT and VCCB are connected to the external source. Only the LDO quiescent current (see DC electrical specifications) will add to the level-shifter current consumption. This Operating Rating does not imply guaranteed performance. For guaranteed performance limits and associated test conditions, see Electrical Characteristics tables. Note 8: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 220 mW rating appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125˚C, for TJ, 85˚C for TA, and 180˚C/W for θJA into (1) above. More power can be dissipated at ambient temperatures below 85˚C. The thermal resistance can be better or worse than 180˚C/W depending on board layout. Larger copper planes and thermal vias should be used to conduct heat away from the micro SMD solder bumps. Note 9: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25˚C or correlated using Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 10: The target output voltage, which is labeled VOUT(target), is the desired or ideal output voltage. The nominal output voltage, which is labeled VOUT(nom), is the output voltage measured with the input 0.5V above VOUT(target) and a 1 mA load. Note 11: Input leakage current for pins DIRi, EN1, EN2. Note 12: Input leakage current for pins Bi, LatchClk. Note 13: This is the static current consumption from VCCB for channel (i) when DIRi=H (A→B direction). Note 14: This is the static current consumption from VCCB for channel (i) when DIRi=L (B→ A direction). Note 15: This is the static current consumption from VCCB for the part common to the channels. 7 www.national.com LP3928 Note 16: This is the static current consumption from VCCA for the part common to the channels. Note 17: Only ICCBTOTAL for DIR1=DIR2=DIR3=H and ICCATOTAL for DIR1=DIR2=DIR3=L will be tested in production. Calculation example: assuming DIR1=H, DIR2=L, DIR3=L, then the typical ICCB current will be: ICCBTOTAL = IBCOM + ICHA→B + 2 * ICHB→A = 450 µA + 530 µA + 2 * 2 µA = 984 µA The typical ICCA current is: ICCATOTAL = IA = 90 µA. Note 18: This is the time it takes either to switch the level shifter on or off, or the time it takes to turn the latch by-pass on/off. Note 19: This is the time it takes to switch the direction of the level shifter. After this time a signal can be applied on the new input. For the B→A direction, if EN2=1, the latch set-up time has to be considered separately. Note 20: The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and vice versa. Note 21: The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage and vice versa. Note 22: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its normal value. This specification does not apply for input voltages below 2.7V. Note 23: Turn-on time is that between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal value. Note 24: Range of capacitor values for which the device will remain stable. This electrical specification is guaranteed by design. Note 25: Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design. Note 26: The built-in thermal shut-down of the LDO is also used to put all Ai and Bi outputs in tristate mode. Note 27: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112). Note 28: Unused inputs must be terminated. Note 29: This electrical specification is guaranteed by design. 20039106 FIGURE 1. Output AC Line Regulation 20039107 FIGURE 2. PSRR Input Perturbation Typical Performance Characteristics CVCCB = 1 µF, VBAT = 3.3V, VCCA = 1.8V, TA = 25˚C. Level Shifter Propagation Delay A→B Unless otherwise specified: CVBAT = 1 µF, CVCCA = 1 µF, Level Shifter Propagation Delay B→A 20039109 20039110 www.national.com 8 LP3928 Typical Performance Characteristics Unless otherwise specified: CVBAT = 1 µF, CVCCA = 1 µF, CVCCB = 1 µF, VBAT = 3.3V, VCCA = 1.8V, TA = 25˚C. (Continued) Power Supply Rejection Ratio (VBAT=3.46V) 20039108 Application Hints EXTERNAL CAPACITORS Like any low-dropout regulator, the LP3928 requires external capacitors for regulator stability. The LP3928 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. INPUT CAPACITOR An input capacitance of ≅ 1 µF is required between the LP3928 VBAT pin and ground (the amount of the capacitance may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the VBAT pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will be ≅ 1 µF over the entire operating temperature range. FAST ON-TIME The LP3928 utilizes a speed up circuitry to ramp up the internal VREF voltage to its final value to achieve a fast output turn on time. CAPACITOR CHARACTERISTICS The LP3928 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the range of 1 µF to 4.7 µF range, ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability by the LP3928. The ceramic capacitor’s capacitance can vary with temperature. Most large value ceramic capacitors (≅ 2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25˚C to 85˚C. A better choice for temperature coefficient in ceramic capacitor is X7R, which holds the capacitance within ± 15%. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1 µF to 4.7 µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25˚C down to −40˚C, so some guard band must be allowed. OUTPUT CAPACITOR The LP3928 is designed specifically to work with very small ceramic output capacitors, any ceramic capacitor (dielectric types Z5U, Y5V or X7R) in 1.5 µF to 22 µF range with 5 mΩ to 500 mΩ ESR range is suitable in the LP3928 application circuit. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see section Capacitor Characteristics). The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range. The output capacitor should be placed as near to the VCCB pin as possible. 9 www.national.com LP3928 Application Hints NO-LOAD STABILITY (Continued) The LDO of the LP3928 will remain stable and in regulation with no external load connected to the LDO output VCCB. This is especially important in CMOS RAM keep-alive applications. LEVEL SHIFTER DIRECTION CONTROL AND LATCH CLOCK The direction of the level shifter is set to Ax →Bx by pulling the DIRx pin to high. The direction of each of the three channels can be set individually. In this mode a change at the LatchClk pin has no effect. A low at the DIRx pin sets the direction to Bx→Ax. If EN2 is set to high (enabling latch mode), a rising edge of LatchClk will update Ax depending on the level at Bx. A falling edge of LatchClk will not change Ax. MICRO SMD ASSEMBLY For assembly recommendations of micro SMD package please refer to National Semiconductor Application Note AN-1112. MICRO SMD LIGHT SENSITIVITY Exposing the micro SMD device to direct sunlight will cause misoperation of the device. Light sources such as Halogen lamps can effect electrical performance if brought near to the device. The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has very little effect on performance. A micro SMD test board was brought to within 1 cm of a fluorescent desk lamp and the effect on the regulated output voltage was negligible, showing a deviation of less thanTBD from nominal. OPERATION MODES, EN1 AND EN2 The output of the LDO (VCCB) is turned off and the level shifter channels are set to a high Z state by pulling the enable input pins EN1 and EN2 low. EN1=0 and EN2=1 turns the LDO on and the level shifter off. EN1=1 and EN2=0 turns the LDO on and the latch of the level shifter is bypassed in B to A direction. The Latch Clock is not used in this mode. The LatchClk pin should not be left floating but actively terminated. EN1=1 and EN2=1 turns the LDO on and activates the latch in B to A direction. To assure proper operation, the signal source used to drive the EN input pins must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under Level Shifter DC Voltage Levels. Both pins, EN1 and EN2 must be actively terminated. www.national.com 10 LP3928 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator Physical Dimensions inches (millimeters) unless otherwise noted micro SMD, 16 Bump NS Package Number TLA16AAA The Dimensions for X1, X2 and X3 are as follows: X1 = 1.996mm X2 = 1.996mm X3 = 0.600mm LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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National Semiconductor Asia Pacific Customer Support Center Fax: 65-6250 4466 Email: ap.support@nsc.com Tel: 65-6254 4466 National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: nsj.crc@jksmtp.nsc.com Tel: 81-3-5639-7560 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.