LP3929TMEX-AACQ

LP3929 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator and Line Protection July 2006 LP3929 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator and Line Protection General Description The LP3929 is designed for portable and wireless applications requiring level translation and power supply generation in a compact footprint. The device level translates 1.8 V LVCMOS on the host (A) side to 2.85 V LVCMOS levels on the card (B) side for a miniSD / SD 4-bit bi-directional data bus. Independent direct control of the CMD, Data0 and Data1-3 paths support mini SD state machine requirements. A shutdown pin is provided for the level shifters and regulator. The f_CLK_A is a feedback clock to the host which can be used to overcome level shifter bus delay. The built-in low-dropout voltage regulator is ideal for mobile phone and battery powered wireless applications. It provides up to 200 mA from a 3.05 V to 5.5 V input. It is stable with small 1.0 µF ± 30% ceramic and high quality tantalum output capacitors, requiring smallest possible PC board area. The card (B port) side channels have integration of ASIP (Application Specific Integrated Passives) - on chip integrated pull-up, pull-down, series resistors and capacitors for EMC filtering. It is designed to tolerate IEC61000-4-2 level 4 ESD: ± 15 kV air discharge, ± 8 kV direct contact. Key Specifications Level Shifter: n 6-signal Level Shifter (5 bi-directional and 1 uni-direction) n 3 ns (typ) propagation delay n Channel-to-channel skew < 1 ns (max) Low-Dropout Regulator: n 3.05 V to 5.5 V input range n 2.85 V at 200 mA n Fast Turn-On time: 30 µs (typ) n 110 mV (max) dropout with 200 mA load n Thermal shutdown at 160˚C (typ) Protection Block (B Side): n Robust IEC ESD Protection: ± 15 kV Air Gap, ± 8 kV Direct Contact n ASIP / EMI Filtering Features n Ultra small micro SMD 24 bump package n 6-signal level translation 1.8 V to 2.85 V n LDO stable with ceramic and high quality tantalum capacitors Typical Application Circuit 20186801 © 2006 National Semiconductor Corporation DS201868 www.national.com LP3929 Block Diagram 20186802 www.national.com 2 LP3929 Package Outline and Connection Diagrams 20186812 Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” will designate the date code. The “TT” is a NSC internal code for die traceability; engineering sample parts will be marked as "ES". Both will vary considerably. The pin 1 marking identifier is the location of corner bump A1. Top View - TME24 Device Marking 20186811 Top View - Bump Underneath 24 Bump micro SMD Package See NSC Package Number TME24AAA Ordering Information For 24 Bump micro SMD Package Output Voltage Grade 2.85 V STD LP3929 Supplied As 250 Units, Tape & Reel LP3929 Supplied As 3000 Units, Tape & Reel LP3929TME-AACQ LP3929TMEX-AACQ Tape and Reel Information 20186810 Top View: Tape and Reel Information 3 www.national.com LP3929 Pin Descriptions Pin Name D0_A D1_A D2_A D3_A CMD_A CLK_A fCLK_A DIR_0 micro SMD Bump Identifier D1 E1 A1 B1 D2 C1 E2 A3 Port / Direction Host / Bidirectional Host / Bidirectional Host / Bidirectional Host / Bidirectional Host / Bidirectional Host / Input Host / Output Host / Input Type Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull High Z Push-Pull High Z Function 1.8 V I/O Channel (Note 14) 1.8 V I/O Channel (Note 14) 1.8 V I/O Channel (Note 14) 1.8 V I/O Channel (Note 14) 1.8 V I/O Channel (Note 14) 1.8 V Input CLK Channel (Note 14) 1.8 V Output CLK Channel 1.8 V Input Direction Control D0 Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) 1.8 V Input Direction Control D1-D3 Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) 1.8 V Input Direction Control CMD Channel: VDDA = A → B Direction (Write), VSS = B → A Direction (Read) Device Enable with high impedance pull-down resistor (200 kΩ): VDDA = Device Active (on), VSS = Device Disabled (off) 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) 2.85 V I/O Channel with high impedance pull-up to VDDB (70 kΩ) 2.85 V I/O Channel with high impedance pull-down to VSS (470 kΩ) 2.85 V I/O Channel with high impedance pull-up to VDDB (15 kΩ) 2.85 V Output CLK Channel 3.05 V to 5.5 V 1.71 V to 1.92 V, 1.8 V (typ) 2.85 V (LDO output) Ground Ground Host / Card Input Host / Card Input Pull-up Pull-up Pull-up to VDDA (100 kΩ) Pull-up to VDDA (100 kΩ) DIR_1-3 E3 Host / Input High Z CMD_DIR A2 Host / Input High Z EN C2 Host / Input High Z D0_B D1_B D2_B D3_B CMD_B CLK_B VBAT VDDA VDDB VSS VSS WP CD D5 E5 A5 B5 D4 C5 A4 B3 B4 C3 C4 E4 D3 Card / Bidirectional Card / Bidirectional Card / Bidirectional Card / Bidirectional Card / Bidirectional Card / Output Host / Input Host / Input Card / Output Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull Push-Pull Power Power Power www.national.com 4 LP3929 Pin Descriptions Inputs EN L H H H H H H H H CMD_DIR X L L L L H H H H DIR_0 X L L H H L L H H (Continued) TABLE 1. Operation Modes Mode DIR_1-3 X L H L H L H L H Level shifter / LDO = off (Shutdown Mode) All channels (D0-D3 and CMD): B → A Direction A → B Direction: D1-D3, B → A Direction: CMD and D0 A → B Direction: D0, B → A Direction: CMD and D1-D3 A → B Direction: D0-D3, B → A Direction: CMD A → B Direction: CMD, B → A Direction: D0-D3 A → B Direction: CMD and D1-D3, B → A Direction: D0 A → B Direction: CMD and D0, B → A Direction: D1-D3 All channels (D0-D3 and CMD): A → B Direction H = VDDA, L = VSS 5 www.national.com LP3929 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VBAT) Supply Voltage (VDDA) LVCMOS A Port Input Voltage LVCMOS A Port I/O Voltage LVCMOS A Port I/O Voltage Junction Temperature Storage Temperature Lead Temperature (Note 13) Pad Temperature (Note 13) Derate micro SMD Package above 25˚C −0.3V to +6.0V −0.3V to +3.3V −0.3V to VDDA + 0.3V −0.3V to VDDA + 0.3V −0.3V to VDDB + 0.3V 150˚C −65˚C to +150˚C 235˚C 235˚C 22.9 mW/˚C Maximum Power Dissipation Capacity at 25˚C micro SMD ESD Rating HBM, 1.5kΩ, 100pF EIAJ, 0Ω, 200pF IEC61000-4-2, 330Ω, 150pF, Air Gap, B Side (Note 2) IEC61000-4-2, 330Ω, 150pF, Direct Contact, B Side (Note 2) 2.8 W ± 2kV ± 200V ± 15kV ± 8kV Operating Conditions VBAT to VSS VDDA to VSS Ambient Temperature 3.05V to 5.5V 1.71V to 1.92V −30˚C to +85˚C Electrical Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25˚C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30˚C to +85˚C. (Notes 3, 4) Symbol VIH Parameter Input Voltage High Level VDDA = 1.71V VDDA = 1.92V VIL Input Voltage Low Level VDDA = 1.71V VDDA = 1.92V IIH Input Current High Level VIH = VDDA EN = VSS EN = VDDA IIL VOH VOL VIH VIL IIH Input Current Low Level Output Voltage High Level Output Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level VIH = VDDB D0_B to D2_B D3_B CMD_B IIL Input Current Low Level VIL = VSS D0_B to D2_B D3_B CMD_B IOS + IOS − VOH VOL Output Voltage High Level Output Voltage Low Level Short Circuit Current VOUTlow = VDDB VOUThigh = VSS IOH = − 2 mA IOL = 2 mA 0.75xVDDB 0.25xVDDB VIL = VSS IOH = −4 mA IOL = 4 mA Conditions Min 0.65xVDDA 1.1115 1.248 0 0 0 −1 −1 −1 −1 1.26 VSS 0.65xVDDB 0 −2 0 −5 − 80 −1 − 300 0.2 6.5 0.3 −40 0.1 − 200 45 − 20 0 0 0 0 1.8 0 Typ Max 1.92 1.92 1.92 0.30xVDDA 0.513 0.576 +1 +1 +10 +1 VDDA 0.45 VDDB 0.35xVDDB +2 + 13 +5 0 +1 − 20 Units V V V V V V µA µA µA µA V V V V µA µA µA µA µA µA µA µA V V LVCMOS A (Host) Port (VDDA = 1.71V to 1.92V) LVCMOS B (Card) Port (VDDB = 2.85V) www.national.com 6 LP3929 Electrical Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25˚C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30˚C to +85˚C. (Notes 3, 4) Symbol Supply Current IDD IDDZ COUT Supply Current Supply Current — Shutdown Output Capacitance (Note 15) All Channels Static: A → B mode, LDO unloaded EN = VSS B (card) port VBAT VDDA VBAT VDDA 4 95 0.1 0.2 15 7 200 2 2 20 mA µA µA µA pF Parameter Conditions Min Typ Max Units Level Shifter AC Switching Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25˚C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30˚C to +85˚C. (Notes 3, 5, 15, 16) Symbol tPLH Parameter Propagation Delay A to B or B to A Propagation Delay CLK_A to fCLK_A tPHL Propagation Delay A to B or B to A Propagation Delay CLK_A to fCLK_A tRISE tFALL tSKEW tEN tDIS tTA Rise Time A Side Output Figure 2 Rise Time B Side Output with ASIP Figure 2 Fall Time A Side Output Figure 2 Fall Time B Side Output with ASIP Figure 2 Skew between D0–D3, CLK and CMD outputs (either edge) Enable Time Disable Time Level-Shifter Direction Switch Response (Turn Around) Time Conditions CLB = 15 pF, CLA = 20 pF, 50%-50% CLA = 20 pF, 50%-50% CLB = 15 pF, CLA = 20 pF, 50%-50% CLA = 20 pF, 50%-50% CLA = 20 pF, 20%-70% CLB = 15 pF, 20%-70% CLA = 20 pF, 20%-70% CLB = 15 pF, 20%-70% Min Typ 3 5 3 5 1.1 1.6 1.0 1.9 Max 7 14 7 14 3 3 3 3 1.0 200 50 20 Units ns ns ns ns ns ns ns ns ns µs ns ns < 0.5 30 18 13 7 www.national.com LP3929 LDO Electrical Characteristics Unless otherwise specified: CVBAT = 1 µF, IOUT = 1 mA, CVDDB = 1 µF, CVDDA = 1 µF. Typical values and limits appearing in standard typeface apply for TA = 25˚C. Limits appearing in boldface type apply over the entire ambient temperature range for operation, −30˚C to +85˚C. (Note 3) Symbol VOUT ∆VOUT Parameter Output Voltage, VOUT = VDDB Output Voltage Tolerance Line Regulation Error (Note 6) Load Regulation Error (Note 7) Output AC Line Regulation PSRR Power Supply Rejection Ratio (Note 15) IOUT = 1 mA VBAT = (VOUT(nom) + 0.5V) to 5.5V, IOUT = 1 mA IOUT = 1 mA to 200 mA VBAT = VOUT(nom) + 1V, IOUT = 100 mA, COUT = 1.0 µF VBAT = VOUT(nom) + 1V, f = 1 kHz, IOUT = 50 mA VBAT = VOUT(nom) + 1V, f = 10 kHz, IOUT = 50 mA ∆VDO Dropout Voltage (Note 8) IOUT = 1 mA IOUT = 50 mA IOUT = 100 mA IOUT = 200 mA ISC TON ρn (1/f) en Output Capacitor Short Circuit Current Limit Turn-On Time (Notes 9, 15) Output Noise Density Output Noise Voltage Output Filter Capacitance (Note 10) Output Filter Capacitance ESR (Note 11) Thermal Shutdown Thermal Shutdown Temperature (Notes 12, 15) Thermal Shutdown Hysteresis (Note 15) f = 1 kHz, COUT = 1.0 µF BW = 10 Hz to 100 kHz, COUT = 1.0 µF VBAT = 3.05V to 5.5V, IOUT = 1mA to 200 mA VBAT = 3.05V to 5.5V, IOUT = 1mA to 200mA VBAT = 3.05V to 5.5V, IOUT = 1mA to 200mA 0.7 5 160 20 VBAT = 5.5V, Output Grounded (Steady State) Conditions IOUT = 200mA, VBAT = 3.05V to 5.5V Min 2.76 −2 −3 −0.15 −0.01 1.5 40 30 1 20 35 60 750 30 0.6 45 1.0 22 500 200 110 mA µs µV/√Hz µVrms µF mΩ ˚C ˚C mV Typ 2.85 Max 2.93 2 3 0.15 0.01 Units V % of VOUT(nom) %/V %/mA mVPP dB Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation. Note 2: IEC61000-4-2 level 4 ESD tolerance applies to VDDB, D0_B–D3_B, CMD_B, CLK_B, WP and CP pins only. Device is tested in application (common ground, bypass capacitors of 1.0 µF present on VBAT, VDDA and VDDB). Note 3: Typical values are given for VDDA = 1.8V, VBAT = 3.6V, TA = 25˚C Note 4: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are reference to ground unless otherwise specified. Note 5: Input signal for test purpose is defined as: A side – 0V to 1.8V with 2ns rise time (20%-70%) and B side – 0V to 2.85V with 2ns rise time (20%-70%) Note 6: The output voltage changes slightly with line voltage. An increase in the line voltage results in a slight increase in the output voltage and vice versa. Note 7: The output voltage changes slightly with load current. An increase in the load current results in a slight decrease in the output voltage and vice versa. Note 8: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for input voltages below 2.7V. Note 9: Turn-on time is that between when the enable input is high an the output voltage just reaching 95% of its nominal value. Note 10: Range of capacitor value for which the device will remain stable. This electrical specification is guaranteed by design. Note 11: Range of capacitor ESR values for which the device will remain stable. This electrical specification is guaranteed by design. Note 12: The built-in thermal shut-down of the LDO is also used to put all A and B outputs in tri-state mode. Note 13: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112). Note 14: Unused inputs must be terminated. Note 15: This electrical specification is guaranteed by design. Note 16: The SD/MMC card specification calls for a total of 30 pF capacitance. A load of 15 pF is internal to the LP3929, so the external load capacitance on the B side should comprise the remaining (15 pF or less). Timing Diagrams www.national.com 8 LP3929 Timing Diagrams (Continued) 20186805 FIGURE 1. A to B Timing Diagram (propagation delay, skew) 20186806 FIGURE 2. Output Transition Time (A and B Side) 9 www.national.com LP3929 Timing Diagrams (Continued) 20186807 FIGURE 3. B to A Direction (37 MHz Example) Typical Performance Characteristics CVDDB = 1 µF, VBAT = 3.85 V, VDDA = 1.8 V, TA = 25˚C. ASIP / EMI Filter Response Unless otherwise specified: CVBAT = 1 µF, CVDDA = 1 µF, Power Supply Rejection Ration (VBAT = 3.85V) 20186809 20186808 www.national.com 10 LP3929 Application Information EXTERNAL CAPACITORS Like any low-dropout regulator, the LP3929 requires external capacitors for regulator stability. The LP3929 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. INPUT CAPACITOR An input capacitance of 1 µF is required between the LP3929 VBAT pin and ground (the amount of the capacitance may be increased without limit). This capacitor must be located a distance of not more than 1 cm from the VBAT pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR on the input capacitor, but tolerance, bias voltage and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will be 1 µF over the entire operating conditions. FAST ON-TIME The LP3929 utilizes a speed up circuitry to ramp up the internal VREF voltage to its final value to achieve a fast output turn on time. CAPACITOR CHARACTERISTICS The LP3929 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the range of 1 µF to 4.7 µF range, ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR requirement for stability by the LP3929. The ceramic capacitor’s capacitance can vary with temperature. Most large value ceramic capacitors (2.2 µF) are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by more than 50% as the temperature goes from 25˚C to 85˚C. A better choice for temperature coefficient in ceramic capacitor is X7R, which holds the capacitance within ± 15%. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 1 µF to 4.7 µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25˚C down to −40˚C, so some guard band must be allowed. OUTPUT CAPACITOR The LP3929 is designed specifically to work with very small ceramic output capacitors, any ceramic capacitor (dielectric types Z5U, Y5V or X7R) in 1.0 µF to 2.2 µF range with 5 mΩ to 500 mΩ ESR range is suitable in the LP3929 application circuit. It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for reasons of size and cost (see section Capacitor Characteristics). The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range. The output capacitor should be placed as near as possible to the VDDB pin. NO-LOAD STABILITY The LDO of the LP3929 will remain stable and in regulation with no external load connected to the LDO output VDDB. This is especially important in CMOS RAM keep-alive applications. MICRO SMD ASSEMBLY For assembly recommendations of micro SMD package please refer to National Semiconductor Application Note AN-1112. MICRO SMD LIGHT SENSITIVITY Exposing the micro SMD device to direct sunlight will cause misoperation of the device. Light sources such as Halogen lamps can effect electrical performance if brought near to the device. The wavelengths which have most detrimental effect are reds and infra-reds, which means that the fluorescent lighting used inside most buildings has very little effect on performance. 11 www.national.com LP3929 High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator and Line Protection Physical Dimensions inches (millimeters) unless otherwise noted micro SMD, 24 Bump NS Package Number: TME24AAA The dimensions for X1, X2 and X3 are as follows: X1 = 2.015mm ± 30µm X2 = 2.015mm ± 30µm X3 = 0.600mm ± 75µm National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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