LP55271TLX

LP55271 Tiny LED Driver for Camera Flash and 4 LEDs with I2C Programmability, Connectivity Test and Audio Synchronization September 2006 LP55271 Tiny LED Driver for Camera Flash and 4 LEDs with I2C Programmability, Connectivity Test and Audio Synchronization General Description The LP55271 is a lighting management unit for handheld devices with I2C compatible control interface. The LP55271 has a step-up DC/DC converter with high current output and it drives display and keypad backlights and powers the camera flash LED. In addition the DC/DC converter has the output current to power for example an audio amplifier simultaneously. The chip has four 8-bit programmable high efficiency constant current LED drivers and a FLASH LED driver. Built-in audio synchronization feature allows the user to synchronize one of the LEDs to audio input. The LP55271 has an integrated 370 mA flash driver with a safety stop feature and 46 mA torch mode. An external enable pin is provided for the synchronizing the flash with the camera action. An external software independent test interface provides a fast way to find a broken path or short on LED circuits. Very small microSMD package together with minimum number of external components is a best fit for handheld devices. Features n High current boost DC-DC converter (up to 1A output current) n Programmable boost output voltage n 370 mA flash LED constant current driver with low tolerance and a safety circuit n Synchronization pin for the flash timing n Two single-ended audio inputs with gain control n Four constant current 15 mA LED drivers with 8-bit programmable brightness control n Audio synchronization feature n I2C compatible control interface n Built-in LED connectivity test to maximize manufacturing yield n Small microSMD-30 package (2.5 mm x 3.0 mm x 0.6 mm) Applications n Camera FLASH, funlight and backlight driving in battery powered devices Typical Application 20202401 © 2006 National Semiconductor Corporation DS202024 www.national.com LP55271 Connection Diagrams and Package Mark Information CONNECTION DIAGRAMS microSMD-30 package, 2.466 x 2.974 x 0.60 mm body size, 0.5 mm pitch NS Package Number TLA3011A 20202402 Top View 20202403 Bottom View PACKAGE MARK 20202404 Top View XY — Date Code TT — Die Traceability D55B — Product Identification ORDERING INFORMATION Order Number LP55271TL LP55271TLX Package Marking D55B D55B Supplied As TNR 250 TNR 3000 Spec/Flow NoPB NoPB www.national.com 2 LP55271 Connection Diagrams and Package Mark Information Pin Descriptions Pin D3 A1 F5 E5 D5 B5 A5 B4 A4 F2 F3 D2 C1 B1 F4 E4 C5 F1 A2 D1 C3 E1 A3 B3 E2 E3 D4 C4 C2 B2 Name VDD1 VDD2 SW1 SW2 FB LED1 LED2 LED3 LED4 FLASH GNDC RT VREF VDDA GND_SW1 GND_SW2 GND_LED GND_FLASH IFLASH GNDA GND VDD_IO NRST SCL SDA FLASH_SYNC T2 T1 ASE1 ASE2 Type P P A A A O O O O O G A A P G G G G A G G P DI DI OD DI DO DI AI AI Supply Voltage Supply Voltage Boost Converter Switch Boost Converter Switch Boost Converter Feedback LED1 Driver Output LED2 Driver Output LED3 Driver Output LED4 Driver Output Flash LED Driver Output Ground for Core Circuitry Oscillator Frequency Setting Reference Voltage Internal LDO Boost Converter Ground Boost Converter Ground LEDs 1 to 4 Driver Ground Connection Flash Driver Ground Connection Resistor for Flash Current Setting Analog Ground Connection Ground Supply Voltage for Digital Interface Low Active Reset I2C Compatible Interface Clock Signal I2C Compatible Interface Data Signal FLASH LED Control Test Pin (Result) Test Pin (Clock) Audio Input Audio Input (Continued) Description A: Analog Pin D: Digital Pin G: Ground Pin P: Power Pin I: Input Pin I/O: Input/Output Pin O: Output Pin OD: Open Drain Pin 3 www.national.com LP55271 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Voltage on power pins (VDD1,2) Voltage on analog pins Voltage on input/output pins V(all other pins): Voltage to GND I(VREF) I(FLASH) Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature (Reflow soldering, 3 times) (Note 4) -0.3V to +6.0V -0.3V to VDD1,2+0.3V with 6.0V max -0.3V to VDD1,2+0.3V with 6.0V max -0.3V to 6.0V 10 µA 500 mA Internally Limited 125 C -65oC to +150oC 260oC o ESD Rating (Note 5) Human Body Model 2 kV Operating Ratings (Note 1), (Note 2) Voltage on power pins (VDD1,2) Voltage on ASE1, ASE2 VDD_IO Junction Temperature (TJ) Range Ambient Temperature (TA) Range (Note 6) 3.0 to 5.5V 0V to 1.6V 1.65V to VDD1 -30oC to +125oC -30oC to +85oC Thermal Properties Junction-to-Ambient Thermal Resistance (θJA), TLA3011A Package (Note 7) 60 - 100oC/W Electrical Characteristics (Notes 2, 8) Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDD_IO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH. (Note 9) Symbol ISHUT DOWN Parameter Current of VDD1 + VDD2 pins + Leakage Current of SW1, SW2, LED1 to 4 and FLASH Active Mode Supply Current (VDD1 + VDD2 current) No load supply current (VDD1 + VDD2 current) VDD_IO Standby Supply current Condition Voltage on VDD_IO = 0V, NRST = L, NSTBY(bit) = L NRST = H, NSTBY(bit) = H, no load, EN_BOOST(bit) = L, SCL, SDA = H NSTBY(bit) = H, EN_BOOST(bit) = H, SCL, SDA, NRST = H, AUTOLOAD_EN(bit) = L NSTBY(bit) = L IVDDA = 1 mA -4% 2,8V Min Typ 1 Max 5 Units µA IDD IDD 350 850 µA µA IVDDIO VDDA 1 +4% µA V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160oC (typ.) and disengages at TJ = 140oC (typ.). Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip Scale Package. Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. MIL-STD-883 3015.7 Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125oC), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX). Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. www.national.com 4 LP55271 LP55271 Block Diagram 20202405 5 www.national.com LP55271 Modes of Operation 20202406 In the reset mode all the internal registers are reset to the default values. Reset is entered always if input NRST is LOW or internal Power On Reset (POR) is active. Power on reset will activate during the chip startup or when the supply voltage VDD2 falls below 1.5V. Once VDD2 rises above 1.5V, POR will inactivate and the chip will continue to the STANDBY mode. NSTBY control bit is low after POR by default. STANDBY: The standby mode is entered if the register bit NSTBY is LOW and reset is not active. This is the low power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective immediately after start up. STARTUP: When NSTBY bit is written high, the internal startup sequence powers up all the needed internal blocks (VREF, Oscillator, etc.). To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. If the chip temperature rises too high, the thermal shutdown (TSD) disables the chip operation and startup mode is entered until no thermal shutdown event is present. BOOST STARTUP: Soft-start for boost output is generated in the boost startup mode. The boost output is raised in a low current PWM mode during the 10 ms delay generated by the state-machine. The boost startup is entered from internal startup sequence if EN_BOOST is HIGH or from normal mode when EN_BOOST is written HIGH. NORMAL: During normal mode the user controls the chip using the Control Registers. The registers can be written in any sequence and any number of bits can be altered in a register in one write. RESET: www.national.com 6 LP55271 Magnetic Boost DC/DC Converter The LP55271 boost DC/DC converter generates a 4.00 – 5.40V output voltage to drive the LEDs from a single Li-Ion battery (3.0V to 4.5V). The output voltage is controlled with a 4-bit register in 8 steps. The converter is a magnetic switching PWM mode DC/DC converter with a current limit. The converter has 2.0 MHz / 1.0 MHz selectable switching frequency operation, when the timing resistor RT is 82 kΩ. The LP55271 boost converter uses pulse-skipping elimination method to stabilize the noise spectrum. Even with light load or no load a minimum length current pulse is fed to the inductor. An internal active load is used to remove the excess charge from the output capacitor when needed. The topology of the magnetic boost converter is called CPM control, current programmed mode, where the inductor current is measured and controlled with the feedback. The output voltage control changes the resistor divider in the feedback loop. The following figure shows the boost topology with the protection circuitry. Four different protection schemes are implemented: 1. Over voltage protection, limits the maximum output voltage. — Keeps the output below breakdown voltage. — Prevents boost operation if battery voltage is much higher than desired output. 2. Over current protection, limits the maximum inductor current. — Voltage over switching NMOS is monitored; too high voltages turn the switch off. 3. 4. Feedback (FB) protection for no connection. Duty cycle limiting, done with digital control. 20202477 Boost Converter Topology 7 www.national.com LP55271 Magnetic Boost DC/DC Converter (Continued) MAGNETIC BOOST DC/DC CONVERTER ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH. (Note 9) Symbol ILOAD VOUT Parameter Load Current (Note 10) Output Voltage Accuracy (FB pin) Output Voltage (FB Pin) RDSON fPWF Switch ON Resistance PWM Mode Switching Frequency Frequency Accuracy tPULSE tSTARTUP ICL_OUT Switch Pulse Minimum Width Startup Time SW1 + SW2 current limit Conditions 3.2V ≤ VIN ≤ 4.5V VOUT = 5.0V 3.2V ≤ VIN ≤ 4.5V VOUT (target value) = 5.0V, active load off 3.0V ≤ VIN ≤ (5.0V+VSCHOTTKY) active load off VIN > (5.0V + VSCHOTTKY) VIN = 3.6V, ISW = 1.0A RT = 82 kΩ FREQ_SEL (bit) = 1 FREQ_SEL (bit) = 0 3.2V ≤ VDD1,2 ≤ 5.0V RT = 82 kΩ no load −6 -9 −5 Min Typ Max 670 +5 Units mA % 5.0 VIN - VSCHOTTKY 0.20 2.0 1.0 0.4 V Ω MHz ±3 25 10 1.7 +6 +9 % ns ms A Note 10: Specified currents are the worst case currents. If input voltage is larger or output voltage is smaller, current can be increased according to graph "Boost Maximum Output Current". BOOST STANDBY MODE User can set the boost converter to STANDBY mode by writing the register bit EN_BOOST low when there is no load to avoid idle current consumption. When EN_BOOST is written high, the converter starts in low current PWM (Pulse Width Modulation) mode for 10 ms and then goes to normal PWM mode. BOOST CONTROL REGISTERS User can control the boost output voltage and the switching frequency according to the following tables. Boost Output Voltage [3:0] Register 0000 0001 0011 0111 1000 1001 1011 1111 Boost Output Voltage (V) (Typical) 4.00 4.20 4.40 4.60 default 4.80 5.00 5.20 5.40 FREQ_SEL Bit 0 1 Boost Switching Frequency (Typical) 1.0 MHz default 2.0 MHz www.national.com 8 LP55271 Boost Converter Typical Performance Characteristics TJ = 25oC. Unless otherwise noted, typical performance characteristics apply to the LP55271 Block Diagram with: VIN = 3.6V, VOUT = 5.0V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDD_IO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH (Note 9). Boost Converter Efficiency Boost Typical Waveforms at 100 mA Load 20202479 20202480 Battery Current vs Voltage Boost Frequency vs RT Resistor 20202481 20202482 Boost Line Regulation 3.0V - 3.6V Boost Startup to 5.4V with no Load 20202483 20202484 9 www.national.com LP55271 Boost Converter Typical Performance Characteristics Boost Load Transient Response, 50 mA to 100 mA (Continued) Boost Maximum Output Current 20202485 20202498 www.national.com 10 LP55271 Flash Driver LP55271 has an internal constant current driver that is capable for sinking low (46 mA) and high (370 mA) current mainly targeted for torch and flash LED in camera phone applications. 370 mA flash driver can be hardware or software enabled. Flash safety function prevents hardware damages due to possible overheating when the flash has been stuck on because of a hardware, software or user error. Flash safety counter starts counting when the flash is activated and disables the flash automatically when the preFlash LED Control (X = don’t care) EN_TORCH bit 0 1 X EN_FLASH bit 0 0 1 defined 1.0s or 2.0s time limit is reached. Flash is activated with FLASH_SYNC bit or FLASH_SYNC pin, as defined in the table below. Safety time limit is defined by SAFETY_TIME bit. (Time limit is 2.0s if SAFETY_TIME bit is low and 1.0s if the bit is high.) Flash driver currents — both torch and flash — are set with external resistor R F. The flash current is 480/RF amperes and the torch current is 60/RF amperes. User should not use lower resistance value than 1200Ω. FLASH_SYNC bit or pin X X Change from LOW to HIGH to engage; from HIGH to LOW to disengage SAFETY_TIME bit X X 0 for 2.0 seconds; 1 for 1.0 second Flash LED Action Off Torch Flash Flash Programming Example Address 00H 00H 00H 00H Data 8FH 9FH FFH BFH Function Sets safety time to 1.0s. In this example LED1 to LED4 are enabled. Enables torch. Activates FLASH. EN_FLASH bit and FLASH_SYNC bit are written simultaneously because EN_FLASH disables torch. Disables FLASH. If FLASH is disabled by safety time, FLASH_SYNC bit needs to be written to 0 before next FLASH. FLASH DRIVER ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85 oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH, RF = 1300Ω Symbol IFLASH ITORCH ILEAKAGE tFLASH VSAT Parameter Flash Mode Sink Current (Note 8) Torch Mode Sink Current (Note 8) Flash Driver Leakage Current Flash Turn-On Time (Note 11) Saturation Voltage 3.0V ≤ VIN ≤ 5.5V, Current Decreased to 95% of the Maximum Sink Current -9 Condition 3.0V ≤ VIN ≤ 5.5V, VFLASH = 1.0V 3.0V ≤ VIN ≤ 5.5V VFB = 5.0V Min -7.5 46 0.1 20 550 Typ 370 +7.5 Max Units mA % mA µA µs mV tSAFETY Safety Time Accuracy +9 % Note 11: Flash turn-on time is measured from the moment the flash is activated until the flash current crosses 90% of its target value. 11 www.national.com LP55271 Constant Current Sink Outputs LED1, LED2, LED3, LED4 LP55271 has four independent backlight/keypad LED drivers. All the drivers are regulated constant current sinks. LED currents are controlled by 8-bit current mode DACs. Every driver can be controlled in two ways: 1. Brightness control with constant current drivers 2. Direct ON/OFF control. The current is pre-set by 8-bit current mode DAC. In addition, LED1 driver can be synchronized to audio input signal amplitude. By using brightness control user can set brightness of every single LED by using 8-bit brightness control registers. If analog audio is available on system the user can use audio synchronization for synchronizing LED1 to the music. Direct ON/OFF control is mainly for switching LEDs on and off. LED Control Register (00 hex) has control bits for direct on/off control of all the LEDs. Note that the LEDs have to be turned on in order to control them with audio synchronization (LED1 only) or brightness control. The brightness is programmed as described in the following. ILED = n x (15 mA / 255) where: n = LED[7:0] (8-bit) step = 15 mA / 255 ≈ 0.05882 mA For example if 13.2 mA is required for driver current: n = 13.2 mA / (15 mA / 255) ≈ 224 224 = 1110 0000, E0 hex LED1 to LED4 Brightness Control LED1[7:0], LED2[7:0], LED3[7:0] and LED4[7:0] Registers 0000 0000 0000 0001 0000 0010 Driver Current, mA (typical) 0 0.059 0.118 • 1110 0000 • 1111 1110 1111 1111 • 13.176 • 14.941 15 LED1 TO LED4 DRIVERS ELECTRICAL CHARACTERISTICS Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH. (Note 9) Symbol IMAX ILEAKAGE ILED IMATCH VSAT Parameter Maximum Sink Current Leakage Current Current Tolerance Sink Current Matching Between LED 1 to 4 Saturation Voltage VFB = 5.0V ISINK = 13.2 mA (target value) -7 ISINK = 13.2 mA 3.0V ≤ VIN ≤ 5.5V, Current Decreased to 95% of the Maximum Sink Current 1 150 230 Condition Min Typ 15 0.03 13.2 +7 Max Units mA µA mA % % mV Note: Sink current matching is the maximum difference from the average. www.national.com 12 LP55271 Audio Synchronization The LED1 output can be synchronized to incoming audio signal with Audio Synchronization feature. Audio Synchronization synchronizes LED1 based on input signal’s peak amplitude. Programmable gain and automatic gain control function are also available for adjustment of input signal amplitude to light response. Control of LED1 brightness refreshing frequency is done with four different frequency configurations. The digitized input signal has a DC component that is removed by a digital DC-remover. The DCremover is a high-pass filter where corner frequency is user selectable by using DC_FREQ bit. LP55271 has 2-channel audio (stereo) input for audio synchronization, as shown in the figure below. The inputs accept signals in the range of 0V to 1.6V peak-to-peak and these signals are mixed into a single wave so that they can be filtered simultaneously. LP55271 audio synchronization is mainly done digitally and it consists following signal path blocks (see figure below). • Input buffer • AD converter • Automatic Gain Control (AGC) and manually programmable gain • Peak detector Automatic Gain Control (AGC) adjusts the input signal to suitable range automatically. User can disable AGC and the gain can be set manually with programmable gain. Audio synchronization is based on peak detection method. 20202416 Audio Synchronization Input Electrical Parameters Symbol ZIN AIN Parameter Input Impedance of ASE1, ASE2 ASE1, ASE2 Audio Input Level Range (peak-to-peak) Min input level needs maximum gain; Max input level for minimum gain. Conditions Min 10 0 Typ 15 1600 Max Units kΩ mV CONTROL OF AUDIO SYNCHRONIZATION The following table describes the controls required for audio synchronization. LED1 brightness control through serial interface is not available when audio synchronization is enabled. Audio Synchronization Control EN_SYNC EN_AGC GAIN_SEL[2:0] SPEED_CTRL[1:0] THRESHOLD[3:0] DC_FREQ Audio synchronization enabled. Set EN_SYNC = 1 to enable audio synchronization or 0 to disable. Automatic gain control. Set EN_AGC = 1 to enable automatic control or 0 to disable. When EN_AGC is disabled, the audio input signal gain value is defined by GAIN_SEL. Input signal gain control. Gain has a range from 0 dB to -46 dB. Control for refreshing frequency. Sets the typical refreshing rate for the LED1 output. Control for the audio input threshold. Sets the typical threshold for the audio inputs signals. May be needed if there is noise on the audio lines. Control for the high-pass filter corner frequency. 0 = 80 Hz 1 = 510 Hz 13 www.national.com LP55271 Audio Synchronization Audio Input Threshold Setting Threshold[3:0] 0000 0001 0010 * * 1110 1111 (Continued) Input Signal Gain Control GAIN_SEL[2:0] 000 001 010 011 100 101 110 111 Refreshing Frequency SPEED_CTRL[1:0] 00 01 10 11 Refreshing Rate Hz FASTEST 15 7.6 3.8 Gain dB 0 -6 -12 -18 -24 -31 -37 -46 Threshold Level, mV (typical) Disabled 0.2 0.4 * * 2.5 2.7 Typical Gain Values vs. Audio Input Amplitude Audio Input Amplitude mVP-P 0 to 10 0 to 20 0 to 40 1 to 85 3 to 170 5 to 400 10 to 800 20 to 1600 Gain Value dB 0 -6 -12 -18 -24 -31 -37 -46 Logic Interface Characteristics Limits in standard typeface are for TJ = 25oC. Limits in boldface type apply over the operating ambient temperature range (-30oC < TA < +85oC). Unless otherwise noted, specifications apply to the LP55271 Block Diagram with: VIN = 3.6V, CIN = 10 µF, COUT1 = 10 µF, COUT2 = 10 µF, CVDDIO = 100 nF, CVREF = 100 nF, CVDDA = 4.7 µF, CVDD1 = 100 nF, CVDD2 = 100 nF, L1 = 4.7 µH (Note 9) Symbol VIL VIH II fSCL VIL VIH II tNRST VOL IL Parameter Input Low Level Input High Level Input Current SCL Pin Clock Frequency Input Low Level Input High Level Input Current Reset Pulse Width Output Low Level Output leakage current IOUT = 3 mA VOUT = 2.8V VDD_IO = 1.65V to VDD1,2 1.2 -1.0 10 0.3 0.5 1.0 1.0 Condition VDD_IO = 1.65V to VDD1,2 0.8 x VDD_IO -1.0 400 0.5 1.0 Min Typical Max 0.2 x VDD_IO Unit V V µA kHz V V µA µs V µA Logic Inputs SCL and FLASH_SYNC Logic Input NRST Logic Input/Output SDA www.national.com 14 LP55271 I2C Compatible Interface I2C SIGNALS The SCL pin is used for the I2C clock and the SDA pin is used for bidirectional data transfer. Both these signals need a pull-up resistor according to I2C specification. The values of the pull-up resistors are determined by the capacitance of the bus (typ. ~1.8 kΩ). Signal timing specifications are shown in table I2C Timing Parameters. I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can only be changed when CLK is LOW. TRANSFERRING DATA Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been received. After the START condition, the I2C master sends a chip address. This address is seven bits long followed by an eighth bit which is a data direction bit (R/W). The LP55271 address is 4C hex. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected register. When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the I2C Read Cycle waveform. 20202449 I2C Signals: Data Validity 20202451 I2C START AND STOP CONDITIONS START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data transmission, I2C master can generate repeated START conditions. First START and repeated START conditions are equivalent, function-wise. I2C Chip Address 4C hex for LP55271 20202450 I2C Start and Stop Conditions 15 www.national.com LP55271 I2C Compatible Interface (Continued) 20202417 w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = chip address, 4C hex for LP55271. I2C Write Cycle 20202418 I2C Read Cycle 20202454 I2C Timing Diagram I2C TIMING PARAMETERS (VDD1,2 = 3.0 to 4.5V, VDDIO = 1.65V to VDD1,2) Symbol 1 2 3 4 5 5 6 7 8 9 Parameter Hold Time (repeated) START Condition Clock Low Time Clock High Time Setup Time for a Repeated START Condition Data Hold Time (Output direction, delay generated by LP55271) Data Hold Time (Input direction) Data Setup Time Rise Time of SDA and SCL Fall Time of SDA and SCL Set-up Time for STOP condition Limit Min 0.6 1.3 600 600 300 0 100 20+0.1Cb 15+0.1Cb 600 300 300 900 900 Max Units µs µs ns ns ns ns ns ns ns ns www.national.com 16 LP55271 I2C Compatible Interface 10 Cb (Continued) 1.3 10 200 µs pF Bus Free Time between a STOP and a START Condition Capacitive Load for Each Bus Line NOTE: Data guaranteed by design Test Interface The test bus can be controlled externally or internally. For the external control, the LP55271 pins VDD1,2 only need to be powered. External control is independent on status of NRST and VDDIO pins. T1 is an input and it has an internal 6 kΩ pull-down resistor. T2 is an output line for the test result with an internal 200 kΩ pull-down resistor. When T1 is low, T2 is always pulled down; when T1 is high, T2 is indicating the result of the test. 20202419 High Level Schematic Representation of the Test Interface The device is capable of detecting a defective unit in three cases: • Production test 1: The LP55271 is assembled on a printed wiring board (PWB), but there is no LEDs connected on current sink outputs. An external 4.2V test voltage is supplied on the VDD1 and VDD2 pins, from which follows that the reset operating mode is entered with POR. Test pin T1 is pulled high. The chip will send an acknowledge “1” onto the T2 pin if the chip is in working order; otherwise T2 stays low (0). Refer to Test Interface Timing Diagram. • Production test 2: The LP55271 is assembled on a PWB with the external components shown in LP55271 Block Diagram. 4.2V voltage is connected to VDD1, VDD2 and FB pins (see the figure above), from which follows that the reset operating mode is entered with POR. Test pin T1 is pulled high. The chip will send an acknowledge • “1” onto the T2 pin if the chip is in working order; otherwise T2 stays low (0). If the ACK is “1”, a repetitive test pattern “0-1-0-1-0-1-0-1-0-1-0-1” is applied to T1 pin and if the LED corresponding the pattern (see Test Interface Timing Diagram) is connected properly T2 gives “1”, otherwise T2 stays low. The last “1” disengages the test. Field test: Build-in self-test through the I2C compatible control interface. The LP55271 is enabled (NSTBY(bit) = 1, EN_BOOST(bit) = 1) and external test pins T1 and T2 are disconnected. The result can be read through the I2C compatible control interface. LED test is enabled by writing to address 0Ch hex data 01h. Result can be read from the same address during the next I2C cycle. Note: I2C compatible interface clock signal controls the timing of the test procedure. For that reason the clock signal frequency should be 50 kHz or less during the build-in self-test. 17 www.national.com LP55271 Test Interface (Continued) 20202420 Test Interface Timing Diagram Test Interface Timing Parameters Limit Symbol 1 2 3 4 5 NOTE: Data guaranteed by design Condition VDD1,2 = 4.2V Parameter Setup Time after VDD1,2 = 4.2V Clock High Time Clock Low Time Test Result Settling Time Data Hold Time Min 1 200 200 Max Units ms µs µs 10 0 10 µs ns Test Interface Characteristics Limits in standard typeface are for TJ = 25oC. Symbol VIL VIH VOL VOH Parameter Input Low Level Input High Level Output Low Level Output High Level VDD1,2 = 4.2V, IOUT = 3 mA (pull-up current) VDD1,2 = 4.2V, IOUT = -3 mA (pull-down current) VDD1,2 = 4.2V Production test cases VDD1,2 = 4.2V VOUT = 3.9V to 4.2V Field test cases VDD1,2 = 3.0V to 4.2V VOUT = 5.0V ± 5% VDD1,2 - 0,5 Condition VDD1,2 = 4.2V 1.2 0.3 3.9 0.5 Min Typ Max 0.5 Units V V V V Logic Input T1 Logic Output T2 Internal Current Sink ISINK VPASS1 VPASS2 VPASS3 VPASS4 Sink Current Voltage Over the Internal Current Sink; Low Level Voltage Over the Internal Current Sink; High Level Voltage Over the Internal Current Sink; Low Level Voltage Over the Internal Current Sink; High Level 500 0.10 -50 2.90 -10 0.40 -30 3.95 -10 +10 +30 +10 +50 µA V % V % V % V % Connectivity Test Pass Range NOTE: Data guaranteed by design www.national.com 18 LP55271 Recommended External Components OUTPUT CAPACITOR, COUT1, COUT2 The output capacitors COUT1, COUT2 directly affect the magnitude of the output ripple voltage. In general, the higher the value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best choice. At the lighter loads, the low ESR ceramics offer a much lower VOUT ripple that the higher ESR tantalums of the same value. At the higher loads, the ceramics offer a slightly lower VOUT ripple magnitude than the tantalums of the same value. However, the dv/dt of the VOUT ripple with the ceramics is much lower that the tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V is recommended Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction with the increased applied voltage. The capacitance value can fall to below half of the nominal capacitance. Too low output capacitance can make the boost converter unstable. INPUT CAPACITOR, CIN The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V or greater is recommended. OUTPUT DIODE, D1 The output diode for a boost converter must be chosen correctly depending on the output voltage and the output current. The diode must be rated for a reverse voltage Table List of Recommended External Components Symbol CVDD1 CVDD2 COUT1,2 CIN CVDDIO CVDDA C1,2 RT RF CVREF L1 D1 Symbol Explanation VDD1 Bypass Capacitor VDD2 Bypass Capacitor Output Capacitors from FB to GND Input Capacitor from Battery Voltage to GND VDD_IO Bypass Capacitor VDDA Bypass Capacitor Audio Input Capacitors Oscillator Frequency Bias Resistor Flash Current Set Resistor for 370 mA Sink Current Reference Voltage Capacitor, between VREF and GND Boost Converter Inductor Rectifying Diode, VF @ maxload Flash LED LED1 to LED4 greater than the output voltage used. The average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current (~1.7A at maximum load). A Schottky diode should be used for the output diode. Schottky diodes with a low forward voltage drop (VF) and fast switching speeds are ideal for increasing efficiency in portable applications. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery times cause the efficiency and the load regulation to suffer. In Schottky barrier diodes reverse leakage current increases quickly with the junction temperature. Therefore, reverse power dissipation and the possibility of thermal runaway has to be considered when operating under high temperature conditions. Examples of suitable diodes are Diodes Incorporated type DFLS220L, ON Semiconductor type MBRA210LT3 and Philips type PMEG1020. INDUCTOR, L1 The LP55271 high switching frequency enables the use of the small surface mount inductor. A 4.7 µH shielded inductor is suggested for 2 MHz switching frequency. The inductor should have a saturation current rating higher than the peak current it will experience during circuit operation (~1.7A at maximum load). Less than 300 mΩ ESR is suggested for high efficiency. Open core inductors cause flux linkage with circuit components and interfere with the normal operation of the circuit. This should be avoided. For high efficiency, choose an inductor with a high frequency core material such as ferrite to reduce the core losses. To minimize radiated noise, use a toroid, pot core or shielded core inductor. The inductor should be connected to the SW1 and SW2 pins as close to the IC as possible. Example of a suitable inductor is TDK type VLCF5020T-4R7N1R7-1. Value 100 100 2 x 10 µF ± 10% 10 ± 10% 100 4.7 47 82 1300 100 4.7 0.35 User defined Unit nF nF µF µF nF µF nF kΩ Ω nF µH V Type Ceramic, X5R Ceramic, X5R Ceramic, X5R, 10V Ceramic, X5R, 10V Ceramic, X5R Ceramic, X5R, 6.3V Ceramic, X5R 1% 1% Ceramic, X5R Shielded, low ESR, ISAT ~1.7A Schottky diode 19 www.national.com LP55271 LP55271 Control Registers and Default Values D7 safety_time 0 led1[7] 0 led2[7] 0 led3[7] 0 led4[7] 0 nstby 0 led1_ok r/o r/o r/o led2_ok led3_ok 0 1 led4_ok r/o boost[3] 0 gain_sel[2] 0 threshold[3] 0 0 1 threshold[2] threshold[1] 0 0 gain_sel[1] gain_sel[0] dc_freq 0 threshold[0] 1 en_agc 0 en_boost 0 0 0 0 en_autoload led4[6] led4[5] led4[4] led4[3] 0 0 0 0 led3[6] led3[5] led3[4] led3[3] 0 led4[2] 0 freq_sel 0 flashled_ok r/o boost[2] 1 en_sync 0 boost[1] 1 speed_ctrl[1] 0 en_test 0 boost[0] 1 speed_ctrl[2] 0 0 0 0 0 0 led3[2] led2[6] led2[5] led2[4] led2[3] led2[2] 0 0 0 0 0 led1[6] led1[5] led1[4] led1[3] led1[2] 0 0 0 0 0 0 led1[1] 0 led2[1] 0 led3[1] 0 led4[1] 0 flash_sync en_flash en_torch en_led1 en_led2 en_led3 D6 D5 D4 D3 D2 D1 D0 en_led4 0 led1[0] 0 led2[0] 0 led3[0] 0 led4[0] 0 www.national.com ADDR (HEX) REGISTER 00 LED Control Register 01 LED1 02 LED2 03 LED3 04 LED4 0B ENABLES 0C LED Test Control 0D Boost Output 20 2A Audio Sync Control1 2B Audio Sync Control2 r/o = Read Only LP55271 Tiny LED Driver for Camera Flash and 4 LEDs with I2C Programmability, Connectivity Test and Audio Synchronization Physical Dimensions inches (millimeters) unless otherwise noted The dimension for X1, X2 and X3 are as given: • X1 = 2.466 mm ± 0.03 mm • X2 = 2.974 mm ± 0.03 mm • X3 = 0.60 mm ± 0.075 mm microSMD-30 NS Package Number TLA3011A See National Semiconductor Application Note 1112 Micro SMD Wafer Level Chip Scale Package for PCB design and assembly instructions. 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