LP55281TLX

LP55281 Quad RGB Driver June 2007 LP55281 Quad RGB Driver General Description LP55281 is a quad RGB LED driver for handheld devices. It can drive 4 RGB LED sets and a single fun light LED. The boost DC-DC converter drives high current loads with high efficiency. The RGB driver can drive individual color LEDs or RGB LEDs powered from boost output or external supply. Built-in audio synchronization feature allows user to synchronize the fun light LED to audio inputs. The flexible SPI/I2C interface allows easy control of LP55281. Small Micro SMD or Micro SMDxt package together with minimum number of external components is a best fit for handheld devices. LP55281 has also a LED test feature, which can be used for example in production for checking the LED connections. Features ■ ■ ■ ■ ■ ■ ■ Audio synchronization for a single fun light LED 4 PWM controlled RGB LED drivers High efficiency Boost DC-DC converter SPI/I2C compatible interface 2 addresses in I2C compatible interface LED connectivity test through the serial interface Small 36-bump Micro SMD (3 mm x 3 mm x 0.6 mm) or 36-bump Micro SMDxt package (3 mm x 3 mm x 0.65 mm) Applications ■ Cellular Phones ■ PDAs, MP3 players Typical Application 20201101 National Semiconductor® is a registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 202011 www.national.com LP55281 Connection Diagram 20201171 36-bump Micro SMD package, 3 * 3 * 0.6 mm body size, 0.5 mm pitch NS Package Number TLA36AAA 36-bump Micro SMDxt package, 3 * 3 * 0.65 mm body size, 0.5 mm pitch NS Package Number RLA36AAA Package Mark 20201196 36-bump Micro SMD package, 3 * 3 * 0.6 mm body size, 0.5 mm pitch NS Package Number TLA36AAA 20201128 36-bump Micro SMDxt package, 3 * 3 * 0.65 mm body size, 0.5 mm pitch NS Package Number RLA36AAA Ordering Information Order Number LP55281TL LP55281TLX LP55281RL LP55281RLX Package Marking D56B D56B D61B D61B Supplied As TNR 250 TNR 1000 TNR250 TNR1000 Spec/Flow NoPB NoPB NoPB NoPB www.national.com 2 LP55281 Pin Descriptions Pin 6F 6E 6D 6C 6B 6A 5F 5E 5D 5C 5B 5A 4F 4E 4D 4C 4B 4A 3F 3E 3D 3C 3B 3A 2F 2E 2D 2C 2B 2A 1F 1E 1D 1C 1B 1A Name SW FB B3 R1 G1 B1 GND_SW R3 G3 SS/SDA IRGB GND_RGB1 GND_RGB2 GND ASE2 SI/A0 SO R2 NRST R4 VDD1 VDDIO SCK/SCL G2 ALED G4 ASE1 IRT IF_SEL B2 GND B4 GNDA VREF VDDA VDD2 Type Output Input Output Output Output Output Ground Output Output Logic Input/Output Input Ground Ground Ground Input Logic Input Logic Output Output Input Output Power Power Logic Input Output Output Output Input Input Logic Input Output Ground Output Ground Output Power Power Description Boost Converter Power Switch Boost Converter Feedback Blue LED 3 Output Red LED 1 Output Green LED 1 Output Blue LED 1 Output Power Switch Ground Red LED 3 Output Green LED 3 Output Slave Select (SPI), Serial Data In/Out (I2C) Bias Current Set Resistor for RGB Drivers Ground for RGB1-2 Currents Ground for RGB3-4 Currents Ground Audio Synchronization Input 2 Serial Input (SPI), Address Select (I2C) Serial Data Out (SPI) Red LED 2 Output Asynchronous Reset, Active Low Red LED 4 Output Supply Voltage Supply Voltage for Input/Output Buffers and Drivers Clock (SPI/I2C) Green LED 2 Output Audio Synchronized LED Output Green LED 4 Output Audio Synchronization Input 1 Oscillator Frequency Resistor Interface (SPI or I2C compatible) Selection (IF_SEL = 1 for SPI) Blue LED 2 Output Ground Blue LED 4 Output Ground for Analog Circuitry Reference Voltage Internal LDO Output Supply Voltage 3 www.national.com LP55281 Block Diagram 20201174 www.national.com 4 LP55281 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V (SW, FB, R1-4, G1-4, B1-4, -0.3V to +7.2V ALED (Notes 3, 4)) VDD1, VDD2, VDDIO, VDDA -0.3V to +6.0V Voltage on ASE1-2, IRT, -0.3V to VDD1 +0.3V with 6.0V IRGB, VREF max Voltage on Logic Pins -0.3V to VDDIO + 0.3V with 6.0V max V (all other pins): Voltage to -0.3V to +6.0V GND I (VREF) 10 µA I (R1-4, G1-4, B1-4) 100 mA Continuous Power Internally Limited Dissipation (Note 5) Junction Temperature (TJ150°C ) MAX Storage Temperature Range -65°C to +150°C Maximum Lead Temperature 260°C (Reflow soldering, 3 times) (Note 6) ESD Rating Human Body Model (Note 7) 2 kV (Notes 1, 2) 0 to 6.0V 2.7V to 5.5V 3.0V to 5.5V 2.7V to 2.9V 1.65V to VDD1 0.1V to VDDA - 0.1V 0 mA to 300 mA -30°C to +125°C -30°C to +85°C Operating Ratings VDD1,2 with internal LDO VDDA VDDIO Voltage on ASE1-2 V (SW, FB, R1-4, G1-4, B1-4, ALED) VDD1,2 with external LDO Recommended Load Current Junction Temperature (TJ) Range Ambient Temperature (TA) Range (Note 8) Thermal Properties Junction-to-Ambient Thermal Resistance (θJA), TLA36AAA Package (Note 9) 60°C/W Electrical Characteristics (Notes 2, 10) Limits in standard typeface are for TJ = 25°C. Limits in boldface type apply over the operating ambient temperature range (-30°C < TA < +85°C). Unless otherwise noted, specifications apply to the LP55281 Block Diagram with: VDD1 = VDD2 = 3.6V, VDDIO = 2.8V, CVDD = CVDDIO = 100 nF, COUT = CIN = 10 µF, CVDDA= 1 µF, CREF = 100 nF, L1 = 4.7 µH, RRGB = 8.2 kΩ and RRT = 82 kΩ (Note 11). Symbol IDD Parameter Condition Min Typ 1 Max 10 Units µA Standby supply NSTBY = L current (VDD1 + SCK = SS = SI = H VDD2 + leakage to NRST = L SW, FB, RGB1-4, ALED) No-Boost supply current (VDD1 + VDD2) No-load supply current (VDD1 + VDD2) NSTBY = H, EN_BOOST = L SCK = SS = SI = H Audio synchronization and LEDs OFF NSTBY = H, EN_BOOST = H, SCK = SS = SI = H Audio synchronization and LEDs OFF Autoload OFF 350 µA 0.6 mA Total RGB drivers EN_RGBx = H quiescent current (VDD1 + VDD2) ALED driver current (VDD1 + VDD2) Audio Synchronization current (VDD1 + VDD2) IDDIO VDDIO Standby Supply current VDDIO supply current ALED[7:0] = FFh ALED[7:0] = 00h Audio Synchronization ON VDD1,2 = 2.8V VDD1,2 = 3.6V NSTBY = L SCK = SS = SI = H 1 MHz SCK frequency in SPI mode, CL = 50 pF at SO pin 250 µA 180 0 390 700 µA µA µA µA 1 20 µA µA 5 www.national.com LP55281 VDDA Output voltage of internal LDO for analog parts Parameter Recommended Load Current (Note 12) -3% 2.80 +3% V MAGNETIC BOOST DC/DC CONVERTER ELECTRICAL CHARACTERISTICS Symbol ILOAD Condition 3.0V ≤ VIN VOUT = 5V 3.0V ≤ VIN VOUT = 4V VOUT Output Voltage 3.0V ≤ VIN ≤ VOUT - 0.5 Accuracy (FB pin) V OUT = 5V Output Voltage (FB pin) RDSON fBoost Switch ON resistance PWM mode switching frequency Frequency Accuracy tPULSE tSTARTUP ISW_MAX Switch pulse minimum width Startup time SW pin current limit Parameter R1-4, G1-4, B1-4 pin leakage current Maximum Recommended Sink Current Accuracy @ 15 mA Current mirror ratio RGB1-4 current mismatch fPWM RGB switching frequency Parameter Input Impedance of ASE1, ASE2 Condition 5.5V at measured pin 1 mA ≤ ILOAD ≤ 300 mA VIN > VOUT + VSCHOTTKY (Note 14) VDD1,2 = 3.0V, ISW = 0.5 A RT = 82 kΩ freq_sel[2:0] = 1XX 2.7V ≤ VDDA ≤ 2.9V RT = 82 kΩ ± 1% no load Boost startup from STANDBY (Note 13) 700 550 Min -7 -10 Min 0 0 -5 VIN Vschottky 0.4 2 0.8 Typ Max 300 400 +5 Units mA mA % V Ω MHz ±3 30 10 800 +7 +10 % ns ms 900 950 Max 1 mA RGB DRIVER ELECTRICAL CHARACTERISTICS (R1-4, G1-4, B1-4) Symbol ILEAKAGE Typ 0.1 Units µA IRGB Limited with external resistor RRGB 40 mA RRGB = 8.2 kΩ ± 1 % (Note 13) IRGB = 15 mA Accuracy defined by internal oscillator, frequency value selectable Condition (Note 13) Min 10 0 ±5 1 : 100 ±5 fPWM % % AUDIO SYNCHRONIZATION INPUT ELECTRICAL CHARACTERISTICS Symbol ZIN AIN Typ 15 1600 Max Units kΩ mV ASE1, ASE2 Min input level needs maximum gain; Max input level for Audio Input Level minimum gain Range (peak-topeak) Parameter Leakage current Condition VALED = 5.5V ALED DRIVER ELECTRICAL CHARACTERISTICS Symbol Ileakage Min Typ 0.03 Max 1 Units µA www.national.com 6 LP55281 IALED ALED current tolerance Parameter Input Low Level Input High Level Logic Input Current Clock Frequency IALED set to 13.2 mA 11.9 -10 Min 13.2 14.5 +10 Max 0.2*VDDIO mA % Units V V µA kHz MHz MHz LOGIC INTERFACE CHARACTERISTICS Symbol VIL VIH II fSCK/SCL Condition Typ Logic Input SS/SDA, SI/A0, SCK/SCL, IF_SEL 0.8*VDDIO -1.0 I2C SPI Mode, VDDIO > 1.8V (Note 13) SPI Mode, 1.65V ≤ VDDIO < 1.8V Logic Input NRST VIL VIH II tNRST VOL Input Low Level Input High Level Logic Input Current Reset Pulse Width Output Low Level ISO = 3 mA VDDIO > 1.8V ISO = 2 mA VOH 1.65V ≤ VDDIO < 1.8V Output High Level ISO = -3 mA VDDIO > 1.8V ISO = -2 mA IL Output Leakage Current VSO = 2.8V 1.65V ≤ VDDIO < 1.8V VDDIO 0.5 VDDIO 0.5 VDDIO 0.3 VDDIO 0.3 1.0 µA V 1.2 -1.0 10 0.3 0.3 0.5 0.5 1.0 0.5 V V µA µs V 1.0 400 13 5 Logic Output SO Logic Output SDA VOL Output Low Level ISDA = 3 mA 0.3 0.5 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins. Note 3: Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime. Note 4: Voltage tolerance of LP55281 above 6.0V relies on fact that VDD1 and VDD2 (2.8V) are available (ON) at all conditions. If VDD1 and VDD2 are not available (ON) at all conditions, National Semiconductor® does not guarantee any parameters or reliability for this device. Note 5: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and disengages at TJ = 140°C (typ.) Note 6: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip Scale Package or National Semiconductor Application Note AN1412 : Micro SMDxt Wafer Level Chip Scale Package. Note 7: The Human Body Model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. MIL-STD-883 3015.7 Note 8: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to-ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP - (θJA x PD-MAX). Note 9: Junction-to-Ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 10: Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 11: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics. Note 12: VDDA output is not recommended for external use. Note 13: Data guaranteed by design Note 14: When VIN rises above VOUT + VSCHOTTKY, VOUT starts to follow the VIN voltage rise so that VOUT = VIN - VSCHOTTKY 7 www.national.com LP55281 Modes of Operation In the RESET mode all the internal registers are reset to the default values and the device goes to STANDBY mode after reset. NSTBY control bit is low after reset by default. Reset is entered always if Reset Register is written, internal Power On Reset is active, or NRST pin is pulled down externally. The LP55281 can be reset by writing any data to the Reset Register (address 60H). Power On Reset (POR) will activate during the device startup or when the supply voltage VDD2 falls below 1.5V. Once VDD2 rises above 1.5V, POR will inactivate and the device will continue to the STANDBY mode. STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW. This is the low power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective immediately after startup. STARTUP: When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (VREF, Oscillator, etc.). To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. If the device temperature rises too high, the Thermal Shutdown (TSD) disables the device operation and STARTUP mode is entered until no thermal shutdown is present. BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in PWM mode during the 10 ms delay generated by the state-machine. The Boost startup is entered from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH. During the 10 ms Boost Startup time all LED outputs are switched off to ensure smooth startup. NORMAL: During NORMAL mode the user controls the device using the Control Registers. The registers can be written in any sequence and any number of bits can be altered in a register in one write. RESET: 20201175 www.national.com 8 LP55281 Magnetic Boost DC/DC Converter The LP55281 Boost DC/DC Converter generates a 4.0 - 5.3V supply voltage for the LEDs from single Li-Ion battery (3V... 4.5V). The output voltage is controlled with an 8-bit register in 9 steps. The converter is a magnetic switching PWM mode DC/DC converter with a current limit. The converter has three options for switching frequency, 1 MHz, 1.67 MHz and 2 MHz (default), when timing resistor RT is 82 kΩ. Timing resistor defines the internal oscillator frequency and thus directly affects boost frequency and all circuit's internally generated timing (RGB, ALED). The LP55281 Boost Converter uses pulse-skipping elimination to stabilize the noise spectrum. Even with light load or no load a minimum length current pulse is fed to the inductor. An active load is used to remove the excess charge from the output capacitor at very light loads. At very light load and when input and output voltages are very close to each other, the pulse skipping is not completely eliminated. Output voltage should be at least 0.5V higher than input voltage to avoid pulse skipping. Reducing the switching frequency will also reduce the required voltage difference. Active load can be disabled with the EN_AUTOLOAD bit. Disabling will increase the efficiency at light loads, but the downside is that pulse skipping will occur. The Boost Con- verter should be stopped when there is no load to minimise the current consumption. The topology of the magnetic boost converter is called CPM control, current programmed mode, where the inductor current is measured and controlled with the feedback. The user can program the output voltage of the boost converter. The output voltage control changes the resistor divider in the feedback loop. The following figure shows the boost topology with the protection circuitry. Four different protection schemes are implemented: 1. Over voltage protection, limits the maximum output voltage — Keeps the output below breakdown voltage. — Prevents boost operation if battery voltage is much higher than desired output. 2. Over current protection, limits the maximum inductor current — Voltage over switching NMOS is monitored; too high voltages turn the switch off. 3. Feedback break protection. Prevents uncontrolled operation if FB pin gets disconnected. 4. Duty cycle limiting, done with digital control. 20201177 Boost Converter Topology 9 www.national.com LP55281 BOOST STANDBY MODE User can stop the Boost Converter operation by writing the Enables register bit EN_BOOST low. When EN_BOOST is written high, the converter starts for 10 ms in PFM mode and then goes to PWM mode. BOOST OUTPUT VOLTAGE CONTROL User can control the Boost output voltage by boost output 8bit register. Boost Output [7:0] Register 0Fh Bin 0000 0000 0000 0001 0000 0011 0000 0111 0000 1111 0001 1111 0011 1111 0111 1111 1111 1111 Hex 00 01 03 07 0F 1F 3F 7F FF Boost Output Voltage (typical) 4.00 4.25 4.40 4.55 4.70 4.85 5.00 (default) 5.15 5.30 FRQ_SEL[2:0] 1XX 01X 001 frequency 2.00 MHz 1.67 MHz 1.00 MHz BOOST FREQUENCY CONTROL Register 'Frequency selections' (address 10h). Register default value after reset is 07h. 20201197 Boost Output Voltage Control www.national.com 10 LP55281 BOOST CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS 20201108 20201198 Boost Typical Waveforms with 100 mA Load Boost Converter Efficiency 20201109 20201110 Battery Current vs Voltage Battery Current vs Voltage 20201111 Boost Line Regulation 20201112 Boost Startup with No Load 11 www.national.com LP55281 20201113 20201114 Boost Load Regulation, 50 - 100 mA 20201115 20201116 Output Voltage vs Load Current Efficiency at Low Load vs Autoload www.national.com 12 LP55281 Functionality of RGB LED Outputs (R1-4, G1-4, B1-4) LP55281 has 4 sets of RGB/color LED outputs. Each set has 3 outputs, which can be controlled individually with a 6-bit PWM control register. The pulsed current level for each LED output is set with a single external resistor RRGB and a 2-bit coarse adjustment bit for each LED output (see tables below). Rx_IPLS[7:6] / Gx_IPLS[7:6] / Bx_IPLS[7:6] 00 01 10 11 Rx_PWM[5:0] / Gx_PWM[5:0] / Bx_PWM[5:0] 000 000 000 001 000 010 ... Awerage Sink Current 0 1/63*IPLS 2/63*IPLS ... Sink Current Pulse (IMAX = 100*1.23/RRGB) IPLS 0.25*IMAX 0.50*IMAX 0.75*IMAX 1.00*IMAX Pulse Ratio, % 111 110 111 111 62/63*IPLS 63/63*IPLS 98.4 100 Each RGB set must be enabled separately by setting EN_RGBx bit to '1'. Note, that the device must be enabled (NSTBY = '1') before the RGB outputs can be activated. When any of EN_RGBx bits are set to '1' and NSTBY = '1', the RGB driver takes a certain quiescent current from battery even if all PWM control bits are '0'. The quiescent current is dependent on RRGB resistor, and can be calculated from formula IR_RGB = 1.23V/RRGB. PWM CONTROL TIMING PWM frequency can be selected from 3 predefined values: 10 kHz, 20 kHz and 40 kHz. The frequency is selected with FPWM1 and FPWM0 bits, see following table: FPWM1 0 0 1 FPWM0 0 1 0 1 PWM Frequency (fPWM) 9.92 kHz 19.84 kHz 39.68 kHz 39.68 kHz 0 1.6 3.2 ... 1 Each RGB set has equivalent internal PWM timing between R, G and B: R has a fixed start time, G has a fixed midpulse time and B has a fixed pulse end time. PWM start time for each RGB set is different in order to minimize the instantaneous current loading due to the current sink switch on transition. See following timing diagram for details. Timing Diagram 20201117 13 www.national.com LP55281 RGB DRIVER TYPICAL PERFORMANCE CHARACTERISTICS 20201126 Output Current vs Pin Voltage (Current Sink Mode) 20201127 Output Current vs RRGB (Current Sink Mode) www.national.com 14 LP55281 Audio Synchronization The ALED output can be synchronized to incoming audio with Audio Synchronization feature. Audio Synch synchronizes ALED based on input signal's peak amplitude. Programmable gain and automatic gain control function are also available for adjustment of input signal amplitude to light response. Control of ALED brightness refreshing frequency is done with four different frequency configurations. The digitized input signal has DC component that is removed by a digital dc-remover (-3 dB @ 500 Hz). LP55281 has a 2-channel audio (stereo) input for audio synchronization, as shown in the figure below. The inputs accept signals in the range of 0V to 1.6V peak-topeak and these signals are mixed into a single wave so that they can be filtered simultaneously. LP55281 audio synchronization is mainly realized digitally and it consists following signal path blocks (see figure below) • Input buffer • AD converter • Automatic Gain Control (AGC) and manually programmable gain • Peak detector 20201119 CONTROL OF AUDIO SYNCHRONIZATION The following table describes the controls required for audio synchronization. ALED brightness control through serial in- terface is not available when audio synchronization is enabled. Audio Synchronization Control (Registers 0Dh and 0Eh) GAIN_SEL [2:0] DC_FREQ Register Input signal gain control. Gain has a range from 0 dB to -46 dB. 0Dh [000] = 0 dB, [001] = -6 dB, [010] = -12 dB, [011] = -18 dB, Bits 7-5 [100] = -24 dB, [101] = -31 dB, [110] = -37 dB, [111] = -46 dB Register Control of the high-pass filter's corner frequency: 0Dh 0 = 80 Hz Bit 4 1 = 510 Hz Register Automatic gain control. Set EN_AGC = 1 to enable automatic control or 0 to disable. When EN_AGC 0Dh is disabled, the audio input signal gain value is defined by GAIN_SEL. Bits 3 Register Audio synchronization enabled. Set EN_SYNC = 1 to enable audio synchronization or 0 to disable. 0Dh Bits 2 EN_AGC EN_SYNC SPEED_CTRL Register Control for refreshing frequency. Sets the typical refreshing rate for the ALED output [1:0] 0Dh [00] = FASTEST, [01] = 15 Hz, [10] = 7.6 Hz, [11] = 3.8 Hz Bits 1-0 THRESHOLD [3:0] Register Control for the audio input threshold. Sets the typical threshold for the audio inputs signals. May be 0Eh needed if there is noise on the audio lines. Bits 3-0 Typical Gain Values vs Audio Input Amplitude Audio Input Amplitude mVP-P 0 to 10 0 to 20 0 to 40 1 to 85 3 to 170 5 to 400 10 to 800 20 to 1600 Gain Value dB 0 -6 -12 -18 -24 -31 -37 -46 Audio Input Threshold Setting (Register 0Eh) THRESHOLD[3:0] 0000 0001 0010 ... 1110 1111 Threshold Level, mV (typical) Disabled 0.2 0.4 ... 2.5 2.7 15 www.national.com LP55281 ALED Driver LP55281 has a single ALED driver. It is a constant current sink with an 8-bit control. ALED driver can be used as a DC current sink or an audio synchronized current sink. Note, that when the audio synchronization function is enabled, the 8-bit current control register has no effect. ALED driver is enabled when audio synchronization is enabled (EN_SYNC = 1) or when ALED[7:0] control byte has other than 00h value. once in every 128 µs period, as long as the EN_LTEST bit is '1'. User can set the preferred DC current level with the LED driver controls. The RGB drivers' PWM must be set to 100%, or otherwise there can appear random variation on results. Note, that the 55 kΩ resistor divider causes small additional current through the LED under measurement. ADC result can be converted into a voltage value (of the selected pin) by multiplying the ADC result (in decimals) with 27.345 mV (value of LSB). The calculated voltage value is the voltage between the selected pin and ground. The internal LDO voltage is used as a reference voltage for the conversion. The accuracy of LDO is ± 3%, which is defining the overall accuracy. The non-linearity and offset figures are both better than 2LSB. 20201107 ADJUSTMENT OF ALED DRIVER Adjustment of the ALED driver current (Register 0Ch) is described in table below: ALED[7:0] 0000 0000 0000 0001 0000 0010 ... 1111 1101 1111 1110 1111 1111 Driver Current, mA (typical) 0 0.06 0.1 ... 14.8 14.9 15 20201120 Principle of LED Connection to ADC LED Multiplexing (Register 12h) MUX_LED[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Connection R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 ALED Boost Output With other than values on the table, the current value can be calculated to be (15.0 mA / 255) * ALED[7:0], where ALED [7:0] is value in decimals. LED Test Interface All LED pin voltages and boost output voltage in LP55281 can be measured and value can be read through the SPI/I2C compatible interface. MUX_LED[3:0] bits in the LED test register (address 12h) are used to select one of the LED outputs or boost output for measurement. The selected output is connected to the internal ADC through a 55 kΩ resistor divider. The AD conversion is activated by setting the EN_LTEST bit to '1'. The first conversion is ready after 128 µs from this. The result can be read from the ADC output register (address 13h). The device executes the AD conversions automatically www.national.com 16 LP55281 LED TEST PROCEDURE An example of LED test sequence is presented here. Note, that user can use incremental write sequence on I2C. The test sequence consists of the basic setup and measurement phases for all RGB LEDs and Boost voltage. Basic setup phase for the device: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. Give reset to LP55281 (by power on, NRST pin or write any data to register 60h) Set the preferred value for RED1 (write 3Fh, 7Fh, BFh or FFh to register 00h) Set the preferred value for GREEN1 (write 3Fh, 7Fh, BFh or FFh to register 01h) Set the preferred value for BLUE1 (write 3Fh, 7Fh, BFh or FFh to register 02h) Set the preferred value for RED2 (write 3Fh, 7Fh, BFh or FFh to register 03h) Set the preferred value for GREEN2 (write 3Fh, 7Fh, BFh or FFh to register 04h) Set the preferred value for BLUE2 (write 3Fh, 7Fh, BFh or FFh to register 05h) Set the preferred value for RED3 (write 3Fh, 7Fh, BFh or FFh to register 06h) Set the preferred value for GREEN3 (write 3Fh, 7Fh, BFh or FFh to register 07h) Set the preferred value for BLUE3 (write 3Fh, 7Fh, BFh or FFh to register 08h) Set the preferred value for RED4 (write 3Fh, 7Fh, BFh or FFh to register 09h) Set the preferred value for GREEN4 (write 3Fh, 7Fh, BFh or FFh to register 0Ah) Set the preferred value for BLUE4 (write 3Fh, 7Fh, BFh or FFh to register 0Bh) Set the preferred value for ALED (write 01h - FFh to register 0Ch) Dummy write: 00h to register 0Dh (Only if the incremental write sequence is used) Dummy write: 00h to register 0Eh (Only if the incremental write sequence is used) Set preferred boost voltage (write 00h - FFh to register 0Fh) Set preferred boost frequency (write 00h - 07h to register 10h, PWM frequency can be anything) Enable boost and RGB drivers (write CFh to register 11h) Wait 20 ms for the device and boost startup Measurement phase: 1. 2. 3. 4. 5. Enable LED test and select output (write 1xh to register 12h) Wait for 128 µs Read ADC output (read register 13h) Go to step 1 of measurement phase and define next output to be measured as many times as needed Disable LED test (write 00h to register 12h) or give reset to the device (see step 1 in basic setup phase) Test Phase I2C Setup Boost startup 14 measurements Total Time 0.528 20 4.137 24.7 Time (ms) SPI 0.024 20 1.831 21.9 LED TEST TIME ESTIMATION Assuming the maximum clock frequencies used in SPI or I2C compatible interfaces, the following table predicts the overall test sequence time for the test procedure shown above. This estimation gives the shortest time possible. Incremental write is assumed with I2C. Reset and LED test disable are not included. 17 www.national.com LP55281 7V Shielding To shield LP55281 from high input voltages (6 to 7.2V), the use of external 2.8V LDO is required. This 2.8V voltage protects internally the device against high voltage condition. The recommended connection is shown in the picture below. Internally both logic and analog circuitry works at 2.8V supply voltage. Both supply voltage pins should have separate filtering capacitors. Note that it is recommended to pull down the external LDO voltage when it is disabled in order to minimize the leakage current of the LED outputs. 20201121 In cases where high voltage is not an issue, the alternative connection is shown below. 20201122 www.national.com 18 LP55281 Control Interface The LP55281 supports two different interface modes: • SPI interface (4 wire, serial) • I2C compatible (2 wire, serial) User can define the serial interface by IF_SEL pin. If IF_SEL = 0, I2C mode is selected. SPI INTERFACE LP55281 is compatible with SPI serial bus specification and it operates as a slave. The transmission consists of 16-bit Write and Read Cycles. One cycle consists of a 7 Address bits, 1 Read/Write (RW) bit and 8 Data bits. RW bit high state defines a Write Cycle and low a Read Cycle. SO output is normally in high-impedance state and it is active only when Data is sent out during a Read Cycle. A pull-up resistor may be needed in SO line if a floating logic signal can cause unintended current consumption in the input circuits where SO is connected. The Address and Data are transmitted MSB first. The Slave Select signal (SS) must be low during the Cycle transmission. SS resets the interface when high and it has to be taken high between successive Cycles. Data is clocked in on the rising edge of the clock signal (SCK), while data is clocked out on the falling edge of SCK. 20201123 SPI Write Cycle 20201124 SPI Read Cycle 20201125 SPI Timing Diagram 19 www.national.com LP55281 SPI Timing Parameters VDD = VDDIO = 2.8V Symbol 1 2 3 4 5 6 7 8 9 10 11 Note: Data guaranteed by design Parameter Min Cycle Time Enable Lead Time Enable Lag Time Clock Low Time Clock High Time Data Setup Time Data Hold Time Data Acces Time Disble Time Data Valid Data Hold Time 0 70 35 35 35 35 20 0 Limit Max Units ns ns ns ns ns ns ns 20 10 20 ns ns ns ns www.national.com 20 LP55281 I2C COMPATIBLE SERIAL BUS INTERFACE Interface Bus Overview The I2C compatible synchronous serial interface provides access to the programmable functions and registers on the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle. For every device on the bus is assigned a unique address and it acts as a Master or a Slave, depending on whether it generates or receives the serial clock (SCL). When LP55281 is connected in parallel with other I2C compatible devices, the LP55281 supply voltages VDD1, VDD2 and VDDIO must be active. Supplies are required to make sure that the LP55281 does not disturb the SDA and SCL lines. 20201152 Data Transactions One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCL). Consequently, throughout the clock's high period, the data should remain stable. Any changes on the SDA line during the high states of the SCL and in the middle of the transaction, aborts the current transaction. New data should be sent during the low SCL state. This protocol permits a single data line to transfer both command/control information and data using the synchronous serial clock. Acknowledge Signal The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop Condition is generated. A high-to-low transition of the data line (SDA), while the clock (SCL) is high, indicates a Start Condition. A low-to-high transition of the SDA line, while the SCL is high, indicates a Stop Condition 20201150 20201149 Start and Stop Conditions In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This allows another device to be accessed or a register read cycle. Acknowledge Cycle The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte transferred, and the acknowledge signal sent by the receiving device. The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to receive the next byte. "ACKNOWLEDGE AFTER EVERY BYTE" Rule The Master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge signal after every byte received. There is one exception to the "acknowledge after every byte" rule. When the master is the receiver, it must indicate to the transmitter an end of data by not-acknowledging ("negative acknowledge") the last byte clocked out of the slave. This Data Validity Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following sections provide further details of this process. 21 www.national.com LP55281 "negative acknowledge" still includes the acknowledge clock pulse (generated by the master), but the SDA line is not pulled down. Addressing Transfer Formats Each device on the bus has a unique slave address. The LP55281 operates as a slave device with 7-bit address. LP55281 I2C address is pin selectable from two different choices. The LP55281 address is 4Ch (SI/A0 = 0) or 4Dh (SI/A0 = 1) as selected with SI/A0 pin. If eighth bit is used for programming, the 8th bit is 1 for read and 0 for write. Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device should send an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave address (the eighth bit). When the slave address is sent, each device in the system compares this slave address with its own. If there is a match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the R/W bit (1 for read, 0 for write), the device acts as a transmitter or a receiver. • Write cycle ends when the master creates stop condition. Control Register Read Cycle • Master device generates a start condition. • Master device sends slave address (7 bits) and the data direction bit (r/w=0). • Slave device sends acknowledge signal if the slave address is correct. • Master sends control register address (8 bits). • Slave sends acknowledge signal. • Master device generates repeated start condition. • Master sends the slave address (7 bits) and the data direction bit (r/w=1). • Slave sends acknowledge signal if the slave address is correct. • Slave sends data byte from addressed register. • If the master device sends acknowledge signal, the control register address will be incremented by one. Slave device sends data byte from addressed register. • Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop condition. Address Mode Data Read [Ack] [Ack] [Ack] [Register Data] ...additional reads from subsequent register address possible [Ack] [Ack] [Ack] ...additional writes to subsequent register address possible 20201151 I2C Device Address Control Register Write Cycle • Master device generates start condition • Master device sends slave address (7 bits) and the data direction bit (r/w=0). • Slave device sends acknowledge signal if the slave address is correct. • Master sends control register address (8 bits). • Slave sends acknowledge signal. • Master sends data byte to be written to the addressed register. • Slave sends acknowledge signal. • If master will send further data bytes, the control register address will be incremented by one after acknowledge signal Data Write < > Data from master, [ ] data from slave 20201194 Register Read Format www.national.com 22 LP55281 When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle waveform. 20201193 Register Write Format • • • • • w = write (SDA = 0) r = read (SDA = 1) ack = acknowledge (SDA pulled down by either master or slave) rs = repeated start id = 7-bit device address I2C Timing Parameters VDD1,2 = 3.0V to 4.5V, VDDIO = 1.65V to VDD1,2 20201154 I2C Timing Diagram Symbol 1 2 3 4 5 6 7 8 9 10 Cb Note: Data guaranteed by design Parameter Min Hold Time (repeated) START condition Clock Low Time Clock High Time Setup Time for a Repeated START Condition Data Hold Time Data Setup TIme Rise Time of SDA and SCL Fall Time of SDA and SCL Set-up Time for STOP condition Bus Free Time between a STOP and a START Condtion Capacitive Load for Each Bus Line 0.6 1.3 600 600 50 100 Limit Max Units µs µs ns ns ns ns 300 300 ns ns ns µs 200 pF 20 + 0.1Cb 15 + 0.1Cb 600 1.3 10 23 www.national.com LP55281 Recommended External Components OUTPUT CAPACITOR, COUT: The output capacitor COUT directly affects the magnitude of the output ripple voltage. In general, the higher the value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best choice. At the lighter loads, the low ESR ceramics offer a much lower VOUT ripple than the higher ESR tantalums of the same value. At the higher loads, the ceramics offer a slightly lower VOUT ripple magnitude than the tantalums of the same value. However, the dv/dt of the VOUT ripple with the ceramics is much lower than the tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V or greater is recommended. Some ceramic capacitors, espesically those in small packages, exhibit a strong capacitance reduction with the increased applied voltage. The capacitance value can fall to below half of the nominal capacitance. Too low output capacitance will increase the noise and it can make the boost converter unstable. INPUT CAPACITOR, CIN: The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V or greater is recommended. LIST OF RECOMMENDED EXTERNAL COMPONENTS Symbol CVDD1 CVDD2 CVDDIO CVDDA COUT CIN LBOOST CVREF CVDDIO RRGB RRT D1 CASE LEDs Symbol explanation C between VDD1 and GND C between VDD2 and GND C between VDDIO and GND C between VDDA and GND C between FB and GND C between battery voltage and GND L between SW and VBAT at 2 MHz C between VREF and GND C between VDDIO and GND R between IRGB and GND R between IRT and GND Rectifying Diode (Vf @ maxload) C between Audio input and ASEx Value 100 100 100 1 10 10 4.7 100 100 8.2 82 0.3 100 OUTPUT DIODE, D1: A Schottky diode should be used for the output diode. To maintain high efficiency the average current rating of the schottky diode shoulde be larger than the peak inductor current (1A). Schottky diodes with a low forward drop and fast switching speeds are ideal for increasing efficiency in portable applications. Choose a reverse breakdown of the schottky diode larger than the output voltage. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery times cause the efficiency and the load regulation to suffer. INDUCTOR, L: The LP55281's high switching frequency enables the use of the small surface mount inductor. A 4.7 µH shielded inductor is suggested for 2 MHz operation, 10 µH should be used at 1 MHz. The inductor should have a saturation current rating higher than the peak current it will experience during circuit operation (~1A). Less than 300 mΩ ESR is suggested for high efficiency. Open core inductors cause flux linkage with circuit components and interfere with the normal operation of the circuit. This should be avoided. For high efficiency, choose an inductor with a high frequency core material such as ferrite to reduce the core losses. To minimize radiated noise, use a toroid, pot core or shielded core inductor. The inductor should be connected to the SW pin as close to the IC as possible. Recommended inductors are LPS3015 and LPS4012 from Coilcraft and VLF4012 from TDK. Unit nF nF nF µF µF µF µH nF nF kΩ kΩ V nF User defined Type Ceramic, X7R/X5R Ceramic, X7R/X5R Ceramic, X7R/X5R Ceramic, X7R/X5R Ceramic, X7R/X5R Ceramic, X7R/X5R Shielded, low ESR, ISAT 1A Ceramic, X7R Ceramic, X7R ±1% ±1% Schottky diode Ceramic, X7R/X5R www.national.com 24 LP55281 LP55281 Registers Following table summarizes the registers and their default values Address Register 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h RED1 GREEN1 BLUE1 RED2 GREEN2 BLUE2 RED3 GREEN3 BLUE3 RED4 GREEN4 BLUE4 ALED 0 Audio Sync CTRL1 Audio Sync CTRL2 Boost Output 0 Frequency Selections Enables NSTBY 0 12h 13h LED Test ADC Output 0 r/o 60h Reset 0 r/o 0 r/o 0 r/o 0 1 FPWM1 0 EN_BOOS EN_AUTO T LOAD 0 0 EN_LTEST 0 DATA[7:0] 0 r/o 0 r/o 0 r/o 0 r/o 0 1 FPWM0 0 1 Boost[7:0] 1 1 1 FRQ_SEL[2:0] 1 1 EN_RGB1 0 0 EN_RGB4 EN_RGB3 EN_RGB2 0 0 0 0 0 1 0 0 GAIN_SEL[2:0] 0 0 0 0 DC_FREQ 0 D7 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 0 0 ALED[7:0] 0 EN_AGC 0 0 0 EN_SYNC 0 0 0 1 0 0 1 0 SPEED_CTRL[1:0] D3 0 0 0 0 0 0 0 0 0 0 0 0 D2 0 0 0 0 0 0 0 0 0 0 0 0 D1 0 0 0 0 0 0 0 0 0 0 0 0 D0 0 0 0 0 0 0 0 0 0 0 0 0 R1 - IPLS[7:6] G1 - IPLS[7:6] B1 - IPLS[7:6] R2 - IPLS[7:6] G2 - IPLS[7:6] B2 - IPLS[7:6] R3 - IPLS[7:6] G3 - IPLS[7:6] B3 - IPLS[7:6] R4 - IPLS[7:6] G4 - IPLS[7:6] B4 - IPLS[7:6] R1_PWM[5:0] G1_PWM[5:0] B1_PWM[5:0] R2_PWM[5:0] G2_PWM[5:0] B2_PWM[5:0] R3_PWM[5:0] G3_PWM[5:0] B3_PWM[5:0] R4_PWM[5:0] G4_PWM[5:0] B4_PWM[5:0] THRESHOLD[3:0] MUX_LED[3:0] Writing any data to Reset Register resets LP55281 Note: r/o = read-only 25 www.national.com LP55281 Physical Dimensions inches (millimeters) unless otherwise noted NS Package Number TLA36AAA 36-bump Micro SMD package, 3 x 3 x 0.6 mm, 0.5 mm pitch NS Package Number RLA36AAA 36-bump Micro SMDxt package, 3 x 3 x 0.65 mm, 0.5 mm pitch See National Semiconductor Application Note AN–1112 Micro SMD Wafer Level Chip Scale Package for PCB design and assembly instructions for Micro SMD. For Micro SMDxt see National Semiconductor Application Note AN–1412 Micro SMDxt Wafer Level Chip Scale Package www.national.com 26 LP55281 27 www.national.com LP55281 Quad RGB Driver Notes THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS, IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. 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As used herein: Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. Copyright© 2007 National Semiconductor Corporation For the most current product information visit us at www.national.com National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530-85-86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +49 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 www.national.com