LP5553

LP5553 - PowerWise® AVS Energy Management Unit with SPMI March 5, 2009 LP5553 PowerWise® AVS Energy Management Unit with SPMI General Description The LP5553 is a System Power Management Interface (SPMI) compliant Energy Management Unit for reducing power consumption of low power hand held applications such as dual-core processors and DSPs. The LP5553 contains 2 advanced, digitally controlled stepdown DC/DC converters for supplying variable voltages to a SoC. The device also incorporates 5 programmable lowdropout, low noise linear regulators for powering I/O, peripheral logic blocks, auxiliary system functions, and maintaining memory retention (dual-domain) in shutdown-mode. The LP5553 implements 2 Non-Request Capable Slaves that are controlled via the SPMI. The LP5553 operates cooperatively with PowerWise® AVS technology compatible processors to optimize supply voltages adaptively (AVS - Adaptive Voltage Scaling) over process and temperature variations. It also supports dynamic voltage scaling (DVS) using frequency/voltage pairs from pre-characterized look-up tables. Features ■ SPMI bus for system-level power management ■ High-efficiency PowerWise® Technology Adaptive ■ ■ Voltage Scaling for intelligent energy management in AVS and DVS environments Two digitally programmable 3.6 MHz buck regulators to power dual voltage domains Five Programmable LDOs for system functions such as: — PLL/Clock Generation — I/O — Memory Retention Internal soft start Variable regulator power up sequencing. ■ ■ Applications ■ ■ ■ ■ ■ GSM/GPRS/EDGE & UMTS cellular handsets Hand-held radios PDAs Battery powered devices Portable instruments Key Specifications ■ 2.7 to 4.8V Input Voltage Range ■ ±2% (typical) Output Voltage Range Programmable DC/DC Buck Converters ■ 800 mA Output Current per DC/DC Converter ■ Up to 88% Efficiency ■ Digitally Programmable from 0.6 to 1.235V Programmable LDOs ■ Five digitally programmable LDOs System Diagram 30040601 © 2009 National Semiconductor Corporation 300406 www.national.com LP5553 Connection Diagrams and Package Mark Information CONNECTION DIAGRAM 30040602 LP5553 Pinout -- Top View PACKAGE MARK 30040607 LP5553 Package Marking (The diamond denotes pin A1.) Note: The actual physical placement of the package marking will vary from part to part. The package markings “XYTT” designate assembly and manufacturing information. "XY" is a date code and “TT” is a NSC internal code for die traceability. Both will vary considerably. “5553” is an internal code that identifies the LP5553. Ordering Information Order Number LP5553TL/NOPB LP5553TLX/NOPB Package marking 5553 5553 Supplied As 250 units Tape and Reel 3000 units Tape and Reel www.national.com 2 LP5553 Pin Descriptions Pin # E2 E6 B6 B1 D1 A6 A1 E4 F4 B4 B3 A4 A3 F3 C3 D5 F2 F1 E5 F5 E1 F6 C6 C1 D6 A5 A2 B5 B2 C4 D4 D3 C2 D2 E3 C5 Pin Name DVDD1 DVDD2 AVDD1 AVDD2 AVDD3 PVDD1 PVDD2 DGND1 DGND2 AGND1 AGND2 PGND1 PGND2 SUB RGND ENABLE SCLK SDATA RESETN PWROK VO1 VO2 VO3 VO4 VO5 SW1 SW2 VFB1 VFB2 GPO0 GPO1 GPO2 SA1 SA2 SA3 Reserved I/O P P P P P P P G G G G G G G G I I I/O I O P P P P P P P I I O O O I I I G Type P P P P P P P G G G G G G G G D D D D D P P P P P P P A A D/OD D/OD D/OD D D D G Function Power supply voltage input for digital. Connect to VIN. Power supply voltage input for digital, LDO2 and LDO5. Connect to VIN. Power supply voltage input for analog, switching regulator #1 and LDO3. Connect to VIN. Power supply voltage input for analog, switching regulator #2 and LDO4. Connect to VIN. Power supply voltage input for analog and LDO1. Connect to VIN. Power supply voltage input to internal PFET of switching regulator #1. Connect to VIN. Power supply voltage input to internal PFET of switching regulator #2. Connect to VIN. Digital Ground. Connect to system Ground. Digital Ground. Connect to system Ground. Analog Ground. Connect to system Ground. Analog Ground. Connect to system Ground. Power Ground. Connect to system Ground. Power Ground. Connect to system Ground. Substrate Ground. Connect to system Ground. Reference/sense Ground. Should connect to the Ground node of the switching regulators output capacitors. Enable input. Set this digital input high for normal operation. SPMI clock input SPMI bi-directional data Active low Reset input. Set this digital input high for normal operation. Power OK indicator. This is a digital, active high output signal. LDO1 output voltage. LDO2 output voltage. SPMI signals SCLK and SDATA reference voltage. LDO3 output voltage. Can be programmed to track VCORE1 voltage. LDO4 output voltage. Can be programmed to track VCORE2 voltage. LDO5 output voltage. VCORE1 Switching node; connected to filter inductor. VCORE2 Switching node; connected to filter inductor. VCORE1 DC/DC analog feedback input. Connect to the VCORE1 output voltage. VCORE2 DC/DC analog feedback input. Connect to the VCORE2 output voltage. General Purpose Output 0. Can be programmed as a CMOS output referenced to VO2 or as an open-drain output to a user selected voltage. General Purpose Output 1. Can be programmed as a CMOS output referenced to VO2 or as an open-drain output to a user selected voltage. General Purpose Output 2. Can be programmed as a CMOS output referenced to VO2 or as an open-drain output to a user selected voltage. SPMI Slave Address Bit 1. Tie to Ground or VIN for 0 or 1, respectively. (Note: SA0 is internal. '0' = Slave(N) = VCORE1; '1' = Slave(N+1) = VCORE2) SPMI Slave Address Bit 2. Tie to Ground or VIN for 0 or 1, respectively. SPMI Slave Address Bit 3 (MSB). Tie to Ground or VIN for 0 or 1, respectively. Must be tied to Ground. Failure to do so may result in undefined behavior. G: Ground Pin O: Output Pin P: Power Pin OD: Open Drain Output Pin A: Analog Pin I: Input Pin D: Digital Pin I/O: Input/Output Pin 3 www.national.com LP5553 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN pins (All VDD pins) −0.3V to +6.0V SW1, SW2, V01, V02, V03, V04, V05 to GND −0.3V to (VIN + 0.3V) ENABLE, RESETN, SCLK, SA1, −0.3V to (VIN + 0.3V) SA2, SA3 SDATA, PWROK, VFB1, VFB2, GPO0, −0.3V to (VIN + 0.3V) GPO1, GPO2 Junction Temperature (TJ-MAX) 150°C Storage Temperature Range −65°C to +150°C Max Continuous Power Dissipation PD-MAX (Notes 3, 4) Internally limited Maximum Lead Temperature (Soldering 10 seconds) +260°C Operating Ratings Input voltage range VIN ENABLE, RESETN, PWROK SDATA, SCLK SA1, SA2, SA3 (Notes 1, 2) 2.7 to 4.8V 0V to VIN 0V to VO2 0V to VIN Thermal Properties Junction Temperature (TJ) Ambient Temperature (TA) (Note 8) Junction-to-Ambient Thermal Resistance (θJA) (Note 7) −40°C to +125°C −40°C to +85°C 60°C/W ESD Ratings All pins (Note 5) 2 kv HBM 200V MM (Notes 2, 8, 9) General Electrical Characteristics Unless otherwise noted, VIN= 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C ≤ TJ≤ +125°C. Symbol IQ Parameter Shutdown Supply Current Conditions All circuits off; -40°C ≤ TA = TJ ≤ +125°C Memory retention current in VCORE1 and VCORE2 in Sleep state; Deep Sleep (i.e., both slaves in VO1, VO2 and VO5 on, but unloaded; Sleep state) V03 and VO4 in low IQ No load supply current UVLO-high UVLO-low Under Voltage Lockout, high threshold Under Voltage Lockout, low threshold Threshold (Note 10) Hysteresis (Note 10) Logic Input Low Logic Input High Logic Input High Input Leakage Current Input Leakage Current (Note: Largely due to pull-down resistors) RPD-SPMI Pull-down resistance for SPMI signals ENABLE, RESETN, SDATA, SCLK 2.7V ≤ VIN ≤ 4.8V ENABLE, RESETN 2.7V ≤ VIN ≤ 4.8V SDATA, SCLK 1.5V ≤ VO2 ≤ 3.3V ENABLE, RESETN 2.7V ≤ VIN ≤ 4.8V SDATA, SCLK 1.5V ≤ VO2 ≤ 3.3V 2.0 V02 - 0.2 -1 +1 µA -1 +5 MΩ 2.5 All regulators active and unloaded; switching regulators in Burst-PWM Min TYP 1 Max 75 Units 130 350 µA 735 2.6 2.6 930 2.7 V V Thermal Shutdown TSD 160 20 °C Logic and Control Inputs VIL VIH-SIDEBAND VIH-SPMI IIL 0.2 V V V SDATA, SCLK 0.5 1 2 www.national.com 4 LP5553 Symbol Logic and Control Outputs VOL VOH-SIDEBAND VOH-SPMI VOH-GPOx VOD-GPOx IGPO TENL TRSTL Parameter Logic Output Low Logic Output High Logic Output High Logic Output High Maximum Open-Drain High Voltage GPO Source/Sink Current Minimum ENABLE low pulse time Minimum RESETN low pulse time (Notes 2, 9) Default Output Voltage (V) 1.235 1.235 1.2 3.3 1.25 1.25 3.3 Conditions PWROK, SDATA, GPOx ISINK ≤ 1 mA PWROK ISOURCE ≤ 1 mA SDATA ISOURCE ≤ 1 mA GPOx, GPOs set for CMOS out ISOURCE ≤ 1 mA GPOx Min TYP Max Units 0.4 VIN - 0.4 VO2 - 0.4 VO2 - 0.4 VIN + 0.3 1 100 100 V V V V V mA ns ns Output Specification Supply Output Voltage Range (V) 0.6 to 1.235 0.6 to 1.235 0.7 to 2.2 1.5 to 3.3 0.6 to 1.35 0.6 to 1.35 1.2 to 3.3 Output Voltage Resolution (mV) 5 5 100 100-300 50 50 100-300 IMAX Maximum Output Current (mA) 800 800 100 250 50 50 250 Typical Application VCORE1 VCORE2 LDO1 LDO2 LDO3 LDO4 LDO5 Voltage Scaling Domain 1 Voltage Scaling Domain 2 PLL/Fixed Logic I/O Voltage Embedded Memory Domain 1 Embedded Memory Domain 2 Peripheral(s) 5 www.national.com LP5553 VCORE1/VCORE2 DC/DC Converters 1 and 2 Output Voltage Characteristics Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. (Notes 2, 8, 9) Symbol VOUT Accuracy Parameter Output voltage, Static accuracy Output voltage, Static accuracy Conditions 0.65V ≤ VOUT ≤ 1.235V IOUT = 0 - 800 mA 0.60V ≤ VOUT ≤ 0.65V IOUT = 0 - 800 mA Min -2 -4 0.6 1.235 (default) 0.05 0.001 30 325 255 135 0 850 IOUT = 200 mA, VIN = 2.7V, VCOREx = 1.235V PWM-mode 0 mA ≤ IOUT ≤ 800 mA 0 mA ≤ IOUT ≤ 800 mA VCOREx = 1.235V, unloaded 3.45 7 0 0.7 1.0 120 200 1200 88 3.6 10 3.75 13 20 1.3 800 1560 Typ Max +2 +4 1.235 Units % % V %/V %/mA µs µA mΩ mΩ mA mA % MHz µF mΩ µH µs µs VOUT Range Programmable Output Voltage Range 0mA ≤ IOUT ≤ 800 mA ΔVOUT Line regulation Load regulation TSCALING IQ RDS-ON(P) RDS-ON(N) IOUT ILIM η fOSC COUT L tSS tSTART-UP VOUT Setting Time Quiescent current P-FET resistance N-FET resistance Continuous load current Peak switching current limit Efficiency peak Oscillator frequency Output Filter Capacitance Output Capacitor ESR Output Filter Inductance Soft start ramp time Start-Up Time from VCOREx enable to VOUT 2.7V ≤ VIN ≤ 4.8V, IOUT = 100 mA IOUT = 100 - 800 mA From min to max output voltage IOUT = 400 mA No Load, Burst-PWM Mode VIN = VSG = 3.6V VIN = VGS = 3.6V www.national.com 6 LP5553 VO1 LDO1 Output Voltage Characteristics Unless otherwise noted, VIN = 3.6V, VOUT = 1.2V (default). Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full operating junction temperature range, -40° to +125°C.(Notes 2, 8, 9) Symbol VOUT Accuracy Parameter Output Voltage Conditions 1 mA ≤ IOUT ≤ 100 mA, 2.7V ≤ VIN ≤ 4.8V Min -2 0.7 1.2 (default) Typ Max 2 2.2 100 400 19 -0.1 -0.005 10 0.1 0.005 Units % V mA µA %/V %/mA mV VOUT Range Programmable Output Voltage Range 0 mA ≤ IOUT ≤ 100 mA 16 steps of 100 mV IOUT IQ ΔVOUT Output Current Output Current Limit Quiescent Current (Note 12) Line Regulation Load Regulation Line Transient Regulation Load Transient Regulation 2.7V ≤ VIN ≤ 4.8V VO1 = 0V (i.e., tied to Ground) IOUT = 50 mA 2.7V ≤ VIN ≤ 4.8V IOUT = 50 mA 1 mA ≤ IOUT ≤ 100 mA VIN = 3.9V → 3.6V → 3.9V TRISE = TFALL = 10 µs IOUT = 10 mA → 90 mA → 10 mA TRISE = TFALL = 10 µs eN PSRR Output Noise Voltage Power Supply Ripple Rejection Ratio 10 Hz ≤ f ≤ 100 kHz COUT = 2.2 µF f = 1 kHz COUT = 2.2 µF f = 10 kHz COUT = 2.2 µF COUT tSTART-UP Output Capacitance Output Capacitor ESR Start-Up Time from LDO1 enable COUT = 2.2 µF, IOUT = 100 mA 0 mA ≤ IOUT ≤ 100 mA VIN = 3.6V 60 mV 100 50 40 1 5 50 2.2 20 500 µVRMS dB dB µF mΩ µs 7 www.national.com LP5553 VO2 LDO2 (I/O Voltage) Output Voltage Characteristics Unless otherwise noted, VIN = 3.6V, IOUT = 125 mA, VO2 = 3.3V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full operating junction temperature range, -40 to +125°C. (Notes 2, 8, 9) Symbol VOUT Accuracy Parameter Output Voltage Conditions 1 mA ≤ IOUT ≤ 250 mA, 3.6V ≤ VIN ≤ 4.8V Min -2 1.5 3.3 (default) Typ Max 2 3.3 250 800 70 19 -0.1 -0.005 0.1 +0.005 260 Units % V mA mV µA %/V %/mA VOUT Range Programmable Output Voltage Range 1.5 through 2.3 in 100 mV steps, 2.5, 2.8, 3.0V and 3.3V IOUT VIN - VO2 IQ ΔVOUT Output Current Output Current Limit Dropout Voltage (Note 11) Quiescent Current (Note 12) Line Regulation Load Regulation Line Transient Regulation (Note 13) (VO2 + 0.4V) ≤ VIN ≤ 4.8V VO2 = 0V (i.e., tied to Ground) IOUT = 125 mA IOUT = 125 mA (VO2 + 0.4V) ≤ VIN ≤ 4.8V IOUT = 125 mA VIIN = 3.6V 1 mA ≤ IOUT ≤ 250 mA VIN = 4.0V → 3.6V → 4.0V VO2 = 3.3V TRISE = TFALL = 10 µs VIN = 3.6V IOUT = 25 mA → 225 mA → 25 mA TRISE = TFALL = 1 µs PSRR Power Supply Ripple Rejection Ratio f = 1 kHz COUT = 4.7 µF f = 10 kHz COUT = 4.7 µF COUT tSTART-UP Output Capacitance Output Capacitor ESR Start-Up Time from LDO2 enable COUT = 4.7 µF, IOUT = 250 mA 0 mA ≤ IOUT ≤ 250 mA 10 mV Load Transient Regulation 125 mV 55 40 2 5 50 4.7 20 500 dB dB µF mΩ µs www.national.com 8 LP5553 VO3/VO3 LDO3 and LDO4 Output Voltage Characteristics Unless otherwise noted, VIN = 3.6V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full operating junction temperature range, -40 to +125°C. (Notes 2, 8, 9) Symbol VOUT Accuracy Parameter Active/Independent, High IQ Active/Independent, Low IQ VOFFSET Conditions IOUT ≤ 50 mA, 2.7V ≤ VIN ≤ 4.8V Low IQ bit is cleared IOUT ≤ 5 mA, 2.7V ≤ VIN ≤ 4.8V Low IQ bit is cleared Min -2.5 -2.5 Typ Max 2.5 % 2.5 Units Active state offset from tracked VCORE 0 mA ≤ IOUT ≤ 50 mA, VFB = 0.9V Offset = VO3 - VFB1 2.7V ≤ VIN ≤ 4.8V Offset = VO4 - VFB2 0 0.6 25 1.25 (default) 35 70 1.35 mV VOUT Range Programmable Output Voltage Range 16 steps of 50 mV IQ Quiescent Current (Note 12) Active state/Tracking mode IOUT = 10 μA Low IQ bit is set Sleep state or Active/Independent mode IOUT = 10 μA Low IQ bit is set IOUT Output Current Low IQ bit is cleared Output Current Limit Active state/Tracking, Low IQ bit is set Quiescent Current Sleep state/Tracking, Low IQ bit is set Output Current, Independent, Low IQ bit is set Output Current Limit PSRR COUT tSTART-UP Power Supply Ripple Rejection Ratio Output Capacitance Output Capacitor ESR Start-Up Time from LDOx enable COUT = 1.0 µF, IOUT = 20 mA 2.7V ≤ VIN ≤ 4.8V 2.7V ≤ VIN ≤ 4.8V V μA 10 50 50 2.7V ≤ VIN ≤ 4.8V 5 2.7V ≤ VIN ≤ 4.8V 5 VO2 = 0V (i.e., tied to Ground) f = 1 kHz COUT = 1.0 µF 0 mA ≤ IOUT ≤ 5 mA 0.75 5 50 37 1.0 2.2 500 420 dB µF mΩ µs mA 9 www.national.com LP5553 VO5 LDO5 Output Voltage Characteristics Unless otherwise noted, VIN = 3.6V, IOUT = 125 mA, VO2 = 3.3V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the full operating junction temperature range, -40 to +125°C. (Notes 2, 8, 9) Symbol VOUT Accuracy Parameter Output Voltage Conditions 1 mA ≤ IOUT ≤ 250 mA, VO2 = 3.3V 3.6V ≤ VIN ≤ 4.8V Min -2 1.2 3.3 (default) Typ Max 2 3.3 250 800 70 19 -0.1 -0.005 0.1 0.005 260 Units % V mA mV µA %/V %/mA VOUT Range Programmable Output Voltage Range 1.2 through 2.3 in 100 mV steps, 2.5, 2.8, 3.0V and 3.3V IOUT VIN - VO5 IQ ΔVOUT Output Current Output Current Limit Dropout Voltage (Note 11) Quiescent Current (Note 12) Line Regulation Load Regulation Line Transient Regulation (Note 13) (VO5 + 0.4V) ≤ VIN ≤ 4.8V VO5 = 0V (i.e., tied to Ground) IOUT = 125 mA IOUT = 125 mA (VO5 + 0.4V) ≤ VIN ≤ 4.8V IOUT = 125 mA VIN = 3.6V 1 mA ≤ IOUT ≤ 250 mA VIN = 4.0V → 3.6V → 4.0V VO5 = 3.3V TRISE = TFALL = 10 μs Load Transient Regulation VIN = 3.6V IOUT = 25 mA → 225 mA → 25 mA TRISE = TFALL = 1 µs PSRR Power Supply Ripple Rejection Ratio f = 1 kHz COUT = 4.7 µF f = 10 kHz COUT = 4.7 µF COUT tSTART-UP Output Capacitance Output Capacitor ESR Start-Up Time from LDO5 enable COUT = 4.7 µF, IOUT = 250 mA 0 mA ≤ IOUT ≤ 250 mA 10 mV 125 mV 55 40 2 5 50 4.7 20 500 dB dB µF mΩ µs www.national.com 10 LP5553 Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pin. Note 3: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula P = (TJ – TA) / θJAwhere TJ is the junction temperature, TA is the ambient temperature and θJA is the junction-to-ambient thermal resistance. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. Note 4: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and disengages at TJ = 140°C (typ.). Note 5: The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is a 200 pF capacitor discharged directly into each pin, MIL-STD-883 3015.7. Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation of the device in the application (PD-MAX) and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX). Note 7: Junction-to-ambient thermal resistance (θJA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 102 mm x 76 mm x 1.6 mm with a 2x1 array of thermal vias. The ground plane on the board is 50 mm x 50 mm. Thickness of copper layers are 36 µm / 18 µm / 18 µm / 36 µm (1.5 oz / 1 oz / 1 oz / 1.5 oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. The value of θJA of this product can vary significantly, depending on PCB material, layout and environmental conditions. In applications where high maximum power dissipation exists (high VIN, high IOUT), special care must be paid to thermal dissipation issues. For more information on these topics, please refer to Application Note 1112: Micro SMD Wafer Level Chip Scale Package and the Board Layout Considerations section of this datasheet. Note 8: All limits are guaranteed by design, test and/or statistical analysis. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Note 9: Capacitors: Low-ESR Surface-Mount Ceramic Capacitors are (MLCCs) used in setting electrical characteristics Note 10: Guaranteed specifically by design. Note 11: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. Other parameters are not guaranteed when the LDO is in dropout. This specification applies only when the output voltage is greater than 2.7V. Note 12: Quiescent currents for LDO1 through LDO5 do not include shared blocks such as the bandgap reference. Note 13: VIN for line transient is above the default 3.6V to allow for 400 mV of headroom from VIN to VOUT 11 www.national.com LP5553 LP5553 - Typical Performance Characteristics LP5553 Startup Timing All Outputs at No Load Efficiency vs. Load, VCOREx 30040606 30040619 DC/DC Converter Load Transient Response 20 mA 800 mA / 3 µs DC/DC Converter Load Transient Response 20 mA 575 mA / 2 µs 30040613 30040614 DC/DC Corevoltage adjust min --> max Tracking and Slew Limit Set DC/DC Corevoltage adjust max --> min Tracking and Slew Limit Set 30040616 30040617 www.national.com 12 LP5553 Sleep IQ Curves Over Temperature Shutdown IQ Curves Over Temperature 30040604 30040605 VCOREx PWM Switching Waveform VCOREx Burst-PWM Switching Waveform 30040620 30040621 VO2/VO5 Load Transient Response VO1 Load Transient Response 30040654 30040655 13 www.national.com LP5553 VO1/VO2/VO5 Line Transient Response VO3/VO4 Line Transient Response 30040653 30040609 www.national.com 14 LP5553 LP5553 SPMI Register Map This table summarizes LP5553 SPMI register usage and shows default register bit values after reset, as programmed by the factory. The following sub-sections provide additional details on the use of each individual register. Slave Address [N] Base Registers Register Name R0 R1 R2 Register Usage Core Voltage 1 Switcher #1 Memory Voltage 1 Independent Mode LDO3 Memory Retention Voltage 1 Sleep State Reserved Do not use Reserved Do not use Not Implemented LDO2 Voltage (I/O Voltage) LDO1 Voltage LDO5 Voltage Enable Control 1 0x07 0x08 0x09 0x0A R/W R/W R/W R/W 0* 0* 0* 0* 1 0 1 1 VCORE1 Enable 1 1 1 1 LDO3 Enable 1 0 1 1 LDO2 Enable 1 1 1 1 LDO1 Enable 0* 0* 0* 1 LDO5 Enable 0* 0* 0* 0* 0* 0* 0* 0 Force PWM Switcher #1 0 GP0 0 LDO3 Low IQ Bit Register Address 0x00 0x01 0x02 Type 7 R/W R/W R/W 0* 0* 0* 1 1 1 6 1 1 1 5 1 0 0 Reset Default Value 4 1 1 1 3 1 0* 0* 2 1 0* 0* 1 1 0* 0* 0 R3 R4 R5-R6 R7 R8 R9 R10 0x03 0x04 N/A N/A - - - - - - - - R11 R12 R13 Not Implemented GPO Data Register Miscallaneous Control 1 0x0C 0x0D R/W R/W 0* 0* 0* 0* 0* 0* 0* 0* 0* 1 GPO Open Drain Select 0 GP2 0 SW1 Slew Control 0 GP1 0 LDO3 Tracking Select R14-R30 R31 Not Implemented Reserved Do not use Not Implemented Extended Long Registers 0x1F N/A - Extended Registers ER0ER255 ELR0Not Implemented ELR65535 15 www.national.com LP5553 Slave Address [N+1] Base Registers Register Name R0 R1 R2 Register Usage Core Voltage 2 Switcher #2 Memory Voltage 2 Independent Mode LDO4 Memory Retention Voltage 2 Sleep State Reserved Do not use Reserved Do not use Not Implemented Enable Control 2 0x0A R/W 0* 1 VCORE2 Enable 1 LDO4 Enable 0* 0* 0* 0* 0 Force PWM Switcher #2 0 LDO4 Low IQ Bit Register Address 0x00 0x01 0x02 Type 7 R/W R/W R/W 0* 0* 0* 1 1 1 6 1 1 1 5 1 0 0 Reset Default Value 4 1 1 1 3 1 0* 0* 2 1 0* 0* 1 1 0* 0* 0 R3 R4 R5-R9 R10 0x03 0x04 N/A N/A - - - - - - - - R11-R12 R13 Not Implemented Miscallaneous Control 2 0x0D R/W 0* 0* 0* 0* 0* 0 SW2 Slew Control 0 LDO4 Tracking Select R14-R31 ER0ER255 Not Implemented Extended Registers Not Implemented Extended Long Registers ELR0Not Implemented ELR65535 Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. A bit with a hyphen ( - ) denotes a bit in a reserved register location. Accessing reserved registers should be avoided to prevent undefined behavior of the LP5553. A write into unimplemented register(s) will be ignored. A read of an unimplemented register(s) will produce a “No response frame”. Please refer to SPMI specification for further information. www.national.com 16 LP5553 Slave Address [N] - 1st Slave Device R0 - VCORE1 - Core Voltage 1 Address Slave Address Type Reset Default 0x00 N R/W 8h'7F Register Bits 7 Sign 0 0 0 0* 0 x 1 1 0 0 0 0 x 1 1 0 0 0 0 x 1 1 6 5 4 3 Voltage Data 0 0 0 0 x 1 1 0 0 0 0 x 1 1 0 0 1 1 x 1 1 0 1 0 1 x 0 1 0x7E 0x7F 0x00 0x01 0x02 0x03 Linear Scaling 1.230 1.235 (default) 0.600 0.605 0.610 0.615 2 1 0 Register Value [hex] Voltage Value [V] Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Write to this bit will be ignored. R1 - VO3 - LDO3 Memory Voltage 1 - Independent Mode Address Slave Address Type Reset Default 0x01 N R/W 8h'68 Register Bits 7 Sign 0 0 0 0 0 0 0 0* 0 1 1 1 1 1 1 1 1 6 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0* 0* 0* 2 1 Unused 0 Voltage Data Register Value [hex] 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 Voltage Value [V] 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 (default) 1.30 1.35 Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. 17 www.national.com LP5553 R2 - VO3 - LDO3 Memory Retention Voltage 1 - Sleep State Value Address Slave Address Type Reset Default 0x02 N R/W 8h'68 Register Bits 7 Sign 0 0 0 0 0 0 0 0* 0 1 1 1 1 1 1 1 1 6 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0* 0* 0* 2 1 Unused 0 Voltage Data Register Value [hex] 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 Voltage Value [V] 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 (default) 1.30 1.35 Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. R3 - Reserved Address Slave Address Type Reset Default 0x03 N Reserved 8h'00 Register bits 7 6 5 4 Reserved Do not use 3 2 1 0 www.national.com 18 LP5553 R4 - Reserved Address Slave Address Type Reset Default 0x04 N Reserved 8h'00 Register bits 7 6 5 4 Reserved Do not use 3 2 1 0 R7 - VO2 - LDO2 Voltage Address Slave Address Type Reset Default 0x07 N R/W 8h'78 Register Bits 7 Sign 0 0 0 0 0 0 0 0* 0 1 1 1 1 1 1 1 1 6 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0* 0* 0* 2 1 Unused 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 1.5 1.5 1.5 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.5 2.8 3.0 3.3 (default) 0 Voltage Data Register Value [hex] Voltage Value [V] Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. 19 www.national.com LP5553 R8 - VO1 - LDO1 Voltage Address Slave Address Type Reset Default 0x08 N R/W 8h'28 Register Bits 7 Sign 0 0 0 0 0 0 0 0* 0 1 1 1 1 1 1 1 1 6 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0* 0* 0* 2 1 Unused 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 0.7 0.8 0.9 1.0 1.1 1.2 (default) 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 0 Voltage Data Register Value [hex] Voltage Value [V] Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. www.national.com 20 LP5553 R9 - VO5 - LDO5 Voltage Address Slave Address Type Reset Default 0x09 N R/W 8h'78 Register Bits 7 Sign 0 0 0 0 0 0 0 0* 0 1 1 1 1 1 1 1 1 6 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0* 0* 0* 2 1 Unused 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.5 2.8 3.0 3.3 (default) 0 Voltage Data Register Value [hex] Voltage Value [V] Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. 21 www.national.com LP5553 R10 - Enable Control Register 1 Address Slave Address Type Reset Default 0x0A N R/W 8h'7C Register bits 7 6 5 R2, LDO3 Voltage Enable 1: regulator is enabled (default) 0: regulator is disabled 4 R7, LDO2 Voltage Enable 1: regulator is enabled (default) 0: regulator is disabled 3 R8, LDO1 Voltage Enable 1: regulator is enabled (default) 0: regulator is disabled 2 R9, LDO5 Voltage Enable 1: regulator is enabled (default) 0: regulator is disabled 0* 1 0 Unused R0, Core Voltage 1 Enable 1: regulator is enabled (default) 0: regulator is disabled 0* Unused Forced PWM Mode - DC/DC #1 0: Intelligent and Automatic PFM/ PWM Transition Most Energy Efficient (default) 1: Forced PWM No PFM Mode Allowed Smallest Voltage Ripple Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. R12 - GPO Data Register Address Slave Address Type Reset Default 0x0C N R/W 8h'00 Register Bits 7 6 5 Unused 4 3 2 GPO2 General Purpose Output - digital This bit drives the GP2 pin 0: GP2 is low (default) 1: GP2 is high 1 GPO1 General Purpose Output - digital This bit drives the GP1 pin 0: GP1 is low (default) 1: GP1 is high 0 GPO0 General Purpose Output - digital This bit drives the GP0 pin 0: GP0 is low (default) 1: GP0 is high 0* 0* 0* 0* 0* Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. www.national.com 22 LP5553 R13 - Misc Control Register 1 Address Slave Address Type Reset Default 0x0D N R/W 8h'08 Register Bits 7 6 Unused 5 4 3 GPO Open Drain Select 0: GPOs will behave as push-pull CMOS outputs referenced to VO2 1: GPOs will act as open-drain outputs (default) 2 SW1 Slew Control 0: No slew rate restiction on VCORE1 DC/DC output voltage (default) 1: Slew rate of VCORE1 DC/DC output voltage is reduced 1 LDO3 Tracking Select 0: LDO3 at R1 register value in Active mode. LDO3 does not track VCORE1 (default) 1: LDO3 tracks VCORE1 with offset 0 LDO3 Low IQ Bit 0: Selects the higher bias point for LDO3 which results in 50 mA operation (default) 1: Selects the lower bias point for LDO3 which results in 5 mA operation See Table 3for a more detailed explanation of this bit 0* 0* 0* 0* Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. R31 - Reserved Address Slave Address Type Reset Default 0x1F N Reserved 8h'00 Register bits 7 6 5 4 Reserved Do not use 3 2 1 0 23 www.national.com LP5553 Slave Address [N+1] - 2nd Slave Device R0 - VCORE2 - Core Voltage 2 Address Slave Address Type Reset Default 0x00 N+1 R/W 8h'7F Register Bits 7 Sign 0 0 0 0* 0 x 1 1 0 0 0 0 x 1 1 0 0 0 0 x 1 1 6 5 4 3 Voltage Data 0 0 0 0 x 1 1 0 0 0 0 x 1 1 0 0 1 1 x 1 1 0 1 0 1 x 0 1 0x7E 0x7F 0x00 0x01 0x02 0x03 Linear Scaling 1.230 1.235 (default) 0.600 0.605 0.610 0.615 2 1 0 Register Value [hex] Voltage Value [V] Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Write to this bit will be ignored. R1 - VO4 - LDO4 Memory Voltage 2 - Independent Mode Address Slave Address Type Reset Default 0x01 N+1 R/W 8h'68 Register Bits 7 Sign 0 0 0 0 0 0 0 0* 0 1 1 1 1 1 1 1 1 6 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0* 0* 0* 2 1 Unused 0 Voltage Data Register Value [hex] 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 Voltage Value [V] 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 (default) 1.30 1.35 Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. www.national.com 24 LP5553 R2 - VO4 - LDO4 Memory Retention Voltage 2 - Sleep State Value Address Slave Address Type Reset Default 0x02 N+1 R/W 8h'68 Register Bits 7 Sign 0 0 0 0 0 0 0 0* 0 1 1 1 1 1 1 1 1 6 5 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 4 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 3 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0* 0* 0* 2 1 Unused 0 Voltage Data Register Value [hex] 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 Voltage Value [V] 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 (default) 1.30 1.35 Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. R3 - Reserved Address Slave Address Type Reset Default 0x03 N+1 Reserved 8h'00 Register bits 7 6 5 4 Reserved Do not use 3 2 1 0 R4 - Reserved Address Slave Address Type Reset Default 0x03 N+1 Reserved 8h'00 Register bits 7 6 5 4 Reserved Do not use 3 2 1 0 25 www.national.com LP5553 R10 - Enable Control Register 2 Address Slave Address Type Reset Default 0x0A N+1 R/W 8h'60 Register bits 7 6 5 R2, LDO4 Voltage Enable 1: regulator is enabled (default) 0: regulator is disabled 4 3 Unused 2 1 0 Forced PWM Mode - DC/DC #2 0: Intelligent and Automatic PFM/PWM Transition - Most Energy Efficient (default) 1: Forced PWM - No PFM Mode Allowed - Smallest Voltage Ripple Unused R0, Core Voltage 2 Enable 1: regulator is enabled (default) 0: regulator is disabled 0* 0* 0* 0* 0* Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. R13 - Misc Control Register 2 Address Slave Address Type Reset Default 0x0D N+1 R/W 8h'00 Register Bits 7 6 5 Unused 4 3 2 SW2 Slew Control 0: No slew rate restiction on VCORE2 DC/DC output voltage (default) 1: Slew rate of VCORE2 DC/DC output voltage is reduced 1 LDO4 Tracking Select 0: LDO4 at R1 register value in Active mode. LDO3 does not track VCORE2 (default) 1: LDO4 tracks VCORE2 with offset 0 LDO4 Low IQ Bit 0: Selects the higher bias point for LDO4 which results in 50 mA operation (default) 1: Selects the lower bias point for LDO4 which results in 5 mA operation See Table 3 for a more detailed explanation of this bit 0* 0* 0* 0* 0* Note: A bit with an asterisk ( * ) denotes a register bit that is always read as a fixed value. Writes to these bits will be ignored. www.national.com 26 LP5553 LP5553 Operation GENERAL DESCRIPTION The LP5553 is a System Power Management Interface (SPMI) compliant energy management unit (EMU) for application or baseband processors in mobile phones and other portable equipment. It operates cooperatively with processors using National Semiconductor’s Advanced Power Controller (APC) to provide Adaptive Voltage Scaling (AVS) which drastically improves processor efficiencies compared to conventional power delivery methods. The LP5553 consists of two high efficiency switching DC/DC buck converters to supply two voltage scaling domains and five LDOs for supplying additional support circuitry. VOLTAGE SCALING The LP5553 is designed to be used in a voltage scaling system to lower the power dissipation of the system. By scaling supply voltage with the clock frequency of a processor, dramatic power savings can be achieved. Two types of voltage scaling are supported, dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS). Both DC/DC 1 and 2 support AVS and DVS modes. DVS systems switch between precharacterized voltages, which are paired to clock frequencies used for frequency scaling in the processor. AVS systems track the processor performance and optimize the supply voltage to the required performance. AVS is a closed loop system that provides process and temperature compensation such that for any given processor, temperature, or clock frequency, the minimum supply voltage is delivered. SYSTEM POWER MANAGEMENT INTERFACE LP5553 is compliant with the SPMI specification low-speed device category and operates at bus speeds below 15 MHz. SPMI interface controls the various voltages, modes and states of the regulators in the LP5553. SPMI control of DC/ DC 1 and 2 facilitates PowerWise AVS and DVS operation. LP5553 implements two non-request capable logic slaves in addresses N and N+1. N is selectable with SA[3:0] pins. Both slaves in the LP5553 support the following SPMI commands as described in the SPMI specification: • Reset • Sleep • Shutdown • Wakeup • Register Read • Register Write • Register 0 Write • Authenticate Please see the SPMI specification for a complete description of the interface standard. The 2-wire SPMI interface is composed of the SCLK and SDATA pins on the LP5553. SCLK is always an input to the LP5553 and should be driven by a SPMI master in the system. The SCLK clock rate can operate from 32 kHz to 15 MHz. SDATA is a bi-directional serial data line. It can drive a 50pF line and meet timing standards for a 15 MHz SPMI bus. Both signals are referenced to the voltage present at VO2, the LDO2 output voltage. Both signals contain an internal pulldown resistor of ~1 MΩ, in accordance with the SPMI specification. Unsupported Features LP5553 does not support optional SPMI commands: Extended Register Read and Write, Extended Register Read Long, Extended Register Write Long and MIPI Descriptor Block (DDB) Slave Read. LP5553 does not support any master specific commands. SPMI slaves are divided into Request Capable Slaves and Non-Request Capable Slaves. Request Capable Slaves have capability to initiate and send sequences to any other Master or Slave connected to the SPMI bus. LP5553 is Non-Request Capable Slave and thus it is not able to initiate sequences. Please refer to the SPMI specification for a complete description of all SPMI functionality. SLAVE ADDRESSING DESCRIPTION SPMI supports up to 16 logical slaves in the same system. The LP5553 contains 2 logical slaves. The 3 MSBs of the LP5553’s slave address are set by the SA1, SA2 and SA3 pins. They are actively decoded by the LP5553 for every transaction. The LSB of the slave address is hardwired inside the LP5553. Slave ‘N’ will always be located at SA[0] = 0 and slave ‘N+1’ will always exist at SA[0] = 1. As an example, if we were to tie SA1 = SA3 = VDD and SA2 = GND in our system, then the LP5553’s slave ‘N’ would be located at SA[3:0] = 0xA and slave ‘N+1’ would be SA[3:0] = 0xB. CONTROL AND STATUS SIGNALS The LP5553 implements all 3 of the SPMI control and status signals. ENABLE and RESETN are inputs to the LP5553 that allow for power-up and power-down sequencing, as well as resetting the EMU to a known state. Both ENABLE and RESETN must be a logic ‘1’ during normal operation. PWROK is an indicator to the system that the LP5553 is in regulation and power is stable. It’s output is dependent upon the state of the two slave devices. Value of PWROK signal is logic ‘1’ if at least one of the slaves is in active or sleep state. See Table 1, “PWROK Value Per Slave State,” below for details. All 3 signals are asynchronous signals. TABLE 1. PWROK Value Per Slave State SLAVE (N+1) STARTUP SLAVE (N) STARTUP ACTIVE SLEEP SHUTDOWN 0 1 1 0 ACTIVE 1 1 1 1 SLEEP 1 1 1 1 SHUTDOWN 0 1 1 0 27 www.national.com LP5553 GENERAL PURPOSE OUTPUTS The LP5553 contains 3 digital output pins that can be used as the system designer sees fit. By default, they are configured as open-drain outputs, outputting a logic ‘0’. They can be changed to a push-pull CMOS output by clearing Slave ‘N’, R13[3]. In the open-drain configuration, they can be referenced to any voltage less than the VDD of the LP5553. The push-pull output mode will reference the high-side to the voltage of LDO2. The 3 GPO pins are guaranteed to sink and source 1mA of current. SLAVE OPERATING STATES Each slave in the LP5553 has four operating states: Startup, Active, Sleep and Shutdown. (Figure 1) 30040645 FIGURE 1. LP5553 Slave State Diagram The Startup state is the default state for both slaves after reset. All regulators are off and PWROK output is a ‘0’. The device will move to the Active state when the external ENABLE and RESETN signals are both pulled high. After the state transition completes, both slaves will be in the Active state, but each slave will maintain its own independent state thereafter. The default, factory-programmed power-up sequence of the LP5553 can be seen in Figure 2. From the global ENABLE of the chip, there is ~80 µs of time for powering on and stabilizing internal support circuitry. Once this time has expired, the startup time slots begin. Table 2 shows the time slots that each regulator begins in. Note that for the switchers, there is an additional ~75 µs of set-up time from the beginning of the time slot until the soft-start ramp begins. 30040606 FIGURE 2. LP5553 Startup Timing www.national.com 28 LP5553 TABLE 2. Factory Programmed Startup Time Slots Time slot 0 1 2 3 4 Start time (µs) 0 32 64 96 128 Regulator(s) LDO2 LDO5/AVS1 LDO1/AVS2 LDO3 LDO4 In the Active state, all regulators that are enabled are on and their outputs are defined by their programmed register values. If the Active state has been reached from the Startup state, the regulators will be programmed to their default value. In the Active state, the SPMI master has complete control over the LP5553’s operation. The PWROK output is ‘1’ if either slave is in this state. The Sleep state is entered by issuing the Sleep command on the SPMI bus. The core regulator of the addressed slave and the associated memory LDO will both respond to the Sleep command. For the first 32 µs after the command is decoded, the core regulator will transition to its zero-code value of 0.6V and the LDO will move to its POR value of 1.25V. After the 32 µs has expired, the core regulator will be turned off and the LDO will transition to its memory retention value as programmed in register R2. See Figure 3. LDO1, LDO2 and LDO5 are unaffected by the Sleep command and will maintain their programmed values. They may be turned off manually, if desired. The LP5553 will still respond to all SPMI traffic as long as LDO2 remains active. 30040665 FIGURE 4. Wakeup Behavior of Core and Memory The Shutdown command will place the addressed slave in the Shutdown state. This command may be issued to any slave in either the Active or Sleep states. All regulators within that state will turn off. The LP5553 holds out one exception to this rule. LDO1, LDO2 and LDO5 act as a shared resource between the two slave devices in the EMU. Therefore, placing just slave ‘N’ into Shutdown will not turn off these regulators even though their registers exist within that space. Slave ‘N’ can be in the Shutdown state, but as long as Slave ‘N+1’ is still in either Active or Sleep states, these shared LDOs will remain on and SPMI traffic will be decoded. When only one of the slaves is in the Shutdown state, it can be started up by sending the Reset command to that slave. Once the Shutdown command has been sent to both slaves, all regulators on the LP5553 will be turned off. The PWROK signal will be ‘0’ if both slaves are in the Shutdown state. The only way to transition away from the Shutdown state is by disabling or resetting the LP5553. By taking the ENABLE pin or the RESETN pin low, the LP5553 will transition to the Startup state. Power-down sequencing is not actively managed by the LP5553 logic, but can be handled by turning off regulators in the desired order within the application, prior to Shutdown. PWM/BURST-PWM OPERATION The switching regulators in the LP5553 have two modes of operation, pulse width modulation (PWM) and “Burst”-PWM. In PWM, the converter switches at 3.6 MHz. Each period can be split into two cycles. During the first cycle, the high-side switch is on and the low-side switch is off. During this cycle, the inductor current is rising. In the second cycle, the highside switch is off and the low-side switch is on causing the inductor current to decrease. The output ripple voltage is lowest in PWM mode. As the load current decreases, the converter efficiency becomes worse due to switching losses. The LP5553 will automatically transition to Burst mode at light load current levels. The exact transition point is dependent upon the present operating environment and the mode assessment is constantly evaluated. The transition is approximately equal to: 30040664 FIGURE 3. Sleep Behavior of Core and Memory A slave may return to the Active state by issuing the Wakeup command. This will result in the core regulator turning on after a ~75 µs delay and a soft-start ramp. It will wake up at its maximum value of 1.235V. The associated memory LDO will go to its default POR value of 1.25V until the core has reached the end of its soft-start period and then will transition to its programmed configuration (i.e., either tracking the core or to the value programmed in R1). See Figure 4. The PWROK output is ‘1’ if either slave is in this state. 30040666 In this mode, the output voltage will be allowed to coast with no switching action by the regulator. When the output voltage dips to 1% below nominal, the switches are enabled, the voltage is boosted back up to the programmed value and the 29 www.national.com LP5553 coast process repeats itself. If the user desires tighter control of the output voltage, at the expense of light-load efficiency, the switchers can be commanded to stay in PWM-only mode by setting bit 0 of R10 in the slave’s registers. CURRENT LIMITING A current limit feature exists for all regulators to help protect the LP5553 and external components during overload conditions. The switcher's current limit feature will trip around 1.2A (typ). Once the fault has occurred and current limit has been entered, the switcher will not resume operation until the output current has decreased to a hysteretic low-level set point. Normal operation will proceed after the fault has been cleared. Likewise, the LDOs all implement current limit and will turn off their pass element when their trip point is reached. Please refer to the Electrical Characteristics section for details. SOFT START Both switching regulators implement a digital soft-start feature to limit in-rush current during the Startup to Active state transition. The voltage output of the switchers will be gradually increased to the default value of 1.235V. An unloaded switcher output will reach its final value in 120 µs (typ.) while a fully loaded switcher – 800 mA -- will reach its output in 135 µs (typ). Because the LP5553 uses voltage increments to handle soft-start, its turn-on time is less dependent on output capacitance and load current than regulators that gradually increase current limit to implement soft-start. LDO2 The on-board LDO2 regulator has special significance to the LP5553. All digital data on the SCLK, SDATA and the GPOx pins while in push-pull mode, is referenced to this voltage. This regulator is used internally to power the I/O drivers. As such, this regulator must be on in order to communicate with the LP5553. The user should ensure that this regulator does not go into dropout or SPMI communication will most likely not be possible. If it is not desirable to use this regulator in the system, the user can turn this regulator off by setting bit 4 of R10 in Slave ‘N’ during system initialization while back-driving the required I/O voltage onto the pin. TRACKING, SLEW RATE LIMITING AND LOW IQ BITS There are 3 bits in each slave’s R13 register that determine the performance and operational behavior of the VCOREx and VO3/VO4 outputs. Their significance and interaction is described below. The Low IQ bit setting in R13, bit 0, of each slave allows the selection of a lower IQ bias point at the expense of decreased output current capability for VO3 and VO4. At reset, the default setting is high IQ mode (i.e., bit 0 is cleared) which results in a 50 mA output capability for the associated LDO. If bit 0 is set, the quiescent current draw of the part will decrease, but the output current capability of the associated LDO will drop to 5 mA. Setting VO3 and VO4 up for low I Q mode is useful in situations where just a trickle of current is required, such as when maintaining some type of low-power memory. The Tracking bit, bit 1 in R13, determines whether or not the LDO3 voltage will track the VCORE1 voltage in Slave ‘N’. Slave ‘N+1’ has its own tracking bit which will determine whether LDO4 tracks VCORE2. Each slave device can be independently configured to tracking or independent mode. When set to operate independently, LDO3 and LDO4 will maintain a voltage output equal to the programmed value of R1 while in the Active state. When set to operate in tracking mode, LDO3 and LDO4 will track the output voltage of their associated switcher, attempting to maintain approximately a 25 mV positive offset. There is some interaction between the Low IQ and Tracking bits based on the state of the slave device and that is detailed in the following table: TABLE 3. Tracking, IQ Bit, Slave State Truth Table Input Tracking, R13[1] 0 0 0 0 1 1 1 1 Low IQ, R13[0] 0 0 1 1 0 0 1 1 State Active Sleep Active Sleep Active Sleep Active Sleep Output LDO3/LDO4 Capability 50 mA 50 mA 5 mA 5 mA 50 mA 50 mA 50 mA 5 mA The final bit, the Slew Rate Limiting bit (R13[2]), places a limit on how fast the output voltage of the VCOREx regulators can change. If slew rate limiting is not enabled while in tracking mode (i.e., R13[2] is cleared), then the switcher will achieve its new programmed value faster than the tracking LDO can change its output. By setting the Slew Rate Limiting bit, the LP5553 will attempt to keep the positive offset of the tracking LDO in relation to the VCOREx output. For AVS systems, the expected configuration is to have all 3 bits, R13[2:0] set to ‘1’. It generally will not make sense to set the Slew Rate Limiting bit while not in tracking mode. Setting all 3 bits will result in a system which has the following properties: 1. The tracking LDO will maintain positive offset from VCOREx in Active state. 2. Tracking LDO will be 50mA output capable in Active state and 5mA capable in Sleep state. www.national.com 30 LP5553 Application Hints SWITCHERS Input Capacitors The input capacitor to a switching regulator supplies the AC switching current drawn from the switching action of the internal power FETs. The input current of a buck converter is discontinuous, so the ripple current supplied by the input capacitor is large. The input capacitor must be rated to handle this current: The input capacitor must be rated to handle both the RMS current and the dissipated power. A 10 µF ceramic capacitor, rated to handle at least 10V, is recommended for each PVDDx/PGNDx pair. Inductor A 1µH inductor should be used for the switchers' output filter. The inductor should be rated to handle the peak load current plus the ripple current: 30040648 The power dissipated in the input capacitor is given by: 30040650 30040649 Suggested Inductors and Their Suppliers Model LPS3010–102 LQM31PN1R0MC0 Coilcraft muRata Vendor Dimensions LxWxH (mm) 3.0 x 3.0 x 1.0 3.2 x 1.6 x 0.5 DCR (Typical) 85 mΩ 140 mΩ Output Capacitors The switchers in the LP5553 are designed to be used with 10 µF of capacitance in the output filter. It is recommended that a 10 µF ceramic capacitor, rated to handle at least 10V and comprised of X5R dielectric material, be chosen. The output capacitor of a switching regulator absorbs the AC ripple current from the inductor and provides the initial response to a load transient. The ripple voltage at the output of the converters is the product of the ripple current flowing through the output capacitor and the impedance of the capacitor. The impedance of the capacitor can be dominated by capacitive, resistive, or inductive elements within the capacitor or the PCB interconnect, depending upon the frequency of the ripple current. Ceramic capacitors are predominantly used in portable systems and have very low ESR and should remain capacitive given good PCB layout practices. The switcher peak-to-peak output voltage ripple in steady state can be calculated as: 30040662 Suggested Switcher Output Capacitors and Their Suppliers Model GRM219R61A106KE44 LMK212BJ106KD Vendor muRata Taiyo Yuden Value 10 µF 10 µF Type Ceramic, X5R Ceramic, X5R Voltage 10V 10V Case Size (Height) 0805 (0.85 mm) 0805 (0.85 mm) A NOTE ABOUT CAPACITORS Capacitors are typically specified by their manufacturers as a particular value +/-X%. These specified values are only valid for a particular test condition that is often not applicable to the final application circuit. If you were to take a ceramic 10 µF capacitor in 0805 package and measure it with an LCR meter, a typical result would be around 7 µF. This is before you even insert the capacitor into the application circuit. Capacitance will decrease with increasing frequency and DC bias point and will generally vary with temperature. A typical 6.3V, 10 µF, 0603 capacitor may only be providing 4 - 5 µF of capacitance when used as the output capacitor in the switching regulators’ loop filter. It is highly recommended that measurements be done on your selected capacitor(s) to ensure you have the proper amount of capacitance. 31 www.national.com LP5553 LDOs Input Capacitors While not mandatory, it is highly recommended that some input capacitance be provided for the DVDDx and AVDDx pins. Typical values may be in the 0.1 - 1.0 µF range. These capacitors will provide bypass for the LP5553 control electronics and LDOs. Output Capacitors The output capacitor of an LDO sets a low frequency pole and a high frequency zero in the control loop of an LDO, as well as providing the initial response for a load transient. The capacitance and the equivalent series resistance (ESR) of the capacitor must be within a specified range to meet stability requirements. The LDOs in the LP5553 are designed to be used with ceramic output capacitors. The following table can be used to select suitable output capacitors: LDO Output Capacitor Selection Guide Output Capacitance Range (Recommended Typical Value) LDO1 LDO2 LDO3 LDO4 LDO5 1.0 - 20 µF (2.2 µF) 2.0 - 20 µF (4.7 µF) 0.7 - 2.2 µF (1.0 µF) 0.7 - 2.2 µF (1.0 µF) 2.0 - 20 µF (4.7 µF) ESR Range 5 mΩ - 500 mΩ 5 mΩ - 500 mΩ 5 mΩ - 500 mΩ 5 mΩ - 500 mΩ 5 mΩ - 500 mΩ as similarly to the example artwork as possible. Everything on the outer ring of the micro SMD should be routed on the component layer while microvias are used to escape the remaining signals on the adjacent layer. The layout should be done in the following order to ensure best performance: 1. Switchers 2. System Power Management Interface (SPMI) 3. Input Caps 4. LDO Output Caps 5. Any remaining layout For good performance of the circuit, it is essential to place the input and output capacitors as close as physically possible to the associated pin. Sensitive components should be placed far from those components with high switching currents. It’s a good practice to minimize high-current and switching current paths. DC/DC Buck Switching Regulators Due to the high switching currents and accuracy of the LP5553, this is the most crucial aspect of the layout. And because the switchers are almost a complete mirror image of one another on the part, the design is most easily placed symmetrically about the part. The 10µF input capacitors should be placed first, as near to PVDDx and PGNDx as possible. PVDDx (pins A6 and A1) are the voltage rails for the high-side power FETs. PGNDx (pins A4 and A3) are the return paths for the low-side power FETs. As seen with C3 and C4 in the artwork, these components have their associated pads very near the pins that they will decouple. These capacitors are important in sourcing charge during switching events. The 10µF output capacitors are the next components to be placed. They can be seen in the artwork as C1 and C2. Best performance of the LP5553 will be realized by maintaining tight physical coupling of the grounds of the input capacitor, output capacitor and PGND pin for each switcher. By placing the input/output capacitors as depicted, a channel is created that will allow routing the switching node out to the inductor between the pads of the input and output capacitors. The output magnetics should be placed in a way that best allows the switching node, output node and supplied load to be routed easily. The inductors and associated connections, are the least sensitive to layout variation. Note that the evaluation board contains a 0-ohm series resistor between the switching node and the inductor. This is included as a means to more easily make measurements on the evaluation board and is NOT required in the application circuit. Once placement of these components has been completed, the associated wiring/routing should be done. The switching nodes should be routed to their associated inductors. Next, a ground polygon and/or plane should be used to tie all capacitor grounds together and to the PGNDs. An example of this is shown in the board artwork. Here we have a pour on the top layer that connects everything together and we stitched it into the ground plane to maintain the same potential at both points. There will be quite a bit of switching current in this area so it should be physically isolated from other sensitive circuitry. Once the ground connections are in place, proceed to routing the VIN connections. Finally, the FBx and RGND contacts should be routed. The RGND should tie into a quiet location that will track the potential of the PGND pins. On the evaluation board layout, this connection was made at the edge of the ground polygon on the top layer. Evaluation board contains a 0-ohm series resistor (R13) on the RGND line. This 32 Dropout Voltages All linear regulators are subject to dropout. Dropout Voltage is the minimum voltage required across the regulator (VIN VOUT) to maintain a constant, specified output voltage. The LP5553 has a VIN range of 2.7V – 4.8V. VO1, VO3 and VO4 cannot be programmed to a level that would make dropout a factor. However, VO2 and VO5 can reach as high as 3.3V on their outputs. Both of those regulators have a dropout voltage of 260mV (MAX). To ensure proper operation of those regulators, the user should ensure that VIN ≥ (VOx-PROGRAMMED + 260 mV). If a regulator does go into dropout, the output voltage will start to track the input: VO = VIN - VDROPOUT. Also, the PSRR will go to zero, meaning any noise at the input will be seen at the output. BOARD LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DCDC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter IC, resulting in poor regulation or instability. Good layout for the LP5553 can be implemented by following design rules below. See Figure 5 through Figure 17 for a good example of proper layout (LP5553 Evaluation Board). It is also recommended to reference AN-1112 for information on the micro SMD package and its requirements. The evaluation board is comprised of four layers. From top to bottom they are: 1. Top layer, component side 2. Ground plane 3. VIN plane 4. Bottom layer Being a very high performance EMU in a small physical package requires that some care be taken when placing the IC into the application circuit. The breakout of the IC should be done www.national.com LP5553 is not required in the application circuit. The FB lines should closely match the RGND routing to reduce the inductive loop of this pair. The FB and RGND lines make up a highside and low-side sense connection to maintain the accuracy of the switcher outputs. The FB line should cross the switching trace as close to perpendicular as possible and tie into the output node of the regulator. Low impedance power connections should be maintained for all of these connections. SPMI Routing The System Power Management Interface SCLK and SDATA lines should then be routed to the appropriate master in the system. If this is a multi-master and/or multi-slave system, care should be taken in matching the trace lengths of all segments of the SPMI bus. Additionally, the designer must ensure that the electrical characteristics of the interconnect do not violate the restrictions in the SPMI specification. Input Capacitors Any additional input decoupling capacitors that are part of the design should now be placed and routed. In the case of the evaluation board, this includes capacitors C5 and C6. They are general purpose caps and are tied directly to the VIN plane on the board. It is not mandatory to include additional bypass caps, however it is recommended. Low impedance connections are required to allow the capacitors to function at their peak performance. Regardless of any decoupling capacitors, EVERY VIN CONNECTION SHOULD HAVE ITS OWN ROUTING FROM THE SOURCE. Vias and/or traces should NOT be shared amongst VIN pins. The PVDDx pins especially should have their own separate supply connections. LDO Output Capacitors This step involves placing the output capacitors of the LDO regulators. If an LDO will not be used, it is not necessary to place its output capacitor in the design. These capacitors should be placed as physically close to the LP5553 IC as possible. Again, use low-impedance connections to the output capacitors for best performance. 33 www.national.com LP5553 Evaluation Board Schematic www.national.com 30040667 34 FIGURE 5. LP5553 Evaluation Board Schematic LP5553 30040668 FIGURE 6. Composite View 30040669 FIGURE 7. Top Silk Screen 35 www.national.com LP5553 30040670 FIGURE 8. Top Layer 30040671 FIGURE 9. Layer 2, Ground Plane www.national.com 36 LP5553 30040672 FIGURE 10. Layer 3, VIN Plane 30040673 FIGURE 11. Bottom Layer 37 www.national.com LP5553 30040680 FIGURE 12. Bottom Silk Screen www.national.com 38 LP5553 30040674 FIGURE 13. Compose View Close Up 30040676 FIGURE 14. Top Layer Close Up 30040681 FIGURE 15. L2 Close Up 39 www.national.com LP5553 30040678 FIGURE 16. L3 Close Up 30040679 FIGURE 17. Bottom Layer Close up Bill of Materials (LP5553 Evaluation Board) Designator A B C CA1 CA2 C1 C2 C3 C4 C5 C6 Part Value 2x13 Pin Array 2x13 Pin Array 2x13 Pin Array NL NL 10 µF 10 µF 10 µF 10 µF 0.1 µF/16V/X5R/ 10% 0.1 µF/16V/X5R/ 10% LMK212BJ106KD LMK212BJ106KD LMK212BJ106KD LMK212BJ106KD P/N 9-146252-0-13 9-146252-0-13 9-146252-0-13 Footprint DIP-26 DIP-26 DIP-26 0402 0402 0805 0805 0805 0805 0402 0402 Description Mainboard Connector Mainboard Connector Mainboard Connector Manufacturer AMP/Tyco AMP/Tyco AMP/Tyco AVDD1 Bypass Cap N/A AVDD2 Bypass Cap N/A SW1 Output Cap SW2 Output Cap SW1 Input Cap SW2 Input Cap General Bypass Cap General Bypass Cap Taiyo Yuden Taiyo Yuden Taiyo Yuden Taiyo Yuden N/A N/A www.national.com 40 LP5553 Designator C7 C8 C9 C10 C11 C12 L1 L2 PWR_ON PWROK R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 SW1_O SW2_O U1 U2 Part Value 2.2 µF/10V/X5R/ 10% 4.7 µF/10V/X5R/ 10% 4.7 µF/10V/X5R/ 10% 1.0 µF/10V/X5R/ 10% 1.0 µF/10V/X5R/ 10% 0.1 µF/16V/X5R/ 10% 1 µH 1 µH Red LED Green LED NL NL 10k/0.1W/5% 10k/0.1W/5% 10k/0.1W/5% 10k/0.1W/5% 10k/0.1W/5% 10k/0.1W/5% 1.5k/0.1W/5% 1.5k/0.1W/5% 240-ohm/0.1W/5% 160-ohm/0.1W/5% 0-ohm/0.063W/5% 0-ohm/0.1W/5% 0-ohm/0.1W/5% LP5553 PMIC Tri-State Buffer P/N Footprint 0603 0603 0603 Description LDO1 Output Cap LDO2 Output Cap LDO5 Output Cap LDO3 Output Cap LDO4 Output Cap PWROK Buffer Bypass Cap SW1 Output Inductor SW2 Output Inductor Red Power On Indicator Green PWROK Indicator Manufacturer N/A N/A N/A Taiyo Yuden Taiyo Yuden N/A Coilcraft Coilcraft Lite-On Lite-On LMK105BJ105KV LMK105BJ105KV 0402 0402 0402 LPS3010-102ML LPS3010-102ML LTST-C171KRKT LTST-C170KGKT LPS30xx LPS30xx 0805 0805 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0402 0603 0603 Pull-up for ENABLE N/A Pull-up for RESETN N/A SA1 Pull-down SA2 Pull-down SA3 Pull-down GPO0 Pull-up GPO1 Pull-up GPO2 Pull-up Mainboard Presence Detect Mainboard Presence Detect Red LED Current Limit Res. N/A N/A N/A N/A N/A N/A N/A N/A N/A Green LED Current N/A Limit Res. RGND Isolation Res. N/A Measurement Pads N/A SW1 Measurement Pads N/A SW2 PMIC National Semiconductor LP5553 NC7SZ126M5 µSMD-36 SOT23-5 PWROK LED Buffer Fairchild Semiconductor 41 www.national.com LP5553 Physical Dimensions inches (millimeters) unless otherwise noted 36-bump micro SMD Package NS Package Number TLA36TTA www.national.com 42 LP5553 43 www.national.com LP5553 - PowerWise® AVS Energy Management Unit with SPMI Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage Reference PowerWise® Solutions Serial Digital Interface (SDI) Temperature Sensors Wireless (PLL/VCO) www.national.com/amplifiers www.national.com/audio www.national.com/timing www.national.com/adc www.national.com/interface www.national.com/lvds www.national.com/power www.national.com/switchers www.national.com/ldo www.national.com/led www.national.com/vref www.national.com/powerwise www.national.com/sdi www.national.com/tempsensors www.national.com/wireless WEBENCH® Tools App Notes Reference Designs Samples Eval Boards Packaging Green Compliance Distributors Design Support www.national.com/webench www.national.com/appnotes www.national.com/refdesigns www.national.com/samples www.national.com/evalboards www.national.com/packaging www.national.com/quality/green www.national.com/contacts www.national.com/quality www.national.com/feedback www.national.com/easy www.national.com/solutions www.national.com/milaero www.national.com/solarmagic www.national.com/AU Quality and Reliability Feedback/Support Design Made Easy Solutions Mil/Aero SolarMagic™ Analog University® THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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