LP5996SD-3033

LP5996 Dual Linear Regulator with 300mA and 150mA Outputs November 2006 LP5996 Dual Linear Regulator with 300mA and 150mA Outputs General Description The LP5996 is a dual low dropout regulator. The first regulator can source 150mA, while the second is capable of sourcing 300mA. The LP5996 provides 1.5% accuracy requiring an ultra low quiescent current of 35µA. Separate enable pins allow each output of the LP5996 to be shut down, drawing virtually zero current. The LP5996 is designed to be stable with small footprint ceramic capacitors down to 1µF. The LP5996 is available in fixed output voltages and comes in a 10 pin, 3mm x 3mm, LLP package. . Key Specifications n n n n Input Voltage Range Low Dropout Voltage Ultra-Low IQ (enabled) Virtually Zero IQ (disabled) 2.0V to 6.0V 210mV at 300mA 35µA < 10nA Package All available in Lead Free option. 10 pin LLP 3mm x 3mm For other package options contact your NSC sales office. Features n 2 LDO Outputs with Independent Enable n 1.5% Accuracy at Room Temperature, 3% over Temperature n Thermal Shutdown Protection n Stable with Ceramic Capacitors Applications n Cellular Handsets n PDA’s n Wireless Network Adaptors Typical Application Circuit 20171501 © 2006 National Semiconductor Corporation DS201715 www.national.com LP5996 Functional Block Diagram 20171506 Pin Descriptions LLP-10 Package Pin No 1 2 3 4 Symbol VIN EN1 EN2 CBYP Name and Function Voltage Supply Input. Connect a 1µF capacitor between this pin and GND. Enable Input to Regulator 1. Active high input. High = On. Low = OFF. Enable Input to Regulator 2. Active high input. High = On. Low = OFF. Internal Voltage Reference Bypass. Connect a 10nF capacitor from this pin to GND to reduce noise and improve line transient and PSRR. This pin may be left open. No Connection. Do not connect to any other pin. Common Ground pin. Connect externally to exposed pad. No Connection. Do not connect to any other pin. No Connection. Do not connect to any other pin. Output of Regulator 2. 300mA maximum current output. Connect a 1µF capacitor between this pin to GND. Output of Regulator 1. 150mA maximum current output. Connect a 1µF capacitor between this pin to GND. Common Ground. Connect to Pin 6. 5 6 7 8 9 10 Pad N/C GND N/C N/C VOUT2 VOUT1 GND www.national.com 2 LP5996 Connection Diagram LLP-10 Package 20171503 See NS package number SDA10A 3 www.national.com LP5996 Ordering Information (LLP-10) For other voltage options, please contact your local NSC sales office. Output Voltage (V) 0.8 / 3.3 Order Number LP5996SD-0833 LP5996SDX-0833 LP5996SD-0833 LP5996SDX-0833 1.5 / 2.5 LP5996SD-1525 LP5996SDX-1525 LP5996SD-1525 LP5996SDX-1525 2.8 / 2.8 LP5996SD-2828 LP5996SDX-2828 LP5996SD-2828 LP5996SDX-2828 3.0 / 3.0 LP5996SD-3030 LP5996SDX-3030 LP5996SD-3030 LP5996SDX-3030 3.0 / 3.3 LP5996SD-3033 LP5996SDX3033 LP5996SD-3033 LP5996SDX3033 3.3 / 0.8 LP5996SD-3308 LP5996SDX-3308 LP5996SD-3308 LP5996SDX-3308 3.3 / 3.3 LP5996SD-3333 LP5996SDX-3333 LP5996SD-333 LP5996SDX-3333 NOPB NOPB L182B NOPB NOPB L205B NOPB NOPB L179B NOPB NOPB L181B NOPB NOPB L180B NOPB NOPB L177B Spec NOPB NOPB Package Marking L176B Supplied As 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Reel 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Re 1000 Units, Tape-and-Reel 4500 Units, Tape-and-Re www.national.com 4 LP5996 Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Input Voltage VOUT1, VOUT2, EN1, and EN2 Voltage to GND Junction Temperature (TJ-MAX) Lead/Pad Temp. (Note 3) Storage Temperature Continuous Power Dissipation Internally Limited(Note 4) -0.3V to 6.5V -0.3V to (VIN + 0.3V) with 6.5V (max) 150˚C 235˚C -65˚C to 150˚C ESD Rating(Note 5) Human Body Model Machine Model 2.0kV 200V Operating Ratings(Notes 1, 2) Input Voltage EN1, EN2 Voltage Junction Temperature Ambient Temperature TARange (Note 6) 2.0V to 6.0V 0 to (VIN + 0.3V) to 6.0V (max) -40˚C to 125˚C -40˚C to 85˚C Thermal Properties(Note 1) Junction To Ambient Thermal Resistance(Note 7) θJALLP-10 Package 55˚C/W Electrical Characteristics(Notes 2, 8) Unless otherwise noted, VEN = 950mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0µF. Typical values and limits appearing in normal type apply for TA = 25˚C. Limits appearing in boldface type apply over the full junction temperature range for operation, −40 to +125˚C. Symbol VIN ∆VOUT Parameter Input Voltage Output Voltage Tolerance (Note 9) IOUT = 1mA 1.5V < VOUT ≤ 3.3V VOUT ≤ 1.5V Line Regulation Error Load Regulation Error VIN = (VOUT(NOM) + 1.0V) to 6.0V IOUT = 1mA to 150mA (LDO 1) IOUT = 1mA to 300mA (LDO 2) VDO Dropout Voltage (Note 10) IOUT = 1mA to 150mA (LDO 1) IOUT = 1mA to 300mA (LDO 2) IQ Quiescent Current LDO 1 ON, LDO 2 ON IOUT1= IOUT2 = 0mA LDO 1 ON, LDO 2 OFF IOUT1 = 150mA LDO 1 OFF, LDO 2 ON IOUT2 = 300mA LDO 1 ON, LDO 2 ON IOUT1 = 150mA, IOUT2 = 300m VEN1 = VEN2 = 0.4V ISC IOUT Short Circuit Current Limit Maximum Output Current LDO 1 LDO 2 LDO 1 LDO 2 0.03 85 26 110 210 35 45 45 70 0.5 420 550 150 300 Conditions Typ Limit Min 2 -2.5 -3.75 -2.75 -4 Max 6 +2.5 +3.75 +2.75 +4 0.3 155 µV/mA 85 220 mV 550 100 110 µA 110 170 10 750 840 nA mA mA Units V % %/V 5 www.national.com LP5996 Electrical Characteristics(Notes 2, 8) (Continued) Unless otherwise noted, VEN = 950mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0µF. Typical values and limits appearing in normal type apply for TA = 25˚C. Limits appearing in boldface type apply over the full junction temperature range for operation, −40 to +125˚C. Symbol Parameter Power Supply Rejection Ratio (Note 11) Conditions f = 1kHz, IOUT = 1mA to 150mA CBYP = 10nF LDO1 LDO2 Typ 58 70 dB 45 60 36 µVRMS 75 160 20 0.005 2 0.95 To 95% Level CBYP = 10nF 0.1 5 0.4 ˚C Limit Min Max Units PSRR f = 20kHz, IOUT LDO1 = 1mA to 150mA LDO2 CBYP = 10nF en Output noise Voltage (Note 11) BW = 10Hz to 100kHz CBYP = 10nF Temperature Hysteresis Enable Control Characteristics IEN VIL VIH TON Transient Response Input Current at VEN1 or VEN2 Low Input Threshold High Input Threshold Turn On Time (Note 11) VEN = 0.0V VEN = 6V VOUT = 0.8V VOUT = 3.3V TSHUTDOWN Thermal Shutdown µA V V Timing Characteristics 300 20 µs Line Transient Response |δVOUT| Trise = Tfall = 10µs (Note 11) δVIN = 1VCBYP = 10nF Load Transient Response |δVOUT| (Note 11) Trise = Tfall = 1µs LDO 1 IOUT = 1mA to 150mA LDO 2 IOUT = 1mA to 300mA 175 mV (pk - pk) 150 Note 1: Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All Voltages are with respect to the potential at the GND pin. Note 3: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN-1187, Leadless Leadframe Package. Note 4: Internal thermal shutdown circuitry protects the device from permanent damage. Note 5: The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin. Note 6: The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125˚C), the maximum power dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part/package in the application (θJA), as given by the following equation: TA(max) = TJ(max-op) - (θJA x PD(max)). Note 7: Junction to ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power dissipation is possible, special care must be paid to thermal dissipation issues in board design. Note 8: Min Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm. Note 9: VIN(MIN) = VOUT(NOM) + 0.5V, or 2.0V, whichever is higher. Note 10: Dropout voltage is voltage difference between input and output at which the output voltage drops to 100mV below its nominal value. This parameter only for output voltages above 2.0V Note 11: This electrical specification is guaranteed by design. www.national.com 6 LP5996 Output Capacitor, Recommended Specifications Symbol COUT Parameter Output Capacitance Capacitance (Note 12) ESR Conditions Nom 1.0 Limit Min 0.7 5 500 Max Units µF mΩ Note 12: The Capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor is X7R. However, depending on the application, X5R, Y5V and Z5U can also be used. (See capacitor section in Applications Hints). 7 www.national.com LP5996 Typical Performance Characteristics. Unless otherwise specified, CIN = 1.0µF Ceramic, COUT1 = COUT2 = 1.0µF Ceramic, CBYP = 10nF, VIN = VOUT2(NOM) + 1.0V, TA = 25˚C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN. Output Voltage Change vs Temperature Ground Current vs Load Current,LDO1 20171510 20171513 Ground Current vs Load Current, LDO2 Ground Current vs VIN, ILOAD = 1mA 20171514 20171515 Dropout Voltage vs ILOAD, LDO1 Dropout Voltage vs ILOAD, LDO2 20171511 20171512 www.national.com 8 LP5996 Typical Performance Characteristics. Unless otherwise specified, CIN = 1.0µF Ceramic, COUT1 = COUT2 = 1.0µF Ceramic, CBYP = 10nF, VIN = VOUT2(NOM) + 1.0V, TA = 25˚C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN. (Continued) Line Transient, CBYP = 10nF Line Transient, CBYP = 0 20171519 20171520 Load Transient, LDO1 Load Transient, LDO2 20171550 20171551 Noise Density, LDO1 Noise Density, LDO2 20171556 20171557 9 www.national.com LP5996 Typical Performance Characteristics. Unless otherwise specified, CIN = 1.0µF Ceramic, COUT1 = COUT2 = 1.0µF Ceramic, CBYP = 10nF, VIN = VOUT2(NOM) + 1.0V, TA = 25˚C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN. (Continued) Short Circuit Current, LDO1 Short Circuit Current, LDO2 20171552 20171553 Power Supply Rejection Ratio, LDO1 Power Supply Rejection Ratio, LDO2 20171555 20171554 Enable Start-up Time, CBYP = 0 Enable Start-up Time, CBYP = 10nF 20171560 20171561 www.national.com 10 LP5996 Application Hints OPERATION DESCRIPTION The LP5996 is a low quiescent current, power management IC, designed specifically for portable applications requiring minimum board space and smallest components. The LP5996 contains two independently selectable LDOs. The first is capable of sourcing 150mA at outputs between 0.8V and 3.3V. The second can source 300mA at an output voltage of 0.8V to 3.3V. INPUT CAPACITOR An input capacitor is required for stability. It is recommended that a 1.0µF capacitor be connected between the LP5996 input pin and ground (this capacitance value may be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analogue ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input, it must be guaranteed by the manufacturer to have a surge current rating sufficient for the application. There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain approximately 1.0µF over the entire operating temperature range. OUTPUT CAPACITOR The LP5996 is designed specifically to work with very small ceramic output capacitors. A 1.0µF ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5mΩ to 500mΩ, is suitable in the LP5996 application circuit. For this device the output capacitor should be connected between the VOUT pin and ground. It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as attractive for reasons of size and cost (see the section Capacitor Characteristics). The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR value that is within the range 5mΩ to 500mΩ for stability. NO-LOAD STABILITY The LP5996 will remain stable and in regulation with no external load. This is an important consideration in some circuits, for example CMOS RAM keep-alive applications. CAPACITOR CHARACTERISTICS The LP5996 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer. For capacitance values in the range of 0.47µF to 4.7µF, ceramic capacitors are the smallest, least expensive and have the lowest ESR values, thus making them best for eliminating high frequency noise. The ESR of a typical 1.0µF ceramic capacitor is in the range of 20mΩ to 40mΩ, which easily meets the ESR requirement for stability for the LP5996. For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depending on the operating conditions and capacitor type. In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the specification is met within the application. The capacitance can vary with DC bias conditions as well as temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer performance figures in general. As an example, Figure 1 shows a typical graph comparing different capacitor case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result in the capacitance value falling below the minimum value given in the recommended capacitor specifications table (0.7µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for the nominal value capacitor are consulted for all conditions, as some capacitor sizes (e.g. 0402) may not be suitable in the actual application. 20171540 FIGURE 1. Graph Showing a Typical Variation in Capacitance vs DC Bias The capacitance value of ceramic capacitors varies with temperature. The capacitor type X7R, which operates over a temperature range of -55˚C to +125˚C, will only vary the capacitance to within ± 15%. The capacitor type X5R has a similar tolerance over a reduced temperature range of -55˚C to +85˚C. Many large value ceramic capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature varies from 25˚C to 85˚C. Therefore X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25˚C. Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more expensive when comparing equivalent capacitance and voltage ratings in the 0.47µF to 4.7µF range. Another important consideration is that tantalum capacitors have higher ESR values than equivalent size ceramics. This means that while it may be possible to find a tantalum 11 www.national.com LP5996 Application Hints (Continued) capacitor with an ESR value within the stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about 2:1 as the temperature goes from 25˚C down to -40˚C, so some guard band must be allowed. ENABLE CONTROL The LP5996 features active high enable pins for each regulator, EN1 and EN2, which turns the corresponding LDO off when pulled low. The device outputs are enabled when the enable pins are set to high. When not enabled the regulator output is off and the device typically consumes 2nA. If the application does not require the Enable switching feature, one or both enable pins should be tied to VIN to keep the regulator output permanently on. To ensure proper operation, the signal source used to drive the enable inputs must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. BYPASS CAPACITOR The internal voltage reference circuit of the LP5996 is connected to the CBYP pin via a high value internal resistor. An external capacitor, connected to this pin, forms a low-pass filter which reduces the noise level on both outputs of the device. There is also some improvement in PSSR and line transient performance. Internal circuitry ensures rapid charging of the CBYP capacitor during start-up. A 10nF, high quality ceramic capacitor with either NPO or COG dielectric is recommended due to their low leakage characteristics and low noise performance. SAFE AREA OF OPERATION Due consideration should be given to operating conditions to avoid excessive thermal dissipation of the LP5996 or triggering its thermal shutdown circuit. When both outputs are enabled, the total power dissipation will be PD(LDO1) + PD(LDO2) where PD = (VIN - VOUT) x IOUT for each LDO In general, device options which have a large difference in output voltage will dissipate more power with both outputs enabled, due to the input voltage required for the higher output voltage LDO. In such cases, especially at elevated ambient temperature, it may not be possible to operate both outputs at maximum current at the same time. www.national.com 12 LP5996 Physical Dimensions inches (millimeters) unless otherwise noted LLP, 10 Lead, Package NS Package Number SDA10A 13 www.national.com LP5996 Dual Linear Regulator with 300mA and 150mA Outputs THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (″NATIONAL″) PRODUCTS. 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