LP8340

LP8340 Low Dropout, Low IQ, 1.0A CMOS Linear Regulator October 2003 LP8340 Low Dropout, Low IQ, 1.0A CMOS Linear Regulator General Description The LP8340 low-dropout CMOS linear regulator is available in 5V, 3.3V, 2.5V, 1.8V and adjustable output versions. Packaged in the 6ld LLP package and 3ld DPAK. The LP8340 can deliver up to 1.0A output current. Typical dropout voltage is 420mV at 1.0A for the 5.0V version, 540mV at 1.0A for the 3.3V version, 670mV at 1.0A for the 2.5V version and 680mV at 800mA for the 1.8V version. The LP8340 includes a zener trimmed bandgap voltage reference, foldback current limiting and thermal overload limiting. The LP8340 features a PMOS output transistor which unlike PNP type low dropout regulators requires no base drive current. This allows the device ground current to remain less than 50µA over operating temperature, supply voltage and irrespective of the load current. Features n n n n n n n n n n ± 1.5% Typical VOUT tolerance 420mV Typical Dropout @ 1.0A (VO = 5V) Wide Operating Range 2.7V to 10V Internal 1.0A PMOS Output Transistor 19µA Typical Quiescent Current Thermal Overload Limiting Foldback Current Limiting Zener Trimmed Bandgap Reference Space saving LLP package Temperature Range — LP8340C 0˚C to 125˚C — LP8340I −40˚C to 125˚C Applications n n n n Hard Disk Drives Notebook Computers Battery Powered Electronics Portable Instrumentation Typical Applications Fixed VOUT 20060901 Adjustable VOUT 20060902 © 2003 National Semiconductor Corporation DS200609 www.national.com LP8340 Ordering Information Package 6-Pin LLP Part Number LP8340CLD-ADJ LP8340CLDX-ADJ LP8340CLD-1.8 LP8340CLDX-1.8 LP8340CLD-2.5 LP8340CLDX-2.5 LP8340CLD-3.3 LP8340CLDX-3.3 LP8340CLD-5.0 LP8340CLDX-5.0 LP8340ILD-ADJ LP8340ILDX-ADJ LP8340ILD-1.8 LP8340ILDX-1.8 LP8340ILD-2.5 LP8340ILDX-2.5 LP8340ILD-3.3 LP8340ILDX-3.3 LP8340ILD-5.0 LP8340ILDX-5.0 3-Pin DPAK LP8340CDT-1.8 LP8340CDTX-1.8 LP8340CDT-2.5 LP8340CDTX-2.5 LP8340CDT-3.3 LP8340CDTX-3.3 LP8340CDT-5.0 LP8340CDTX-5.0 LP8340IDT-1.8 LP8340IDTX-1.8 LP8340IDT-2.5 LP8340IDTX-2.5 LP8340IDT-3.3 LP8340IDTX-3.3 LP8340IDT-5.0 LP8340IDTX-5.0 Package Marking L041B L042B L043B L051B L044B L078B L079B L080B L081B L082B LP8340CDT-1.8 LP8340CDT-2.5 LP8340CDT-3.3 LP8340CDT-5.0 LP8340IDT-1.8 LP8340IDT-2.5 LP8340IDT-3.3 LP8340IDT-5.0 Transport Media 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 1k Units Tape and Reel 4.5k Units Tape and Reel 75 Units/Rail 2.5k Units Tape and Reel 75 Units/Rail 2.5k Units Tape and Reel 75 Units/Rail 2.5k Units Tape and Reel 75 Units/Rail 2.5k Units Tape and Reel 75 Units/Rail 2.5k Units Tape and Reel 75 Units/Rail 2.5k Units Tape and Reel 75 Units/Rail 2.5k Units Tape and Reel 75 Units/Rail 2.5k Units Tape and Reel TD03B NSC Drawing LDE06A www.national.com 2 LP8340 Connection Diagrams 6-Pin LLP FIXED OUTPUT VOLTAGE 6-Pin LLP ADJUSTABLE OUTPUT VOLTAGE 20060906 20060904 Bottom View Bottom View Note: VIN Pins (Pin 1 & 6) must be connected together externally for full 1 amp operation (500mA max per pin). VOUT Sense (Pin 5) must be connected to VOUT (Pin 4). T0-252 20060905 Top View 3 www.national.com LP8340 Absolute Maximum Ratings 2) (Notes 1, Human Body Model (Note 6) Machine Model 2kV 200V If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN, VOUT, VOUT Sense, ADJ Storage Temperature Range Junction Temperature (TJ) Power Dissipation ESD Rating −0.3V to 12V −65˚C to 160˚C 150˚C (Note 3) Operating Ratings(Notes 1, 2) Supply Voltage Temperature Range LP8340C LP8340I 0˚C to 125˚C −40˚C to 125˚C 2.7 to 10V LP8340C Electrical Characteristics Unless otherwise specified all limits guaranteed for VIN = VO+ 1V, CIN = COUT = 10µF, TJ = 25˚C. Boldface limits apply over the full operating temperature range of TJ = 0˚C to 125˚C Symbol VIN VOUT Parameter Input Voltage Output Voltage Conditions LP8340-ADJ,1.8, 2.5 LP8340-3.3, 5.0 LP8340-ADJ, ADJ = OUT IOUT = 10mA, VIN = 2.7V, TJ = 25˚C 100µA ≤IOUT≤ 800mA, 3.0V ≤VIN≤VOUT +4V 800mA < IOUT ≤1.0A, 3.2V ≤VIN ≤VOUT +4V LP8340-1.8 IOUT = 10mA, VIN = 2.8V, TJ = 25˚C 100µA ≤IOUT ≤800mA, 3.2V ≤VIN≤6V 800mA < IOUT ≤1.0A, 3.4V ≤VIN ≤6V LP8340-2.5 IOUT = 10mA, VIN = 3.8V, TJ = 25˚C 100µA ≤IOUT ≤1.0A, 3.8V ≤VIN ≤6.5V LP8340-3.3 IOUT = 10mA, VIN = 4.3V TJ = 25˚C 100µA ≤IOUT ≤1.0A, 4.3V ≤VIN ≤7.5V LP8340-5.0 IOUT = 10mA, VIN = 6V, TJ = 25˚C 100µA ≤IOUT ≤1.0A, 6V ≤VIN ≤9V ∆VO Load Regulation LP8340-ADJ, ADJ=OUT IOUT = 1mA to 1.0A, VIN = 3.2V LP8340-1.8 IOUT = 1mA to 1.0A, VIN = 3.4V LP8340-2.5 IOUT = 1mA to 1.0A, VIN = 3.5V LP8340-3.3 IOUT = 1mA to 1.0A, VIN = 4.3V LP8340-5.0 IOUT = 1mA to 1.0A, VIN = 6V ∆VO Line Regulation VOUT + 0.5V ≤VIN ≤10V, IOUT = 25mA (Note 7) Min (Note 5) 2.7 Typ (Note 4) Max (Note 5) 10 10 1.269 1.288 1.288 1.827 1.854 1.854 2.538 2.575 3.350 3.399 5.075 5.150 25 30 50 75 100 15 mV mV Units V 1.231 1.213 1.213 1.773 1.746 1.746 2.463 2.425 3.250 3.201 4.925 4.850 1.250 V 1.800 V 2.500 V 3.300 V 5.000 V 6 8 15 20 25 4 www.national.com 4 LP8340 LP8340C Electrical Characteristics Symbol Parameter LP8340-1.8 IOUT = 800mA LP8340-2.5 IOUT = 800mA LP8340-2.5 IOUT = 1.0A (Continued) Unless otherwise specified all limits guaranteed for VIN = VO+ 1V, CIN = COUT = 10µF, TJ = 25˚C. Boldface limits apply over the full operating temperature range of TJ = 0˚C to 125˚C Conditions Min (Note 5) Typ (Note 4) 680 550 670 420 540 330 420 19 450 1600 48 55 Max (Note 5) 1400 1000 1300 800 1000 650 800 50 100 µA µA mA dB mV Units VIN − VO Dropout Voltage (Note 7) (Note 8) LP8340-3.3 LP8340-ADJ, VOUT = 3.3V, IOUT = 800mA LP8340-3.3 LP8340-ADJ, IOUT = 1.0A LP8340-5.0 IOUT = 800mA LP8340-5.0 IOUT = 1.0A IQ ILIMIT Quiescent Current Minimum Load Current Foldback Current Limit Ripple Rejection Ratio TSD Thermal Shutdown Temp. Thermal Shutdown Hyst. ADJ Input Leakage Current VOUT Leakage Current VADJ = 1.5V or 0V LP8340-ADJ ADJ = OUT, VOUT = 2V, VIN = 10V LP8340-1.8, VOUT = 2.5V, VIN = 10V LP8340-2.5, VOUT = 3.5V, VIN = 10V LP8340-3.3, VOUT = 4V, VIN = 10V LP8340-5.0, VOUT = 6V, VIN = 10V en Output Noise 10Hz to 10kHz, RL = 1kΩ, COUT = 10µF VIN ≤10V VIN − VOUT ≤4V VIN − VOUT > 5V VIN − VOUT < 4V VIN (dc) = VOUT + 2V VIN (ac) = 1 VP-P @ 120Hz 160 10 ˚C ± 0.01 ± 100 nA 10 10 10 10 10 250 µVrms µA LP8340I Electrical Characteristics Unless otherwise specified all limits guaranteed for VIN = VO+ 1V, CIN = COUT = 10µF, TJ = 25˚C. Boldface limits apply over the full operating temperature range of TJ = −40˚C to 125˚C Symbol VIN Parameter Input Voltage Conditions LP8340-ADJ,1.8, 2.5 LP8340-3.3, 5.0 Min (Note 5) 2.7 Typ (Note 4) Max (Note 5) 10 10 Units V 5 www.national.com LP8340 LP8340I Electrical Characteristics Symbol VOUT Parameter Output Voltage (Continued) Unless otherwise specified all limits guaranteed for VIN = VO+ 1V, CIN = COUT = 10µF, TJ = 25˚C. Boldface limits apply over the full operating temperature range of TJ = −40˚C to 125˚C Conditions LP8340-ADJ, ADJ = OUT IOUT = 10mA, VIN = 2.7V, TJ = 25˚C 100µA ≤IOUT≤ 800mA, 3.0V ≤VIN≤VOUT +4V 800mA < IOUT ≤1.0A, 3.2V ≤VIN ≤VOUT +4V LP8340-1.8 IOUT = 10mA, VIN = 2.8V, TJ = 25˚C 100µA ≤IOUT ≤800mA, 3.2V ≤VIN≤6V 800mA < IOUT ≤1.0A, 3.4V ≤VIN ≤6V LP8340-2.5 IOUT = 10mA, VIN = 3.8V, TJ = 25˚C 100µA ≤IOUT ≤1.0A, 3.8V ≤VIN ≤6.5V LP8340-3.3 IOUT = 10mA, VIN = 4.3V TJ = 25˚C 100µA ≤IOUT ≤1.0A, 4.3V ≤VIN ≤7.5V LP8340-5.0 IOUT = 10mA, VIN = 6V, TJ = 25˚C 100µA ≤IOUT ≤1.0A, 6V ≤VIN ≤9V Min (Note 5) 1.231 1.213 1.213 1.773 1.746 1.746 2.463 2.425 3.250 3.201 4.925 4.850 Typ (Note 4) Max (Note 5) 1.269 1.288 1.288 1.827 1.854 1.854 2.538 2.575 3.350 3.399 5.075 5.150 25 30 50 75 100 15 mV mV Units 1.250 V 1.800 V 2.500 V 3.300 V 5.000 V ∆VO Load Regulation LP8340-ADJ, ADJ=OUT IOUT = 1mA to 1.0A, VIN = 3.2V LP8340-1.8 IOUT = 1mA to 1.0A, VIN = 3.4V LP8340-2.5 IOUT = 1mA to 1.0A, VIN = 3.5V LP8340-3.3 IOUT = 1mA to 1.0A, VIN = 4.3V LP8340-5.0 IOUT = 1mA to 1.0A, VIN = 6V 6 8 15 20 25 4 ∆VO Line Regulation VOUT + 0.5V ≤VIN ≤10V, IOUT = 25mA (Note 7) LP8340-1.8 IOUT = 800mA LP8340-2.5 IOUT = 800mA LP8340-2.5 IOUT = 1.0A LP8340-3.3 LP8340-ADJ, VOUT = 3.3V, IOUT = 800mA LP8340-3.3 LP8340-ADJ, IOUT = 1.0A LP8340-5.0 IOUT = 800mA LP8340-5.0 IOUT = 1.0A VIN − VO Dropout Voltage (Note 7) (Note 8) 680 550 670 420 540 330 420 19 450 1600 48 55 1400 1000 1300 800 1000 650 800 50 100 µA µA mA dB mV IQ ILIMIT Quiescent Current Minimum Load Current Foldback Current Limit Ripple Rejection Ratio VIN ≤10V VIN − VOUT ≤4V VIN − VOUT > 5V VIN − VOUT < 4V VIN (dc) = VOUT + 2V VIN (ac) = 1 VP-P @ 120Hz www.national.com 6 LP8340 LP8340I Electrical Characteristics Symbol TSD Parameter Thermal Shutdown Temp. Thermal Shutdown Hyst. ADJ Input Leakage Current VOUT Leakage Current VADJ = 1.5V or 0V (Continued) Unless otherwise specified all limits guaranteed for VIN = VO+ 1V, CIN = COUT = 10µF, TJ = 25˚C. Boldface limits apply over the full operating temperature range of TJ = −40˚C to 125˚C Conditions Min (Note 5) Typ (Note 4) 160 10 Max (Note 5) Units ˚C ± 0.01 ± 100 nA LP8340-ADJ ADJ = OUT, VOUT = 2V, VIN = 10V LP8340-1.8, VOUT = 2.5V, VIN = 10V LP8340-2.5, VOUT = 3.5V, VIN = 10V LP8340-3.3, VOUT = 4V, VIN = 10V LP8340-5.0, VOUT = 6V, VIN = 10V 10 10 10 10 10 250 µVrms µA en Output Noise 10Hz to 10kHz, RL = 1kΩ, COUT = 10µF Note 1: Absolute Maximum ratings indicate limits beyond which damage may occur. Electrical specifications do not apply when operating the device outside of its rated operating conditions. Note 2: All voltages are with respect to the potential at the ground pin. Note 3: Maximum Power dissipation for the device is calculated using the following equations: where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance. The value of the θJA for the LLP package is specifically dependant on the PCB trace area, trace material, and the number of layers and thermal vias. For improved thermal resistance and power dissipation for the LLP package, refer to Application Note AN-1187. Note 4: Typical Values represent the most likely parametric norm. Note 5: All limits are guaranteed by testing or statistical analysis. Note 6: Human body model 1.5kΩ in series with 100pF. Note 7: Condition does not apply to input voltages below 2.7V since this is the minimum input operating voltage. Note 8: Dropout voltage is measured by reducing VIN until VO drops 100mV from its normal value. 7 www.national.com LP8340 Typical Performance Characteristics Unless otherwise specified, VIN = VO + 1.5V, CIN = COUT = 10µF X7R ceramic, TJ = 25˚C Output Voltage Change vs. Temperature Dropout Voltage vs. Load Current 20060907 20060908 Ground Current vs. Temperature (ILOAD = 1A) Ground Current vs. Load Current 20060909 20060910 Ground Current vs. Input Voltage Ripple Rejection Ratio vs. Frequency 20060911 20060912 www.national.com 8 LP8340 Typical Performance Characteristics LP8340-1.8V Min VIN (Continued) LP8340-ADJ Min VIN 20060919 20060920 Load Transient Response Line Transient Response (ILOAD = 10mA) 20060913 20060914 Start-up Response Minimum Input Voltage Rise Time 20060915 20060921 9 www.national.com LP8340 Typical Performance Characteristics Minimum Input Voltage Rise Time (Continued) Minimum Input Voltage Rise Time 20060922 20060923 Minimum Input Voltage Rise Time Minimum Input Voltage Rise Time 20060924 20060925 www.national.com 10 LP8340 Applications Section GENERAL INFORMATION The LP8340 is a low-dropout, low quiescent current linear regulator. As shown in Figure 1 it consists of a 1.25V reference, error amplifier, MOSFET driver, PMOS pass transistor and for the fixed output versions, an internal feedback network (R1/R2). In addition, the device is protected from overload by a thermal shutdown circuit and a foldback current limit circuit The 1.25V reference is connected to the inverting input of the error amplifier. Regulation of the output voltage is achieved by means of negative feedback to the noninverting input of the error amplifier. Feedback resistors R1 and R2 are either internal or external to the device, depending on whether it is a fixed voltage version or the adjustable version. The negative feedback and high open loop gain of the error amplifier cause the two inputs of the error amp to be virtually equal in voltage. If the output voltage changes due to load changes, the error amplifier and MOSFET driver provide the appropriate drive to the pass transistor to maintain the error amplifier’s inputs as virtually equal. 20060903 FIGURE 1. LP8340 Functional Block Diagram EXTERNAL CAPACITOR An Input capacitor of 1µF or greater is required between the LP8340 VIN pin and ground. While 1µF will provide adequate bypassing of the VIN supply larger values of input capacitor (i.e. 10µF) can provide improved bypassing of power supply noise. Stable operation can be achieved with an output capacitor of 1µF or greater, either ceramic X7R dielectric or aluminum/ tantalum electrolytic. While the minimum capacitor value is 1µF, the typical output capacitor values selected range from 1µF to 10µF. The larger values provide improved loadtransient response, power supply rejection and stability. OUTPUT VOLTAGE SETTING (ADJ VERSION ONLY) The output voltage is set according to the amount of negative feedback (Note that the pass transistor inverts the feedback signal). This feedback is determined by R1 and R2 with the resulting output voltage represented by the following equation: Use the following equation to determine the values of R1 and R2 for a desired VOUT (R2 = 100Ω is recommended). MINIMUM LOAD CURRENT A minimum load of 100µA is required for regulation and stability over the entire operating temperature range. If actual load current fall below 100µA it is recommended that a resistor of value RL = VO/100µA be placed between VO and ground. 11 www.national.com LP8340 Applications Section START UP CONSIDERATIONS (Continued) Under certain operating conditions, overshoot of VOUT at start-up can occur. The observed overshoot is a function of rise time of VIN waveform, COUT, start-up load current, and VIN−VOUT differential. The relationship between these conditions is shown in the Typical Performance Characteristics curves (Minimum Input Voltage Rise Time). VIN rise times above the curve result in < 5% overshoot. Customers are encouraged to check the suitability of LP8340 in their specific application. www.national.com 12 LP8340 Physical Dimensions inches (millimeters) unless otherwise noted 6-Pin LLP NS Package Number LDE06A 3-Pin DPAK NS Package Number TD03B 13 www.national.com LP8340 Low Dropout, Low IQ, 1.0A CMOS Linear Regulator Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: new.feedback@nsc.com Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: ap.support@nsc.com National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: jpn.feedback@nsc.com Tel: 81-3-5639-7560 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.