MM54C165

MM54C165 MM74C165 Parallel-Load 8-Bit Shift Register December 1992 MM54C165 MM74C165 Parallel-Load 8-Bit Shift Register General Description The MM54C165 MM74C165 functions as an 8-bit parallelload serial shift register Data is loaded into the register independent of the state of the clock(s) when PARALLEL LOAD (PL) is low Shifting is inhibited as long as PL is low Data is sequentially shifted from complementary outputs Q7 and Q7 highest-order bit (P7) first New serial data may be entered via the SERIAL DATA (Ds) input Serial shifting occurs on the rising edge of CLOCK1 or CLOCK2 Clock inputs may be used separately or together for combined clocking from independent sources Either clock input may be used also as an active-low clock enable To prevent double-clocking when a clock input is used as an enable the enable must be changed to a high level (disabled) only while the clock is high Features Y Y Y Y Wide supply voltage range Guaranteed noise margin High noise immunity Low power TTL compatibility Parallel loading independent of clock Dual clock inputs Fully static operation 3V to 15V 1V 0 45 VCC (typ ) fan out of 2 driving 74L Y Y Y Connection and Block Diagrams Dual-In-Line Package TL F 5897 – 2 Order Number MM54C165 or MM74C165 Please look into Section 8 Appendix D for availability of various package types TL F 5897 – 1 Top View TL F 5897 – 3 C1995 National Semiconductor Corporation TL F 5897 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin Operating Temperature Range MM54C165 MM74C165 b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a 85 C Storage Temperature Range Absolute Maximum VCC Power Dissipation Dual-In-Line Small Outline Operating VCC Range Lead Temperature (Soldering 10 sec ) b 65 C to a 150 C 18V 700 mW 500 mW 3V to 15V 260 C DC Electrical Characteristics Min Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Supply Current Parameter Max limits apply across temperature range unless otherwise noted Conditions Min Typ Max Units VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V IO e b10 mA VCC e 10V IO e b10 mA VCC e 5V IO e a 10 mA VCC e 10V IO e a 10 mA VCC e 15V VIN e 15V VCC e 15V VIN e 0V VCC e 15V 35 80 15 20 45 90 05 10 0 005 b1 0 b 0 005 V V V V V V V V mA mA 300 mA 10 0 05 CMOS TO LPTTL INTERFACE VIN(1) VIN(0) VOUT(1) VOUT(0) Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V IO e b360 mA 74C VCC e 4 75V IO e b360 mA 54C VCC e 4 5V IO e 360 mA 74C VCC e 4 75V IO e 360 mA 24 24 04 04 VCC b 1 5 VCC b 1 5 08 08 V V V V V V V V OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (short circuit current) ISOURCE ISOURCE ISINK ISINK Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC e 5V TA e 25 C VOUT e 0V VCC e 10V TA e 25 C VOUT e 0V VCC e 5V TA e 25 C VOUT e VCC VCC e 10V TA e 25 C VOUT e VCC b 1 75 b8 0 b3 3 b 15 mA mA mA mA 1 75 80 36 16 Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation 2 AC Electrical Characteristics Symbol tpd0 tpd1 tpd0 tpd1 tS tS tH tS tH tW tW fMAX tr tf CIN CPD Parameter TA e 25 C CL e 50 pF unless otherwise noted Conditions VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V (Note 2) (Note 3) 25 5 10 5 5 65 150 60 50 30 50 30 150 60 50 30 Min Typ 200 80 200 80 75 30 25 15 0 0 75 30 0 0 70 30 85 30 6 12 200 100 180 90 Max 400 200 400 200 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ms ms pF pF Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock or Load to Q or Q Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from H to Q or Q Clock Inhibit Set-up Time Serial Input Set-up Time Serial Input Hold Time Parallel Input Set-Up Time Parallel Input Hold Time Minimum Clock Pulse Width Minimum Load Pulse Width Maximum Clock Frequency Maximum Clock Rise and Fall Time Input Capacitance Power Dissipation Capacitance AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note AN-90 Switching Time Waveform TL F 5897 – 4 Note A The remaining six data and the serial input are low Note B Prior to test high level data is loaded into the P7 input 3 Truth Table Inputs State PL Parallel Load Enable Shift (with Ds) Shift (with Ds) Hold (Disable) X e don’t care H e VIN(1) L e VIN(0) e clock transition from VIN(0) to VIN(1) P0 thru P7 e data present (and loaded into) parallel inputs Q0 thru Q6 e Internal flip-flop outputs Internal Ds X X H L X P0 thru P7 P0 X X X X P7 Q0 P0 P0 H L L Q1 P1 P1 P0 H H Outputs Q7 P7 P7 P6 P5 P5 Q7 P7 P7 P6 P5 P5 Clock1 X L Clock2 (as enable) X L L L H L H H H H u u u u Logic Waveform TL F 5897 – 5 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C165J or MM74C165J NS Package Number J16A 5 MM54C165 MM74C165 Parallel-Load 8-Bit Shift Register Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C165N or MM74C165N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 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