MM58167

MM58167B Microprocessor Real Time Clock October 1990 MM58167B Microprocessor Real Time Clock General Description The MM58167B is a low threshold metal gate CMOS circuit that functions as a real time clock in bus oriented microprocessor systems The device includes an addressable real time counter 56 bits of RAM and two interrupt outputs A POWER DOWN input allows the chip to be disabled from the rest of the system for standby low power operation The time base is a 32 768 kHz crystal oscillator Y Y Y Y Y Y Features Y Y Y 56 bits of RAM with comparator to compare the real time counter to the RAM data 2 INTERRUPT OUTPUTS with 8 possible interrupt signals POWER DOWN input that disables all inputs and outputs except for one of the interrupts Status bit to indicate rollover during a read 32 768 kHz crystal oscillator Four-year calendar (no leap year) 24-hour clock Microprocessor compatible (8-bit data bus) Milliseconds through month counters Connection Diagrams Dual-In-Line Package PCC Package TL F 11070 – 1 Top View Order Number MM58167BN See NS Package Number N24A TL F 11070 – 2 Top View Order Number MM58167BV See NS Package Number V28A TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 11070 RRD-B30M105 Printed in U S A Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at All Pins Operating Temperature VSS b 0 3V to VDD a 0 3V 0 C to 70 C Storage Temperature VDDbVSS Lead Temperature (Soldering 10 sec ) b 65 C to a 150 C 6 0V 300 C Electrical Characteristics VSS e 0V Parameter Supply Voltage VDD VDD Supply Current IDD Dynamic 0 C s TA s 70 C Min 45 22 Max 55 55 Units V V Conditions Outputs Enabled POWER DOWN Mode Outputs TRI-STATE fIN e 32 768 kHz VDD e 5 5V VIH t VDD b 0 3V VIL s VSS a 0 3V Outputs TRI-STATE fIN e 32 768 kHz VDD e 5 5V VIH e 2 0V VIL e 0 8V 20 mA IDD Dynamic 5 mA Input Voltage Logical Low Logical high Input Leakage Current Output Impedance Logical Low Logical High TRI-STATE Output Impedance Logical Low Sink Logical High Leakage VSS s VIN s VDD I O and INTERRUPT OUT VDD e 4 5V IOL e 1 6 mA VDD e 4 5V IOH e b400 mA IOH e b10 mA VSS s VOUT s VDD RDY and STANDBY INTERRUPT (Open Drain Devices) VDD e 4 5V IOL e 1 6 mA VOUT s VDD 00 20 b1 08 VDD 1 04 V V mA V V V mA 24 0 8 VDD b1 1 04 10 V mA 2 Functional Description Real Time Counter The real time counter is divided into 4-bit digits with 2 digits being accessed during any read or write cycle Each digit represents a BCD number and is defined in Table I Any unused bits are held at a logical zero during a read and ignored during a write An unused bit is any bit not necessary to provide a full BCD number For example tens of hours cannot legally exceed the number 2 thus only 2 bits are necessary to define the tens of hours The other 2 bits in the tens of hours digit are unused The unused bits are designated in Table I as dashes The addressable portion of the counter is from milliseconds to months The counter itself is a ripple counter The ripple delay is less than 60 ms above 4 5V and 300 ms at 2 2V RAM 56 bits of RAM are contained on-chip These can be used for any necessary power down storage or as an alarm latch for comparison to the real time counter The data in the RAM can be compared to the real time counter on a digit basis The only digits that are not compared are the unit ten thousandths of seconds and tens of days of the week (these are unused in the real time counter) If the two most significant bits of any RAM digit are ones then this RAM location will always compare The rule of thumb for an ‘‘alarm’’ interrupt is All nibbles of higher order than specified are set to C hex (always compare) All nibbles lower than specified are set to ‘‘zero’’ As an example if an alarm is to occur everyday at 10 15 a m configure the bits in RAM as shown in Table II The RAM is formatted the same as the real time counter 4 bits per digit 14 digits however there are no unused bits The unused bits in the real time counter will compare only to zeros in the RAM An address map is shown in Table III Interrupts and Comparator There are two interrupt outputs The first is the INTERRUPT OUTPUT (a true high signal) This output can be programmed to provide 8 different output signals They are 10 Hz once per second once per minute once per hour once a day once a week once a month and when a RAM real time counter comparison occurs To enable the output a one is written into the interrupt control register at the bit location corresponding to the desired output frequency (Figure 1 ) Once one or more bits have been set in the interrupt control register the corresponding counter’s rollover to its reset state will clock the interrupt status register and cause the interrupt output to go high To reset the interrupt and to identify which frequency caused the interrupt the interrupt status register is read Reading this register places the contents of the status register on the data bus The interrupting frequency will be identified by a one in the respective bit position Removing the read will reset the interrupt The second interrupt is the STANDBY INTERRUPT (open drain output active low) This interrupt occurs when enabled and when a RAM real time counter comparison occurs The STANDBY INTERRUPT is enabled by writing a one on the D0 line at address 16H or disabled by writing a zero on the D0 line This interrupt is not triggered by the edge of the compare signal but rather by the level Thus if the compare is enabled when the STANDBY INTERRUPT is enabled the interrupt will turn on immediately TABLE I Real Time Counter Format Counter Addressed Milliseconds Hundredths and Tenths Sec Seconds Minutes Hours Day of the Week Day of the Month Month ( ) indicates unused bits D0 (00H) (01H) (02H) (03H) (04H) (05H) (06H) (07H) Units D1 D2 D3 Max BCD Code 0 9 9 9 9 7 9 9 Tens D4 D4 D4 D4 D4 D4 D4 D4 D5 D5 D5 D5 D5 D5 D5 D6 D6 D6 D6 D6 D7 D7 D7 Max BCD Code 9 9 5 5 2 0 3 1 D0 D0 D0 D0 D0 D0 D0 D1 D1 D1 D1 D1 D1 D1 D2 D2 D2 D2 D2 D2 D2 D3 D3 D3 D3 D3 D3 3 Functional Description (Continued) TABLE II Clock RAM Bit Map for Alarm Interrupt Everyday at 10 15 a m Address Function 4 Milliseconds Hundredths and Tenths of Seconds Seconds Minutes Hours Day of Week Day of Month Months 0 0 0 0 0 0 0 0 3 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1 7 0 0 0 0 0 Hi Nibble 6 0 0 0 0 0 5 0 0 0 0 0 4 0 0 0 1 1 0 0 0 0 1 X X 1 1 3 Data Lo Nibble 2 1 0 No RAM Exists 0 0 1 0 1 1 1 0 0 0 0 X X X 0 0 1 0 X X X No RAM Exists 1 1 X X TABLE III Address Codes and Function A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 All others unused A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Counter Milliseconds Counter Hundredths and Tenths of Seconds Counter Seconds Counter Minutes Counter Hours Counter Day of Week Counter Day of Month Counter Month RAM Milliseconds RAM Hundredths and Tenths of Seconds RAM Seconds RAM Minutes RAM Hours RAM Day of Week RAM Day of Month RAM Months Interrupt Status Register Interrupt Control Register Counters Reset RAM Reset Status Bit GO Comand STANDBY INTERRUPT Test Mode The comparator is a cascaded exclusive NOR Its output is latched 61 ms after the rising edge of the 1 kHz clock signal (input to the milliseconds counter) This allows the counter to ripple through before looking at the comparator For operation at less than 4 5V the thousandths of seconds counter should not be included in a compare because of the possibility of having a ripple delay greater than 61 ms (For output timing see Interrupt Timing ) Power Down Mode The POWER DOWN input is essentially a second chip select It disables all inputs and outputs except for the STANDBY INTERRUPT When this input is at a logical zero the device will not respond to any external signals It will however maintain timekeeping and turn on the STANDBY INTERRUPT if programmed to do so (The programming must be done before the POWER DOWN input goes to a 4 Functional Description (Continued) logical zero ) When switching VDD to the standby or power down mode the POWER DOWN input should go to a logical zero at least 1 ms before VDD is switched When switching VDD all other inputs must remain between VSS b 0 3V and VDD a 0 3V When restoring VDD to the normal operating mode it is necessary to insure that all other inputs are at valid levels before switching the POWER DOWN input back to a logical one These precautions are necessary to insure that no data is lost or altered when changing to or from the power down mode Counter and RAM Resets GO Command The counters and RAM can be reset by writing all 1’s (FF) at address 12H or 13H respectively A write pulse at address 15H will reset the thousandths hundredths tenths units and tens of seconds counters This GO command is used for precise starting of the clock The data on the data bus is ignored during the write If the seconds counter is at a value greater than 39 when the GO is issued the minute counter will increment otherwise the minute counter is unaffected This command is not necessary to start the clock but merely a convenient way to start precisely at a given minute Status Bit The status bit is provided to inform the user that the clock is in the process of rolling over when a counter is read The status bit is set if this 1 kHz clock occurs during or after any counter read This tells the user that the clock is rippling through the real time counter Because the clock is rippling invalid data may be read from the counter If the status bit is set following a counter read the counter should be reread The status bit appears on D0 when address 14H is read All the other data lines will zero The bit is set when a logical one appears This bit should be read every time a counter read or after a series of counter reads are done The trailing edge of the read at address 14H will reset the status bit Using the Rollover Status Bit If a single read of any clock counter is made it should be followed by reading the rollover status bit Example Read months then read rollover status If a sequential read of the clock counters is made then the rollover status bit should be read after the last counter is read Example Read hours minutes seconds then read the rollover status Oscillator The oscillator used is the standard Pierce parallel resonant oscillator Externally 2 capacitors a 20 MX resistor and the crystal are required The 20 MX resistor is connected between OSC IN and OSC OUT to bias the internal inverter in the linear region For micropower crystals a resistor in series with the oscillator output may be necessary to insure the crystal is not overdriven This resistor should be approximately 200 kX The capacitor values should be typically 20 pF – 25 pF The crystal frequency is 32 768 Hz The oscillator input can be externally driven if desired In this case the oscillator output should be left floating and the oscillator input levels should be within 0 3V of the supplies A ground line or ground plane between pins 9 and 10 may be necessary to reduce interference of the oscillator by the A4 address Control Lines The READ WRITE AND CHIP SELECT signals are active low inputs The READY signal is an open drain output At the start of each read or write cycle the READY line (open drain) will pull low and will remain low until valid data from a chip read appears on the bus or data on the bus is latched in during a write READ and WRITE must be accompanied by a CHIP SELECT (see Figures 3 and 4 for read and write cycle timing) During a read or write address bits must not change while chip select and control strobes are low Test Mode The test mode is for production testing It allows the counters to count at a higher than normal rate In this mode the 32 768 kHz oscillator input is connected directly to the ten thousandths of seconds counter The chip select and write lines must be low and the address must be held at 1FH TL F 11070 – 3 FIGURE 1 Interrupt Register Format 5 Functional Description (Continued) Standby Interrupt Typical Characteristics Typical Supply Current vs Supply Voltage during Power Down TL F 11070–4 TL F 11070 – 5 FIGURE 2 Interrupt Timing 0 C s TA s 70 C Symbol tINTON tSBYON tINTOFF tSBYOFF 4 5V s VDD s 5 5V VSS e 0V Min Max 5 5 5 Units ms ms ms Parameter Status Register Clock to INTERRUPT OUTPUT (Pin 13) High (Note 1) Compare Valid to STANDBY INTERRUPT (Pin 14) Low (Note 1) Trailing Edge of Status Register Read to INTERRUPT OUTPUT Low Trailing Edge of Write Cycle (D0 e 0 Address e 16H) to STANDBY INTERRUPT Off (High Impedance State) 5 ms Note 1 The status register clocks are the corresponding counter’s rollover to its reset state or the compare becoming valid The compare becomes valid 61 ms after the 1 10 000 of a second counter is clocked if the real time counter data matches the RAM data Read Cycle Timing 0 C s TA s 70 C Symbol tAR tCSR tRRY tRYD tAD tRH tHZ tRYH tRA tRYDV 4 5V s VDD s 5 5V VSS e 0V Min 100 0 150 800 1050 0 250 0 50 100 Max Units ns ns ns ns ns ns ns ns ns ns Parameter Address Bus Valid to Read Strobe (Note 3) Chip Select to Read Strobe (Note 2) Read Strobe to Ready Strobe Ready Strobe to Data Valid Address Bus Valid to Data Valid Data Hold Time from Trailing Edge of Read Strobe Trailing Edge of Read Strobe to TRI-STATE Mode Read Hold Time after Ready Strobe Address Bus Hold Time from Trailing Edge of Read Strobe Rising Edge of Ready to Data Valid Note 2 When reading a deselect time of 500 ns minimum must occur between counter reads Deselect is CS e 1 or (WR)  (RD) e 1 Note 3 If tAR e 0 and Chip Select Address Valid or Read are coincident then they must exist for 1050 ns 6 Write Cycle Timing 0 C s TA s 70 C Symbol tAW tCSW tDW tWRY tRY tRYH tWD tWA 4 5V s VDD s 5 5V VSS e 0V Min 100 0 100 150 800 0 110 50 Max Units ns ns ns ns ns ns ns ns Parameter Address Valid to Write Strobe Chip Select to Write Strobe Data Valid before Write Strobe Write Strobe to Ready Strobe Ready Strobe Width Write Hold Time after Ready Strobe Data Hold Time after Write Strobe Address Hold Time after Write Strobe Note 4 If data changes while CS and WR are low then they must remain coincident for 1050 ns after the data change to ensure a valid write Data bus loading is 100 pF Ready output loading is 50 pF and 3 kX pull-up Input and output AC timing levels Logical one e 2 0V Logical zero e 0 8V Read and Write Cycle Timing Diagrams TL F 11070 – 6 FIGURE 3 Read Cycle Timing TL F 11070 – 7 FIGURE 4 Write Cycle Timing 7 Typical Applications R1 e 20 MX g 20% C1 e 6 pF b 36 pF R2 to be selected based on crystal used TL F 11070 – 8 Note 5 A ground line or ground plane guard trace should be included between pins 9 and 10 to insure the oscillator is not disturbed by the address line FIGURE 5 Typical Connection Diagram TL F 11070 – 9 Note 6 Must use 8238 or equivalent logic to insure advanced I OW pulse so that the ready output of the MM58167B is valid by the end of w2 during the T2 microcycle Note 7 tw2 t tRS8080 a tDL8238 a tWRY58167B FIGURE 6 8080 System Interface with Battery Backup 8 Block Diagram TL F 11070 – 10 FIGURE 7 Physical Dimensions inches (millimeters) Molded Dual-In-Line Package (N) Order Number MM58167BN NS Package Number N24A 9 MM58167B Microprocessor Real Time Clock Physical Dimensions inches (millimeters) (Continued) PCC Package (V) Order Number MM58167BV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into 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Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications