MM74C08

MM54C08 MM74C08 Quad 2-Input AND Gate February 1988 MM54C08 MM74C08 Quad 2-Input AND Gate General Description Employing complementary MOS (CMOS) transistors to achieve wide power supply operating range low power consumption and high noise margin these gates provide basic functions used in the implementation of digital integrated circuit systems The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swing essentially equal to the supply voltage No DC power other than that caused by leakage current is consumed during static condition All inputs are protected from damage due to static discharge by diode clamps to VCC and GND Features Y Y Y Y Y Wide supply voltage range Guaranteed noise margin High noise immunity Low power TTL compatibility Low power consumption 3 0V to 15V 1 0V 0 45 VCC (typ ) Fan out of 2 driving 74L 10 nW package (typ ) Connection Diagram and Truth Table Dual-In-Line Package TL F 5878 – 1 Top View Order Number MM54C08 or MM74C08 Inputs A L L H H H e High Level Outputs B L H L H L e Low Level Y L L L H C1995 National Semiconductor Corporation TL F 5878 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Lead Temperature (Soldering 10 seconds) b 65 C to a 150 C If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin Operating Temperature Range MM54C08 MM74C08 b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a 85 C 700 mW 500 mW 3 0V to 15V 18V 260 C DC Electrical Characteristics Min Max limits apply across the guaranteed temperature range unless otherwise noted Symbol CMOS TO CMOS VIN(1) Logical ‘‘1’’ Input Voltage VCC e 5 0V VCC e 10V VIN(0) Logical ‘‘0’’ Input Voltage VCC e 5 0V VCC e 10V VOUT(1) Logical ‘‘1’’ Output Voltage VCC e 5 0V IO e b10 mA VCC e 10V IO e b10 mA VOUT(0) Logical ‘‘0’’ Output Voltage VCC e 5 0V IO e 10 mA VCC e 10V IO e 10 mA IIN(1) IIN(0) ICC Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Supply Current VCC e 15V VIN e 15V VCC e 15V VIN e 0V VCC e 15V b1 0 Parameter Conditions Min Typ Max Units 35 80 15 20 45 90 05 10 0 005 b 0 005 V V V V V V V V mA mA 15 mA 10 0 01 CMOS LPTTL INTERFACE VIN(1) Logical ‘‘1’’ Input Voltage 54C VCC e 4 5V 74C VCC e 4 75V VIN(0) Logical ‘‘0’’ Input Voltage 54C VCC e 4 5V 74C VCC e 4 75V VOUT(1) Logical ‘‘1’’ Output Voltage 54C VCC e 4 5V IO e b360 mA 74C VCC e 4 75V IO e b360 mA VOUT(0) Logical ‘‘0’’ Output Voltage 54C VCC e 4 5V IO e 360 mA 74C VCC e 4 75V IO e 360 mA OUTPUT DRIVE (see 54C 74C Family Characteristics Data Sheet) TA e 25 C (short circuit current) ISOURCE ISOURCE ISINK ISINK Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC e 5 0V VOUT e 0V VCC e 10V VOUT e 0V VCC e 5 0V VOUT e VCC VCC e 10V VOUT e VCC b 1 75 b8 0 b3 3 VCC b 1 5 VCC b 1 5 08 08 24 24 04 04 V V V V V V V V mA mA mA mA 15 36 16 1 75 80 Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation 2 AC Electrical Characteristics (MM54C08 MM74C08) TA e 25 C CL e 50 pF unless otherwise specified Symbol tpd0 tpd1 Parameter Propagation Delay Time to Logical ‘‘1’’ or ‘‘0’’ Input Capacitance Power Dissipation Capacitance Conditions VCC e 5 0V VCC e 10V (Note 2) (Note 3) Per Gate Min Typ 80 40 50 14 Max 140 70 Units ns ns pF pF CIN CPD AC Parameters are guaranteed by DC correlated testing Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90 Typical Performance Characteristics Propagation Delay Time vs Load Capacitance MM54C08 MM74C08 TL F 5878 – 2 AC Test Circuit TL F 5878 – 3 Note Delays measured with input tr tf e 20 ns Switching Time Waveforms TL F 5878 – 4 3 MM54C08 MM74C08 Quad 2-Input AND Gate Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C08J or MM74C08J NS Package Number J14A Molded Dual-In-Line Package (N) Order Number MM54C08N or MM74C08N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use 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