MM74C175

MM54C175 MM74C175 Quad D Flip-Flop February 1988 MM54C175 MM74C175 Quad D Flip-Flop General Description The MM54C175 MM74C175 consists of four positive-edge triggered D type flip-flops implemented with monolithic CMOS technology Both are true and complemented outputs from each flip-flop are externally available All four flipflops are controlled by a common clock and a common clear Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positivegoing edge of the clock pulse The clearing operation enabled by a negative pulse at Clear input clears all four Q outputs to logical ‘‘0’’ and Q’s to logical ‘‘1’’ All inputs are protected from static discharge by diode clamps to VCC and GND Features Y Y Y Y Wide supply voltage range Guaranteed noise margin High noise immunity Low power TTL compatibility 3V to 15V 1 0V 0 45 VCC (typ ) Fan out of 2 driving 74L Connection Diagram Truth Table Dual-In-Line Package TL F 5900 – 1 Top View Order Number MM54C175 or MM74C175 Each Flip-Flop Inputs Clear L H H H H Clock X D X H L X X Q L H L NC NC Outputs Q H L H NC NC u u H L H e High level L e Low level X e Irrelevant e Transition from low to high level NC e No change u C1995 National Semiconductor Corporation TL F 5900 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin Operating Temperature Range MM54C175 MM74C175 b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a 85 C Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Lead Temperature (Soldering 10 seconds) b 65 C to a 150 C 700 mW 500 mW 3V to 15V 18V 260 C DC Electrical Characteristics Min Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IIN(1) IIN(0) ICC Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Supply Current Parameter Max limits apply across temperature range unless otherwise specified Conditions Min Typ Max Units VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V IO e b10 mA VCC e 10V IO e b10 mA VCC e 5V IO e 10 mA VCC e 10V IO e 10 mA VCC e 15V VIN e 15V VCC e 15V VIN e 0V VCC e 15V 35 80 15 20 45 90 05 10 0 005 b1 0 b 0 005 V V V V V V V V mA mA 300 mA 10 0 05 CMOS LPTTL INTERFACE VIN(1) VIN(0) VOUT(1) VOUT(0) Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V IO e b360 mA 74C VCC e 4 75V IO e b360 mA 54C VCC e 4 5V IO e 360 mA 74C VCC e 4 75V IO e 360 mA 24 24 04 04 VCC b 1 5 VCC b 1 5 08 08 V V V V V V V V OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE ISOURCE ISINK ISINK Output Source Current (P-Channel) Output Source Current (P-Channel) Output Sink Current (N-Channel) Output Sink Current (N-Channel) VCC e 5V TA e 25 C VOUT e 0V VCC e 10V TA e 25 C VOUT e 0V VCC e 5V TA e 25 C VOUT e VCC VCC e 10V TA e 25 C VOUT e VCC b 1 75 b3 3 mA mA mA mA b8 0 b 15 1 75 80 36 16 Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation 2 AC Electrical Characteristics Symbol tpd Parameter Propagation Delay Time to a Logical ‘‘0’’ or Logical ‘‘1’’ from Clock to Q or Q Propagation Delay Time to a Logical ‘‘0’’ from Clear to Q Propagation Delay Time to a Logical ‘‘1’’ from Clear to Q Time Prior to Clock Pulse that Data Must be Present Time After Clock Pulse that Data Must be Held Minimum Clock Pulse Width Minimum Clear Pulse Width Maximum Clock Rise Time Maximum Clock Fall Time Maximum Clock Frequency Input Capacitance Power Dissipation Capacitance TA e 25 C CL e 50 pF unless otherwise noted Conditions VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5 0V VCC e 10V VCC e 5 0V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V VCC e 10V Clear Input (Note 2) Any Other Input Per Package (Note 3) 15 50 15 50 20 50 100 40 0 0 Min Typ 190 75 180 70 230 90 45 16 b 11 b4 Max 300 110 300 110 400 150 Units ns ns ns ns ns ns ns ns ns ns tpd tpd tS tH tW tW tr tf fMAX CIN CPD 130 45 120 45 450 125 50 50 35 10 10 50 130 250 100 250 100 ns ns ns ns ms ms ms ms MHz MHz pF pF pF AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90 Switching Time Waveforms CMOS to CMOS TL F 5900 – 6 3 Logic Diagram Typical One of Four TL F 5900 – 4 TL F 5900 – 5 TL F 5900 – 2 TL F 5900–3 4 Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C175J or MM74C175J NS Package Number J16A 5 MM54C175 MM74C175 Quad D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM54C175N or MM74C175N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications