MM74C240

MM54C240 MM74C240 Inverting MM54C244 MM74C244 Non-Inverting Octal Buffers and Line Drivers with TRI-STATE Outputs February 1988 MM54C240 MM74C240 Inverting MM54C244 MM74C244 Non-Inverting Octal Buffers and Line Drivers with TRI-STATE Outputs General Description These octal buffers and line drivers are monolithic complementary MOS (CMOS) integrated circuits with TRI-STATE outputs These outputs have been specially designed to drive highly capacitive loads such as bus-oriented systems These devices have a fan out of 6 low power Schottky loads A high logic level on the output disable control input G makes the outputs go into the high impedance state For improved TTL input compatibility see MM74C941 Features Y Y Y Y Y Y Y Y Y Wide supply voltage range (3V to 15V) High noise immunity (0 45 VCC typ) Low power consumption High capacitive load drive capability TRI-STATE outputs Input protection TTL compatibility 20-pin dual-in-line package High speed 25 ns (typ ) 10V 50 pF (MM74C244) Logic and Connection Diagrams MM54C240 MM74C240 MM54C240 MM74C240 Dual-In-Line Package TL F 5905 – 2 TL F 5905 – 1 Top View Order Number MM54C240 or MM74C240 MM54C244 MM74C244 MM54C244 MM74C244 Dual-In-Line Package TL F 5905 – 4 TL F 5905 – 3 Top View Order Number MM54C244 or MM74C244 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 5905 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin Operating Temperature Range MM54C240 MM54C244 MM74C240 MM74C244 b 0 3V to VCC a 0 3V b 55 C to a 125 C b 40 C to a 85 C Storage Temperature Range Power Dissipation Dual-In-Line Small Outline Operating VCC Range b 65 C to a 150 C 700 mW 500 mW 3V to 15V 18V 260 C Absolute Maximum VCC Lead Temperature (Soldering 10 seconds) DC Electrical Characteristics Min Symbol CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IOZ IIN(1) IIN(0) ICC Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage Logical ‘‘0’’ Output Voltage TRI-STATE Output Current Logical ‘‘1’’ Input Current Logical ‘‘0’’ Input Current Supply Current Parameter Max limits apply across temperature range unless otherwise noted Conditions Min Typ Max Units VCC e 5V VCC e 10V VCC e 5V VCC e 10V VCC e 5V IO e b10 mA VCC e 10V IO e b10 mA VCC e 5V IO e 10 mA VCC e 10V IO e 10 mA VCC e 10V OD e VIH VCC e 15V VIN e 15V VCC e 15V VIN e 0V VCC e 15V 35 80 15 20 45 90 05 10 g 10 V V V V V V V V mA mA mA 300 mA 0 005 b1 0 b 0 005 10 0 05 CMOS LPTTL INTERFACE VIN(1) VIN(0) VOUT(1) Logical ‘‘1’’ Input Voltage Logical ‘‘0’’ Input Voltage Logical ‘‘1’’ Output Voltage 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V 74C VCC e 4 75V 54C VCC e 4 5V IO e b450 mA 74C VCC e 4 75V IO e b450 mA 54C VCC e 4 5V IO e b2 2 mA 74C VCC e 4 75V IO e b2 2 mA VOUT(0) Logical ‘‘0’’ Output Voltage 54C VCC e 4 5V IO e 2 2 mA 74C VCC e 4 75V IO e 2 2 mA VCC b 0 4 VCC b 0 4 24 24 04 04 VCC b 1 5 VCC b 1 5 08 08 V V V V V V V V V V OUTPUT DRIVE (See 54C 74C Family Characteristics Data Sheet) (Short Circuit Current) ISOURCE Output Source Current (P-Channel) VCC e 5V VOUT e 0V TA e 25 C VCC e 10V VOUT e 0V TA e 25 C ISINK Output Sink Current (N-Channel) VCC e 5V VOUT e VCC TA e 25 C VCC e 10V VOUT e VCC TA e 25 C b 14 b 36 b 30 b 70 mA mA mA mA 12 48 20 70 Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation 2 AC Electrical Characteristics Symbol tPD(1) tPD(0) Parameter Propagation Delay (Data In to Out) MM54C240 MM74C240 TA e 25 C CL e 50 pF unless otherwise specified Conditions Min Typ Max Units VCC VCC VCC VCC VCC VCC VCC VCC e e e e e e e e 5V CL e 50 pF 10V CL e 50 pF 5V CL e 150 pF 10V CL e 150 pF 5V CL e 50 pF 10V CL e 50 pF 5V CL e 150 pF 10V CL e 150 pF 60 40 80 60 45 25 60 40 45 35 50 30 45 30 75 50 90 70 110 90 70 50 90 70 80 60 90 60 80 60 140 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MM54C244 MM74C244 t1H t0H Propagation Delay Output Disable to High Impedance State (from a Logic Level) Propagation Delay Output Disable to Logic Level (from High Impedance State) Transition Time RL e 1k CL e 50 pF VCC e 5V VCC e 10V RL e 1k CL e 50 pF VCC e 5V VCC e 10V VCC VCC VCC VCC e e e e tH1 tH0 tT(HL) tT(LH) 5V CL e 50 pF 10V CL e 50 pF 5V CL e 150 pF 10V CL e 150 pF CPD Power Dissipation Capacitance (Output Enabled per Buffer) MM54C240 MM74C240 MM54C244 MM74C244 (Output Disabled per Buffer) MM54C240 MM74C240 MM54C244 MM74C244 (Note 3) 100 100 10 0 VIN e 0V f e 1 MHz TA e 25 C VIN e 0V f e 1 MHz TA e 25 C 10 10 pF pF pF pF pF pF CIN CO Input Capacitance (Any Input) Output Capacitance (Output Disabled) AC Parameters are guaranteed by DC correlated testing Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed Except for ‘‘Operating Range’’ they are not meant to imply that the devices should be operated at these limits The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 CPD determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics Application Note AN-90 Typical Application TL F 5905 – 5 3 Truth Tables MM54C240 MM74C240 ODA 1 1 0 0 IA X X 0 1 OA Z Z 1 0 MM54C244 MM74C244 ODA 1 1 0 0 1 0 e High e Low ODB 1 1 0 0 IB X X 0 1 OB Z Z 1 0 IA X X 0 1 OA Z Z 0 1 ODB 1 1 0 0 IB X X 0 1 OB Z Z 0 1 X e Don’t Care Z e TRI-STATE Typical Performance Characteristics N-Channel Output Drive at 25 C P-Channel Output Drive at 25 C TL F 5905 – 6 TL F 5905 – 7 MM54C240 MM74C240 Propagation Delay vs Load Capacitance MM54C244 MM74C244 Propagation Delay vs Load Capacitance TL F 5905 – 8 TL F 5905 – 9 4 AC Test Circuits and Switching Time Waveforms tpd0 tpd1 CMOS to CMOS TL F 5905–10 TL F 5905 – 11 t1H and tH1 t1H tH1 TL F 5905–12 TL F 5905 – 13 Note VOH is defined as the DC output high voltage when the device is loaded with a 1 kX resistor to ground t0H and tH0 t0H tH0 TL F 5905–14 TL F 5905 – 15 Note VOL is defined as the DC output low voltage when the device is loaded with a 1 kX resistor to VCC Note Delays measured with input tr tf s 20 ns 5 MM54C240 MM74C240 Inverting MM54C244 MM74C244 Non-Inverting Octal Buffers and Line Drivers with TRI-STATE Outputs Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54C240J MM54C244J MM74C240J or MM74C244J See NS Package Number J20A Molded Dual-In-Line Package (N) Order Number MM54C240N MM54C244N MM74C240N or MM74C244N See NS Package Number N20A LIFE SUPPORT POLICY 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