MM74HC03J

MM54HC03 MM74HC03 Quad 2-Input Open Drain NAND Gate January 1988 MM54HC03 MM74HC03 Quad 2-Input Open Drain NAND Gate General Description These NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits All gates have buffered outputs All devices have high noise immunity and the ability to drive 10 LS-TTL loads The 54HC 74HC logic family is functionally as well as pin-out compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground As with standard 54HC 74HC push-pull outputs there are diodes to both VCC and ground Therefore the output should not be pulled above VCC as it would be clamped to one diode voltage above VCC This diode is added to enhance electrostatic protection Features Y Y Y Y Y Typical propagation delay 12 ns Wide power supply range 2 – 6V Low quiescent current 20 mA maximum (74HC Series) Low input current 1 mA maximum Fanout of 10 LS-TTL loads Connection and Logic Diagrams Dual-In-Line Package TL F 5295 – 1 Top View Order Number MM54HC03 or MM74HC03 TL F 5295 – 2 C1995 National Semiconductor Corporation TL F 5295 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Min Supply Voltage VCC DC Input or Output Voltage VIN VOUT Operating Temp Range (TA) MM HC MM HC Input Rise or Fall Times tr tf VCC e V VCC e V VCC e V b b If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5 to a 7 0V Supply Voltage (VCC) b 1 5 to VCC a 1 5V DC Input Voltage (VIN) b 0 5 to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per pin (IOUT) g 50 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temp (TL) (Soldering 10 seconds) 260 C Max VCC Units V V a a C C ns ns ns DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC V V V V V V VIN e VIH lIOUTl s mA RL e % VIN e VIH lIOUTl s lIOUTl s ILKG IIN ICC Maximum High Level Output Leakage Current Maximum Input Current Maximum Quiescent Supply Current V V V V V V V V TA e 25 C Typ VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum Low Level Output Voltage 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units Guaranteed Limits V V V V V V V V V V V mA mA mA VIL VOL mA mA VIN e VIH or VIL VOUT e VCC VIN e VCC or GND VIN e VCC or GND IOUT e mA g g g Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89 2 AC Electrical Characteristics VCC e 5V Symbol tPZL tPLZ Parameter Maximum Propagation Delay Conditions RL e 1 KX TA e 25 C CL e 15 pF tr e tf e 6 ns Typ 10 Guaranteed Limit 20 Units ns AC Electrical Characteristics VCC e 2 0V to 6 0V CL e 50 pF tr e tf e 6 ns (unless otherwise specified) TA e 25 C Typ tPLZ tPZL Maximum Propagation Delay Maximum Output Fall Time Power Dissipation Capacitance Note Maximum Input Capacitance per gate RL e KX V V V V V V 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Symbol Parameter Conditions VCC Units Guaranteed Limits ns ns ns ns ns ns pF pF tTHL CPD CIN Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC The power dissipated by RL is not included 3 MM54HC03 MM74HC03 Quad 2-Input Open Drain NAND Gate Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54HC03J or MM74HC03J NS Package Number J14A Molded Dual-In-Line Package (N) Order Number MM74HC03N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in 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