MM54HC05 MM74HC05 Hex Inverter (Open Drain)
January 1988
MM54HC05 MM74HC05 Hex Inverter (Open Drain)
General Description
The MM54HC05 MM74HC05 are logic functions fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS low quiescent power and wide power supply range These devices are also functionally and pin-out compatible with standard DM54LS DM74LS logic families The MM54HC05 MM74HC05 open drain Hex Inverter requires the addition of an external resistor to perform a wire-NOR function All inputs are protected from static discharge damage by internal diodes to VCC and ground
Features
Y Y Y
Y
Open drain for wire-NOR function Fanout of 10 LS-TTL loads Typical propagation delays tPZL (with 1 kX resistor) 8 ns tPLZ (with 1 kX resistor) 13 ns Low input current 1 mA maximum
Connection Diagram
Dual-In-Line Package
TL F 9388 – 1
Top View Order Number MM54HC05 or MM74HC05
Logic Diagram
Typical Application
TL F 9388 – 2
TL F 9388 – 3
Note Can be extended to more than 2 inputs
C1995 National Semiconductor Corporation
TL F 9388
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings (Notes 1
2)
Operating Conditions
Supply Voltage (VCC) DC Input or Output Voltage (VIN VOUT) Operating Temp Range (TA) MM74HC MM54HC Input Rise or Fall Times (tr tf) VCC e 2 0V VCC e 4 5V VCC e 6 0V Min 2 0 Max 6 VCC
a 85 a 125
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications
b 0 5V to a 7 0V Supply Voltage (VCC) b 1 5V to VCC a 1 5V DC Input Voltage (VIN) b 0 5V to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per pin (IOUT) g 50 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260 C
Units V V
b 40 b 55
C C ns ns ns
1000 500 400
DC Electrical Characteristics
Symbol Parameter Conditions
(Note 4) TA e 25 C Typ 74HC 54HC TA eb40 C to a 85 C TA eb55 C to a 125 C Units Guaranteed Limits 15 3 15 42 05 1 35 18 0 0 0 02 02 01 01 01 0 26 0 26 05
g0 1
VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V
VIH
Minimum High Level Input Voltage Maximum Low Level Input Voltage Maximum Low Level Output Voltage VIN e VIH lIOUTl s20 mA RL e % VIN e VIH lIOUTl s4 0 mA lIOUTl s5 2 mA
15 3 15 42 05 1 35 18 01 01 01 0 33 0 33 5
g1 0
15 3 15 42 05 1 35 18 01 01 01 04 04 10
g1 0
V V V V V V V V V V V mA mA mA
VIL
VOL
2 0V 4 5V 6 0V 4 5V 6 0V 6 0V
ILKG IIN ICC
Maximum High Level VIN e VIH or VIL Output Leakage Current VOUT e VCC Maximum Input Current Maximum Quiescent Supply Current
VIN e VCC or GND 6 0V VIN e VCC or GND 6 0V IOUT e 0 mA
20
20
40
Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89
2
AC Electrical Characteristics
Symbol tPZL tPLZ Parameter Maximum Propagation Delay
VCC e 5V TA e 25 C CL e 15 pF tr e tf e 6 ns Conditions RL e 1 kX Typ 8 Guaranteed Limit Units ns
AC Electrical Characteristics
Symbol Parameter Conditions
VCC e 2 0V to 6 0V CL e 50 pF tr e tf e 6 ns unless otherwise specified VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V TA e 25 C Typ 74HC TA eb40 C to a 85 C 95 19 16 115 23 20 95 19 16 54HC TA eb55 C to a 125 C 110 22 19 135 27 23 110 22 19 Units
Guaranteed Limits 75 15 13 90 18 15 75 15 13 ns ns ns ns ns ns ns ns ns pF 10 10 10 pF
tPZL
Maximum Propagation Delay Maximum Propagation Delay Maximum Output Fall Time Power Dissipation Capacitance (Note 5) Maximum Input Capacitance
RL e 1 kX
30 8 7 30 13 12 30 8 7 8 5
tPLZ
RL e 1 kX
tTHL
CPD CIN
(per gate)
Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC The power dissipated by RL is not included
Physical Dimensions inches (millimeters)
Order Number MM54HC05J or MM74HC05J NS Package Number J14A
3
MM54HC05 MM74HC05 Hex Inverter (Open Drain)
Physical Dimensions inches (millimeters) (Continued)
Order Number MM74HC05N NS Package Number N14A
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