MM74HC166

MM54HC166 MM74HC166 8-Bit Parallel In Serial Out Shift Registers August 1989 MM54HC166 MM74HC166 8-Bit Parallel In Serial Out Shift Registers General Description The MM54HC166 MM74HC166 high speed 8-BIT PARALLEL-IN SERIAL-OUT SHIFT REGISTER utilizes advanced silicon-gate CMOS technology It has low power consumption and high noise immunity of standard CMOS integrated circuits along with the ability to drive 10 LS-TTL loads These Parallel-In or Serial-In Serial-Out shift registers feature gated CLOCK inputs and an overriding CLEAR input The load mode is established by the SHIFT LOAD input When high this input enables the SERIAL INPUT and couples the eight flip-flops for serial shifting with each clock pulse When low the PARALLEL INPUTS are enabled and synchronous loading occurs on the next clock pulse During parallel loading serial data flow is inhibited Clocking is accomplished on the low-to-high level edge of the CLOCK pulse through a 2-input NOR gate permitting one input to be used as a clock enable or CLOCK INHIBIT function Holding either of the clock inputs high inhibits clocking holding either low enables the other clock input This allows the system clock to be free running and the register can be stopped on command with the other clock input The CLOCK INHIBIT input should be changed to the high level only while the clock input is high A direct CLEAR input overrides all other inputs including the CLOCK and sets all flipflops to zero The 54HC 74HC logic family is functionally as well as pin out compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and Ground Features Y Y Y Y Y Typical propagation delay Wide operating supply voltage range 2V – 6V Low input current k1 mA Low quiescent supply current 80 mA maximum (74HC Series) Fanout of 10 LS-TTL loads Connection Diagram Dual-In-Line Package Function Table Inputs Internal Output Shift Clock Parallel Outputs Clear Clock Serial QH Load Inhibit A H QA QB L H H H H H X X L H H X X L L L L H X L X X X H L X X X ah X X X L L QA0 QB0 a b H QAn L QAn QA0 QB0 L QH0 h QGn QGn QH0 u u u u H e High Level (steady state) L e Low Level (steady state) X e Don’t Care (any input including transitions) u e Transition from low to high level a h e The level of steady-state input at inputs A through H respectively QA0 QB0 QH0 e The level of QA QB QH respectively before the indicated steady-state input conditions were established QAn QGn e The level of QA QG respectively before the most recent transition of the clock u TL F 5770 – 1 Order Number MM54HC166 or MM74HC166 C1995 National Semiconductor Corporation TL F 5770 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Supply Voltage (VCC) DC Input or Output Voltage (VIN VOUT) Operating Temp Range (TA) MM74HC MM54HC Input Rise or Fall Times (tr tf) VCC e 2 0V VCC e 4 5V VCC e 6 0V Min 2 0 b 40 b 55 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5V to a 7 0V Supply Voltage (VCC) b 1 5V to VCC a 1 5V DC Input Voltage (VIN) b 0 5V to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per Pin (IOUT) g 50 mA DC VCC or GND Current per Pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temperature (TL) (Soldering 10 seconds) 260 C Max 6 VCC a 85 a 125 Units V V C C ns ns ns 1000 500 400 DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V VIN e VIH or VIL lIOUTl s20 mA 2 0V 4 5V 6 0V 4 5V 6 0V 2 0V 4 5V 6 0V 4 5V 6 0V 6 0V 20 45 60 42 57 0 0 0 02 02 TA e 25 C Typ VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 15 3 15 42 05 1 35 18 19 44 59 3 98 5 48 01 01 01 0 26 0 26 g0 1 74HC TA eb40 C to a 85 C 54HC TA eb55 C to a 125 C Units Guaranteed Limits 15 3 15 42 05 1 35 18 19 44 59 3 84 5 34 01 01 01 0 33 0 33 g1 0 15 3 15 42 05 1 35 18 19 44 59 37 52 01 01 01 04 04 g1 0 V V V V V V V V V V V V V V V V mA VIL VOH VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN e VCC or GND VCC e 2V – 6V VIN e VCC or GND IOUT e 0 mA VCC e 2V – 6V 6 0V 80 80 160 mA Note 1 Absolute Maximum ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst-case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst-case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst-case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89 2 AC Electrical Characteristics CL e 50 pF Symbol fMAX Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to QH Maximum Propagation Delay Clear to Qh Minimum Setup Time Shift Load to Clock Minimum Setup Time Data before Clock Minimum Removal Time Clear to Clock Maximum Hold Time Data after Clock Maximum Output Rise and Fall Time Minimum Pulse Width Clock or Clear Power Dissipation Capacitance (Note 5) Maximum Input Capacitance VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V (per package) 5 7 14 Typ tr e tf e 6 ns unless otherwise noted 74HC TA eb40 C to a 85 C 5 25 29 175 35 30 165 35 30 100 20 18 100 20 18 0 0 0 0 0 0 95 19 16 100 20 16 54HC TA eb55 C to a 125 C 42 21 25 210 42 36 195 39 33 120 24 20 120 24 20 0 0 0 0 0 0 110 22 19 120 24 20 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF 10 10 pF TA e 25 C Guaranteed Limits 6 31 36 140 28 24 130 26 22 80 16 14 80 16 14 0 0 0 0 0 0 75 15 13 80 16 14 100 10 tPHL tPLH tPHL tPLH tsu 11 tsu tREM th tr tf tw Cpd Cin AC Electrical Characteristics VCC e 5V Symbol fMAX tPHL tPLH tPHL tPLH tsu Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Qh Maximum Propagation Delay Clear to Qh Minimum Setup Time Shift Load High to Clock Minimum Setup Time Data before Clock Minimum Removal Time Clear to Clock Maximum Hold Time Data after Clock Minimum Pulse Width Clock or Clear CL e 15 pF TA e 25 C tr e tf e 6 ns unless otherwise noted Typical Guaranteed Limits 31 16 12 16 16 0 0 16 Units MHz ns ns ns ns ns ns ns tsu tREM th tw Note 5 Cpd determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 3 Logic Diagram TL F 5770 – 2 4 Logic Diagram Typical Clear Shift Load Inhibit and Shift Sequences TL F 5770 – 3 5 MM54HC166 MM74HC166 8-Bit Parallel In Serial Out Shift Registers Physical Dimensions inches (millimeters) Order Number MM54HC166 or MM74HC166 NS Package Number M16A Order Number MM54HC166 or MM74HC166 NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for 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