MM74HC193

MM54HC192 MM74HC192 Synchronous Decade Up Down Counters MM54HC193 MM74HC193 Synchronous Binary Up Down Counters January 1988 MM54HC192 MM74HC192 Synchronous Decade Up Down Counters MM54HC193 MM74HC193 Synchronous Binary Up Down Counters General Description These high speed synchronous counters utilize advanced silicon-gate CMOS technology to achieve the high noise immunity and low power consumption of CMOS technology along with the speeds of low power Schottky TTL The MM54HC192 MM74HC192 is a decade counter and the MM54HC193 MM74HC193 is a binary counter Both counters have two separate clock inputs an UP COUNT input and a DOWN COUNT input All outputs of the flip-flops are simultaneously triggered on the low to high transition of either clock while the other input is held high The direction of counting is determined by which input is clocked These counters may be preset by entering the desired data on the DATA A DATA B DATA C and DATA D inputs When the LOAD input is taken low the data is loaded independently of either clock input This feature allows the counters to be used as divide-by-n counters by modifying the count length with the preset inputs In addition both counters can also be cleared This is accomplished by inputting a high on the CLEAR input All 4 internal stages are set to a low level independently of either COUNT input Both a BORROW and CARRY output are provided to enable cascading of both up and down counting functions The BORROW output produces a negative going pulse when the counter underflows and the CARRY outputs a pulse when the counter overflows The counters can be cascaded by connecting the CARRY and BORROW outputs of one device to the COUNT UP and COUNT DOWN inputs respectively of the next device All inputs are protected from damage due to static discharge by diodes to VCC and ground Features Y Y Y Y Y Y Typical propagation delay Count up to Q 28 ns Typical operating frequency 27 MHz Wide power supply range 2 – 6V Low quiescent supply current 80 mA maximum (74HC Series) Low input current 1 mA maximum 4 mA output drive Connection Diagram Dual-In-Line Package Truth Table Count Up Down H Clear L L H L Load H H X L Function Count Up Count Down Clear Load u H X X L e low level u X X H e high level u e transition from low-to-high X e don’t care TL F 5011 – 1 Order Number MM54HC192 193 or MM74HC192 193 C1995 National Semiconductor Corporation TL F 5011 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Supply Voltage (VCC) DC Input or Output Voltage (VIN VOUT) Operating Temp Range (TA) MM74HC MM54HC Input Rise or Fall Times VCC e 2V (tr tf) VCC e 4 5V VCC e 6 0V Min 2 0 Max 6 VCC Units V V If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5 to a 7 0V Supply Voltage (VCC) b 1 5 to VCC a 1 5V DC Input Voltage (VIN) b 0 5 to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per pin (IOUT) g 50 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temp (TL) (Soldering 10 seconds) 260 C b 40 b 55 a 85 a 125 C C ns ns ns 1000 500 400 DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V VIN e VIH or VIL lIOUTl s20 mA 2 0V 4 5V 6 0V 4 5V 6 0V 2 0V 4 5V 6 0V 4 5V 6 0V 6 0V 6 0V 20 45 60 42 57 0 0 0 02 02 TA e 25 C Typ VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 15 3 15 42 05 1 35 18 19 44 59 3 98 5 48 01 01 01 0 26 0 26 g0 1 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units Guaranteed Limits 15 3 15 42 05 1 35 18 19 44 59 3 84 5 34 01 01 01 0 33 0 33 g1 0 15 3 15 42 05 1 35 18 19 44 59 37 52 01 01 01 04 04 g1 0 V V V V V V V V V V V V V V V V mA mA VIL VOH VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN e VCC or GND VIN e VCC or GND IOUT e 0 mA 80 80 160 Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89 2 AC Electrical Characteristics TA e 25 C Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH Parameter Maximum Clock Frequency Maximum Propagation Delay Low to High Maximum Propagation Delay High to Low Maximum Propagation Delay Low to High Maximum Propagation Delay High to Low Maximum Propagation Delay Low to High Maximum Propagation Delay High to Low Maximum Propagation Delay Low to High Maximum Propagation Delay High to Low Maximum Propagation Delay High to Low VCC e 5 0V tr e tf e 6 ns CL e 15 pF (unless otherwise specified) Conditions Typ 27 31 17 Guaranteed Limit 20 24 26 24 24 24 40 52 42 Units MHz MHz ns ns ns ns ns ns ns Count Up Count Down Count Up to Carry 18 16 Count Down to Borrow 15 28 Count Up Or Down to Q 36 30 Data or Load to Q 40 35 ’HC192 ’HC193 ’HC192 ’HC193 40 20 40 10 15 10 b3 tPHL tPHL 55 47 52 26 52 20 22 20 0 10 ns ns ns ns ns ns ns ns ns ns Clear to Q Clear tW Minimum Pulse Width Load Count Up Down tSD tHD tREM Minimum Setup time Minimum Hold Time Minimum Removal Time Data to Load Clear Inactive to Clock AC Electrical Characteristics VCC e 2 0V to 6 0V Symbol Parameter Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V CL e 50 pF tr e tf e 6 ns 74HC 54HC TA eb40 to 85 C TA eb55 to 125 C Units Guaranteed Limits 25 14 16 3 16 18 175 35 30 163 33 28 2 12 13 2 11 12 210 42 36 195 39 33 MHz MHz MHz MHz MHz MHz ns ns ns ns ns ns TA e 25 C Typ Count Up fMAX Maximum Clock Frequency Count Down tPLH Maximum Propagation Delay Low to High Count Up Maximum Propagation Delay to Carry High to Low 5 25 29 5 27 31 30 13 11 39 16 14 3 18 20 4 20 23 140 28 24 130 26 22 tPHL 3 AC Electrical Characteristics (Continued) VCC e 2 0V to 6 0V Symbol Parameter Conditions Count Down to Borrow VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V Typ tPLH tPHL Maximum Propagation Delay 39 16 14 30 8 7 77 35 30 95 45 38 85 37 30 CL e 50 pF tr e tf e 6 ns 74HC 54HC TA eb40 to 85 C TA eb55 to 125 C Units Guaranteed Limits 163 33 28 95 19 16 269 54 46 344 69 59 288 58 49 363 73 61 331 66 56 325 65 56 125 25 21 138 28 24 163 33 28 125 25 22 0 0 0 10 10 10 500 300 200 10 195 39 33 110 22 19 323 65 55 413 83 71 345 69 59 435 87 74 398 80 68 390 78 68 150 30 26 165 33 29 195 39 33 150 30 25 0 0 0 10 10 10 500 300 200 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF TA e 25 C 130 26 22 75 15 13 215 43 37 275 55 47 230 46 39 290 58 49 265 53 45 260 52 45 100 20 17 110 22 19 130 26 22 100 20 17 0 0 0 10 10 10 500 300 200 tTLH tTHL Maximum Output Rise and Fall Time tPLH Maximum Propagation Delay Low to High Maximum Propagation Delay High to Low Maximum Propagation Delay Low to High Maximum Propagation Delay High to Low Maximum Propagation Delay High to Low Data or Load to Q Count Up Or Down to Q tPHL tPLH tPHL 2 0V 102 4 5V 47 6 0V 39 2 0V 4 5V 6 0V 85 42 38 tPHL Clear to Q Clear or Load Load 2 0V 119 ’HC192 4 5V 42 6 0V 38 2 0V ’HC193 4 5V 6 0V 31 10 9 43 17 15 70 21 19 30 10 9 tW Minimum Pulse Width 2 0V Count Up Down 4 5V 6 0V Clear 2 0V ’HC193 4 5V 6 0V 2 0V 4 5V 6 0V tSD Minimum Setup Time Data To Load tHD tREM Minimum Hold Time Minimum Removal Time Clear Inactive to Clock 2 0V b30 4 5V b3 6 0V b3 2 0V b20 4 5V b3 6 0V b2 2 0V 4 5V 6 0V 5 100 tr tf CIN CPD Maximum Count Up or Down Input Rise Fall Time Input Capacitance Power Dissipation Capacitance (Note 5) 10 Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 4 Logic Diagrams MM54HC192 Synchronous 4-Bit Up Down Decade Counter 5 TL F 5011 – 2 Logic Diagrams (Continued) MM54HC193 Synchronous 4-Bit Up Down Binary Counter 6 TL F 5011 – 3 Logic Waveforms ’HC192 Synchronous Decade Counters Typical Clear Load and Count Sequences TL F 5011 – 4 Sequences (1) Clear outputs to zero (2) Load (preset) to BCD seven (3) Count up to eight nine carry zero one and two (4) Count down to one zero borrow nine eight and seven ’HC193 Synchronous Binary Counters Typical Clear Load and Count Sequences TL F 5011 – 5 Sequence (1) Clear outputs to zero (2) Load (preset) to binary thirteen (3) Count up to fourteen fifteen carry zero one and two (4) Count down to one zero borrow fifteen fourteen and thirteen Note A Clear overrides load data and count inputs Note B When counting up count-down input must be high when counting down count-up input must be high 7 MM54HC192 MM74HC192 Synchronous Decade Up Down Counters MM54HC193 MM74HC193 Synchronous Binary Up Down Counters Physical Dimensions inches (millimeters) Order Number MM54HC192J MM54HC193J MM74HC192J or MM74HC193J NS Package J16A Order Number MM74HC192N or MM74HC193N NS Package N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications