MM74HC58J

MM54HC51 MM74HC51 Dual AND-OR-Invert Gate MM54HC58 MM74HC58 Dual AND-OR Gate January 1988 MM54HC51 MM74HC51 Dual AND-OR-Invert Gate MM54HC58 MM74HC58 Dual AND-OR Gate General Description These gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits All gates have buffered outputs providing high noise immunity and the ability to drive 10 LS-TTL loads The 54HC 74HC logic family is functionally as well as pin-out compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features Y Y Y Y Y Typical propagation delay 10 ns Wide power supply range 2 – 6V Low quiescent supply current 20 mA maximum (74 Series) Low input current 1 mA maximum High output current 4 mA minimum Connection Diagrams Dual-In-Line Package TL F 5302 – 1 Top View Order Number MM54HC51 or MM74HC51 Dual-In-Line Package TL F 5302 – 2 Top View Order Number MM54HC58 or MM74HC58 C1995 National Semiconductor Corporation TL F 5302 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Min Supply Voltage VCC DC Input or Output Voltage VIN VOUT Operating Temp Range (TA) MM HC MM HC Input Rise or Fall Times tr tf VCC e V VCC e V VCC e V b b If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5 to a 7 0V Supply Voltage (VCC) b 1 5 to VCC a 1 5V DC Input Voltage (VIN) b 0 5 to VCC a 0 5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per pin (IOUT) g 50 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temp (TL) (Soldering 10 seconds) 260 C Max VCC Units V V a a C C ns ns ns DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC V V V V V V VIN e VIH or VIL lIOUTl s mA V V V V V V V V V V V V g g g TA e 25 C Typ 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units Guaranteed Limits V V V V V V V V V V V V V V V V mA mA VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VIL VOH VIN e VIH or VIL lIOUTl s mA lIOUTl s mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s mA VIN e VIH or VIL lIOUTl s mA lIOUTl s mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN e VCC or GND VIN e VCC or GND IOUT e mA Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89 2 AC Electrical Characteristics VCC e 5V Symbol tPHL tPLH Parameter Maximum Propagation Delay Conditions TA e 25 C CL e 15 pF tr e tf e 6 ns Typ 10 Guaranteed Limit 20 Units ns AC Electrical Characteristics VCC e 2 0V to 6 0V Symbol Parameter Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V (per AND-OR-Gate) CL e 50 pF tr e tf e 6 ns (unless otherwise specified) 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units TA e 25 C Typ Guaranteed Limits 125 25 21 75 15 13 158 32 27 95 19 16 186 37 32 110 22 19 ns ns ns ns ns ns pF 10 10 10 pF tPHL tPLH Maximum Propagation Delay Maximum Output Rise and Fall Time Power Dissipation Capacitance (Note 5) Maximum Input Capacitance 63 13 11 30 8 7 20 5 tTLH tTHL CPD CIN Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 3 MM54HC51 MM74HC51 Dual AND-OR-Invert Gate MM54HC58 MM74HC58 Dual AND-OR Gate Physical Dimensions inches (millimeters) Order Numbers MM54HC51J MM54HC58J MM74HC51J MM74HC58J NS Package J14A Order Numbers MM74HC51N MM74HC58N NS Package N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications