MM74HC73

MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear January 1988 MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear General Description These J-K Flip-Flops utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power dissipation of standard CMOS integrated circuits These devices can drive 10 LS-TTL loads These flip-flops are edge sensitive to the clock input and change state on the negative going transition of the clock pulse Each one has independent J K CLOCK and CLEAR inputs and Q and Q outputs CLEAR is independent of the clock and accomplished by a low level on the input The 54HC 74HC logic family is functionally as well as pinout compatible with the standard 54LS 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features Y Y Y Y Y Typical propagation delay 16 ns Wide operating voltage range 2 – 6V Low input current 1 mA maximum Low quiescent current 40 mA (74HC Series) High output drive 10 LS-TTL loads Connection and Logic Diagrams Dual-In-Line Package Truth Table Inputs CLR L H H H H H CLK X J X L H L H X K X L L H H X Outputs Q Q v v v v H L H Q0 Q0 H L L H TOGGLE Q0 Q0 Top View TL F 5072–1 Order Number MM54HC73 or MM74HC73 TL F 5072 – 2 TL F 5072 – 3 (1 of 2) C1995 National Semiconductor Corporation TL F 5072 RRD-B30M115 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Supply Voltage (VCC) DC Input or Output Voltage (VIN VOUT) Operating Temp Range (TA) MM74HC MM54HC Input Rise or Fall Times (tr tf) VCC e 2 0V VCC e 4 5V VCC e 6 0V Min 2 0 Max 6 VCC Units V V If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK IOK) DC Output Current per pin (IOUT) DC VCC or GND Current per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S O Package only Lead Temperature (TL) (Soldering 10 seconds) b 0 5 to a 7 0V b 1 5 to VCC a 1 5V b 0 5 to VCC a 0 5V g 20 mA g 25 mA g 50 mA b 40 b 55 a 85 a 125 C C ns ns ns b 65 C to a 150 C 1000 500 400 600 mW 500 mW 260 C DC Electrical Characteristics (Note 4) Symbol Parameter Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V VIN e VIH or VIL lIOUTl s20 mA 2 0V 4 5V 6 0V 4 5V 6 0V 2 0V 4 5V 6 0V 4 5V 6 0V 6 0V 6 0V 20 45 60 42 57 0 0 0 02 02 TA e 25 C Typ VIH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage 15 3 15 42 05 1 35 18 19 44 59 3 98 5 48 01 01 01 0 26 0 26 g0 1 74HC TA eb40 to 85 C 54HC TA eb55 to 125 C Units Guaranteed Limits 15 3 15 42 05 1 35 18 19 44 59 3 84 5 34 01 01 01 0 33 0 33 g1 0 15 3 15 42 05 1 35 18 19 44 59 37 52 01 01 01 04 04 g1 0 V V V V V V V V V V V V V V V V mA mA VIL VOH VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA VIN e VIH or VIL lIOUTl s4 0 mA lIOUTl s5 2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN e VCC or GND VIN e VCC or GND IOUT e 0 mA 40 40 80 Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C Note 4 For a power supply of 5V g 10% the worst case output voltages (VOH and VOL) occur for HC at 4 5V Thus the 4 5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC e 5 5V and 4 5V respectively (The VIH value at 5 5V is 3 85V ) The worst case leakage current (IIN ICC and IOZ) occur for CMOS at the higher voltage and so the 6 0V values should be used VIL limits are currently tested at 20% of VCC The above VIL specification (30% of VCC) will be implemented no later than Q1 CY’89 2 AC Electrical Characteristics VCC e 5V Symbol fMAX tPHL tPLH tPHL tPLH tREM tS tH tW Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q or Q Maximum Propagation Delay Clear to Q or Q Minimum Removal Time Clear to Clock Minimum Setup Time J or K to Clock Minimum Hold Time J or K to Clock Minimum Pulse Width Clock or Clear TA e 25 C CL e 15 pF tr e tf e 6 ns Typ 50 16 21 10 14 b3 Conditions Guaranteed Limit 30 21 26 20 20 0 16 Units MHz ns ns ns ns ns ns 10 AC Electrical Characteristics CL e 50 pF Symbol fMAX Parameter Maximum Operating Frequency Maximum Propagation Delay Clock to Q or Q Maximum Propagation Delay Clear to Q or Q Minimum Removal Time Clear to Clock Minimum Setup Time J or K to Clock Minimum Hold Time J or K from Clock Minimum Pulse Width Clock or Clear Maximum Output Rise and Fall Time Maximum Input Rise and Fall Time Power Dissipation Capacitance (Note 5) Maximum Input Capacitance (per flip-flop) Conditions VCC 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V 2 0V 4 5V 6 0V tr e tf e 6 ns (unless otherwise specified) TA e 25 C Typ 9 45 53 70 18 15 126 25 21 55 11 9 77 15 4 13 b3 b3 b3 74HC TA eb40 to 85 C 4 21 25 160 32 27 194 39 32 125 25 21 125 25 21 0 0 0 100 20 18 95 19 16 1000 500 400 54HC TA eb55 to 125 C 3 18 21 185 37 32 250 47 40 150 30 25 150 30 25 0 0 0 120 24 21 110 22 19 1000 500 400 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF Guaranteed Limits 5 27 32 126 25 21 155 31 26 100 20 17 100 20 17 0 0 0 80 16 14 75 15 13 1000 500 400 tPHL tPLH tPHL tPLH tREM tS tH tW 55 11 9 30 8 7 tTLH tTHL tr tf CPD CIN 80 5 10 10 10 pF Note 5 CPD determines the no load dynamic power consumption PD e CPD VCC2 f a ICC VCC and the no load dynamic current consumption IS e CPD VCC f a ICC 3 Typical Applications N Bit Binary Ripple Counter with Enable and Reset TL F 5072 – 4 N Bit Shift Register with Clear TL F 5072 – 5 4 5 MM54HC73 MM74HC73 Dual J-K Flip-Flops with Clear Physical Dimensions inches (millimeters) Dual-In Line Package (J) Order Number MM54HC73J or MM74HC73J NS Package J14A Dual-In Line Package (N) Order Number MM74HC73N NS Package N14A NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein LIFE SUPPORT POLICY 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications