MM74HC942

MM74HC942 300 Baud Modem January 1988 MM74HC942 300 Baud Modem General Description The MM74HC942 is a full duplex low speed modem It provides a 300 baud bidirectional serial interface for data communication over telephone lines and other narrow bandwidth channels It is Bell 103 compatible The MM74HC942 utilizes advanced silicon-gate CMOS technology Switched capacitor techniques are used to perform analog signal processing MODULATOR SECTION The modulator contains a frequency synthesizer and a sine wave synthesizer It produces a phase coherent frequency shift keyed (FSK) output LINE DRIVER AND HYBRID SECTION The line driver and hybrid are designed to facilitate connection to a 600X phone line They can perform two-to-fourwire conversion and drive the line at a maximum of 0 dBm DEMODULATOR SECTION The demodulator incorporates anti-aliasing filters a receive filter limiter discriminator and carrier detect circuit The nine pole receive filter provides 60 dB of transmitted tone rejection The discriminator is fully balanced for stable operation Features Y Y Y Y Y Y Y Y Y Y Drives 600X at 0 dBm All filters on chip Transmit level adjustment compatible with universal service order code TTL and CMOS compatible logic All inputs protected against static damage g 5V supplies Low power consumption Full duplex answer or originate operation Analog loopback for self test Power down mode Applications Y Y Y Y Y Y Y Y Built-in low speed modems Remote data collection Radio telemetry Credit verification Stand-alone modems Point-of-sale terminals Tone signalling systems Remote process control TRI-STATE is a registered trademark of National Semiconductor Corp Connection and Block Diagrams Dual-In-Line Package TL F 5348–1 Top View Order Number MM54HC942 or MM74HC942 TL F 5348 – 2 C1995 National Semiconductor Corporation TL F 5348 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 2) Operating Conditions Supply Voltage (VCC) Supply Voltage (VBB) DC Input or Output Voltage (VIN VOUT) Operating Temp Range (TA) MM74HC Input Rise or Fall Times (tr tf) Crystal frequency Min 45 b4 5 0 Max 55 b5 5 VCC Units V V V If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5 to a 7 0V Supply Voltage (VCC) a 0 5 to b 7 0V Supply Voltage (VBB) VBBb1 5 to VCC a 1 5V DC Input Voltage (VIN) DC Output Voltage (VOUT) VBBb0 5 to VCC a 0 5V g 20 mA Clamp Diode Current (IIK IOK) g 25 mA DC Output Current per pin (IOUT) g 50 mA DC VCC or GND Current per pin (ICC) b 65 C to a 150 C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S O Package only 500 mW Lead Temp (TL) (Soldering 10 seconds) 260 C b 40 a 85 C ns MHz 500 3 579 DC Electrical Characteristics Symbol Parameter Conditions Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage Maximum Low Level Voltage Maximum Input Current Output TRI-STATE Leakage Current RXD and CD Outputs Maximum Quiescent Supply Current Power Down Supply Current VIN e VIH or VIL lIOUTl e 20 mA lIOUTl e 4 0 mA VCC e 4 5V VIN e VIH or VIL lIOUTl e 20 mA lIOUTl e 4 0 mA VCC e 4 5V VIN e VCC or GND ALB e SQT e VCC VCC T e 25 C 74HC T eb40 to 85 C Guaranteed Limits 3 15 11 3 15 11 V V Units VCCb0 1 3 98 01 0 26 g0 1 VCCb0 1 37 01 04 g1 0 V V V V mA mA VOL IIN IOZ g5 ICC IBB VIH e VCC VIL e GND ALB or SQT e GND Transmit Level e b9 dBm ALB e SQT e VCC VIH e VCC VIL e GND 80 12 0 12 0 mA ICC IBB 300 mA Note 1 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2 Unless otherwise specified all voltages are referenced to ground Note 3 Power Dissipation temperature derating plastic ‘‘N’’ package b 12 mW C from 65 C to 85 C ceramic ‘‘J’’ package b 12 mW C from 100 C to 125 C The demodulator specifications apply to the MM74HC942 operating with a modulator having frequency accuracy phase jitter and harmonic content equal to or better than the MM74HC942 modulator 2 AC Electrical Characteristics Unless otherwise specified all specifications apply to the MM74HC942 over the range b40 C to a 85 C using a VCC e a 5V g 10% a VBB e b 5V g 10% and a 3 579MHz g 0 1% crystal Symbol TRANSMITTER FCE Carrier Frequency Error Power Output VCC e 5 0V RL e 1 2 kX 2nd Harmonic Energy RECEIVE FILTER AND HYBRID Hybrid Input Impedance (Pins 15 and 16) FTLC Output Impedance Adjacent Channel Rejection RXA2 e GND TXA e GND or VCC Input to RXA1 50 5 60 10 50 kX kX dB RTLA e 0X RTLA e 5 49 kX RTLA e 0X b3 b 12 b1 5 b 10 5 b 62 Parameter Conditions Min Typ Max Units 4 0 b9 b 56 Hz dBm dBm dBm DEMODULATOR (INCORPORATING HYBRID RECEIVE FILTER AND DISCRIMINATOR) Carrier Amplitude Bit Jitter SNR e 30 dB Input e b38 dBm Baud Rate e 300 Baud Alternating 1-0 Pattern CDA e 1 2V VCC e 5 0V Carrier Detect Hysteresis VCC e 5V Off to On On to Off b 48 b9 dBm mS Bit Bias Carrier Detect Trip Points ( b 45 b 47 100 200 5 b 42 b 45 10 b 40 b 42 % dBm dBm dB 2 3 4 AC Specification Circuit TL F 5348 – 3 3 Description of Pin Functions Pin No 1 Name DSI Function Driver Summing Input This may be used to transmit externally generated tones such as dual tone multifrequency (DTMF) dialing signals Analog Loop Back A logic high on this pin causes the modulator output to be connected to the demodulator input so that data is looped back through the entire chip This is used as a chip self test If ALB and SQT are simultaneously held high the chip powers down Carrier Detect This pin goes to a logic low when carrier is sensed by the carrier detect circuit Carrier Detect Timing A capacitor on this pin sets the time interval that the carrier must be present before the CD goes low Received Data This is the data output pin Positive Supply Pin A a 5V supply is recommended Carrier Detect Adjust This is used for adjustment of the carrier detect threshold Carrier detect hysteresis is set at 3 dB Crystal Drive XTALD and XTALS connect to a 3 5795 MHz crystal to generate a crystal locked clock for the chip If an external circuit requires this clock XTALD should be sensed If a suitable clock is already available in the system XTALD can be driven Crystal Sense Refer to Pin 8 for details Filter Test Limiter Capacitor This is connected to a high impedance output of the receive filter It may thus be used to evaluPin No Name Function ate filter performance This pin may also be driven to evaluate the demodulator RXA1 and RXA2 must be grounded during this test For normal modem operation FTLC is AC grounded via a 0 1 mF bypass capacitor Transmitted Data This is the data input Negative Supply The recommended supply is b5V Originate Answer mode select When logic high this pin selects the originate mode of operation Squelch Transmitter This disables the modulator when held high The EXI input remains active If SQT and ALB are simultaneously held high the chip powers down Receive Analog 2 RXA2 and RXA1 are analog inputs When connected as recommended they produce a 600X hybrid Receive Analog 1 See RXA2 for details Transmit Analog This is the output of the line driver External Input This is a high impedance input to the line driver This input may be used to transmit externally generated tones When not used for this purpose it should be grounded Ground This defines the chip 0V Transmit Level Adjust A resistor from this pin to VCC sets the transmit level 2 ALB 11 12 13 TXD VBB OA 3 CD 14 SQT 4 CDT 5 6 7 RXD VCC CDA 15 RXA2 16 17 18 RXA1 TXA EXI 8 XTALD 9 10 XTALS FTLC 19 20 GND TLA Functional Description INTRODUCTION A modem is a device for transmitting and receiving serial data over a narrow bandwidth communication channel The MM74HC942 uses frequency shift keying (FSK) of an audio frequency tone The tone may be transmitted over the switched telephone network and other voice grade channels The MM74HC942 is also capable of demodulating FSK signals By suitable tone allocation and considerable signal processing the MM74HC942 is capable of transmitting and receiving data simultaneously The tone allocation by the MM74HC942 and other Bell 103 compatible modems is shown in Table I The terms ‘‘originate’’ and ‘‘answer’’ which define the frequency allocation come from use with telephones The modem on the end of the line which initiates the call is called the originate modem The other modem is the answer modem TABLE I BELL 103 Allocation Data Space Mark Originate Modem Transmit 1070Hz 1270Hz Receive 2025Hz 2225Hz Answer Modem Transmit 2025Hz 2225Hz Receive 1070Hz 1270Hz THE LINE INTERFACE The line interface section performs two to four wire conversion and provides impedance matching between the modem and the phone line THE LINE DRIVER The line driver is a power amplifier for driving the line If the modem is operating as an originate modem the second harmonics of the transmitted tones fall close to the frequencies of the received tones and degrade the received signal to noise ratio (SNR) The line driver must thus produce low second harmonic distortion THE HYBRID The voltage on the telephone line is the sum of the transmitted and received signals The hybrid subtracts the transmitted voltage from the voltage on the telephone line If the telephone line was matched to the hybrid impedance the output of the hybrid would be only the received signal This rarely happens because telephone line characteristic impedances vary considerably The hybrid output is thus a mixture of transmitted and received signals 4 Functional Description THE DEMODULATOR SECTION The Receive Filter (Continued) The demodulator recovers the data from the received signals The signal from the hybrid is a mixture of transmitted signal received signals and noise The first stage of the receive filter is an anti-alias filter which attenuates high frequency noise before sampling occurs The signal then goes to the second stage of the receive filter where the transmitted tones and other noise are filtered from the received signal This is a switched capacitor nine-pole filter providing at least 60 dB of transmitted tone rejection This also provides high attenuation at 60 Hz a common noise component The Discriminator The first stage of the discriminator is a hard limiter The hard limiter removes from the received signal any amplitude modulation which may bias the demodulator toward a mark or a space It compares the output of the receive filter to the voltage on the 0 1 mF capacitor on the FTLC pin The hard limiter output connects to two parallel bandpass filters in the discriminator One filter is tuned to the mark frequency and the other to the space frequency The outputs of these filters are rectified filtered and compared If the output of the mark path exceeds the output of the space path the RXD output goes high The opposite case sends RXD low The demodulator is implemented using precision switched capacitor techniques The highly critical comparators in the limiter and discriminator are auto-zeroed for low offset Carrier Detector The output of the discriminator is meaningful only if there is sufficient carrier being received This is established in the carrier detection circuit which measures the signal on the line If this exceeds a certain level for a preset period (adjustable by the CDT pin) the CD output goes low indicating that carrier is present Then the carrier detect threshold is lowered by 3 dB This provides hysteresis ensuring the CD output remains stable If carrier is lost CD goes high after the preset delay and the threshold is increased by 3 dB MODULATOR SECTION The modulator consists of a frequency synthesizer and a sine wave synthesizer The frequency produces one of four tones depending on the O A and TXD pins The frequencies are synthesized to high precision using a crystal oscillator and variable dual modulus counter The counters used respond quickly to data changes introducing negligible bit jitter while maintaining phase coherence The sine wave synthesizer uses switched capacitors to ‘‘look up’’ the voltages of the sine wave This sampled signal is then further processed by switched capacitor and continuous filters to ensure the high spectral purity required by FCC regulations The transmit level is programmable by placing a resistor from TLA to VCC With a 5 5k resistor the line driver transmits a maximum of b9 dBm Since most lines from a phone installation to the exchange provide 3 dB of attenuation the maximum level reaching the exchange will be b12 dBm This is the maximum level permitted by most telephone companies Thus with this programming the MM74HC942 will interface to most telephones This arrangement is called the ‘‘permissive arrangement ’’ The disadvantage with the permissive arrangement is that when the loss from a phone to the exchange exceeds 3 dB no compensation is made and SNR may be unnecessarily degraded SNR can be maximized by adjusting the transmit level until the level at the exchange reaches b12 dBm This must be done with the cooperation of the telephone company The programming resistor used is specific for a given installation and is often included in the telephone jack at the installation The modem is thus programmable and can be used with any jack correctly wired This arrangement is called the universal registered jack arrangement and is possible with the MM74HC942 The values of resistors required to program the MM74HC942 follow the most common code in use the universal service order code The required resistors are given in Table II TABLE II Universal Service Order Code Resistor Values Line Loss (dB) 0 1 2 3 4 5 6 7 8 9 10 11 12 Transmit Level (dBm) b 12 b 11 b 10 b9 b8 b7 b6 b5 b4 b3 b2 b1 Programming Resistor (RTLA) (Ohms) Open 19 800 9 200 5 490 3 610 2 520 1 780 1 240 866 562 336 150 0 0 CARRIER DETECT THRESHOLD ADJUSTMENT The carrier detect threshold is directly proportional to the voltage on CDA This pin is connected internally to a high impedance source This source has a nominal Thevenin equivalent voltage of 1 2V and output impedance of 100 kX By forcing the voltage on CDA the carrier detect threshold may be adjusted To find the voltage required for a given threshold the following equation may be used VCDA e 244 c VON VCDA e 345 c VOFF CARRIER DETECT TIMING ADJUSTMENT CDT A capacitor on Pin 4 sets the time interval that the carrier must be present before CD goes low It also sets the time interval that carrier must be removed before CD returns high The relevant timing equations are TCDL j 6 4 c CCDT for CD going low TCDH j 0 54 c CCDT for CD going high Where TCDL TCDH are in seconds and CCDT is in mF Applications Information TRANSMIT LEVEL ADJUSTMENT The transmitted power levels of Table II refer to the power delivered to a 600X load from the external 600X source impedance The voltage on the load is half the TXA voltage This should be kept in mind when designing interface circuits which do not match the load and source impedances 5 Applications Information (Continued) DESIGN PRECAUTIONS Power supplies to digital systems may contain high amplitude spikes and other noise To optimize performance of the MM74HC942 operating in close proximity to digital systems supply and ground noise should be minimized This involves attention to power supply design and circuit board layout Power supply decoupling close to the device is recommended Ground loops should be avoided For further discussion of these subjects see the Audio Radio Handbook published by National Semiconductor Corporation Interface Circuits for MM74HC942 300 Baud Modem TL F 5348 – 4 CCDT and RTLA should be chosen to suit the application See the Applications Information for more details Complete Acoustically Coupled 300 Baud Modem TL F 5348 – 5 Note The efficiency of the acoustic coupling will set the valves of R1 and R2 6 7 MM74HC942 300 Baud Modem Physical Dimensions inches (millimeters) Order Number MM74HC942J NS Package J20A Order Number MM74HC942N NS Package N20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications