MICROCIRCUIT DATA SHEET MNDS90LV031A-X REV 1C0
Original Creation Date: 02/09/99 Last Update Date: 08/15/03 Last Major Revision Date: 02/21/00
3V LVDS Quad CMOS Differential Line Driver
General Description
The DS90LV031A is a quad CMOS differential line driver utilizing Low Voltage Differentional Signaling (LVDS) technology. It is designed for applications requiring low power dissipation and high data rates. The DS90LV031A accepts TTL/CMOS input levels and translates them to low voltage (350 mV) differential output siginals. In addition the driver supports a TRI-STATE function that may be used to disable the output stage, disabling the load current, and thus dropping the device to a low idle power state. The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. In addition, the DS90LV031A provides power-off high impedance LVDS outputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
Industry Part Number
DS90LV031A
NS Part Numbers
DS90LV031AW-MLS DS90LV031AW-QML DS90LV031AWGMLS DS90LV031AWGQML
Prime Die
DS90LV031A
Controlling Document
SEE FEATURES SECTION
Processing
MIL-STD-883, Method 5004
Subgrp Description
1 2 3 4 5 6 7 8A 8B 9 10 11 Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at Switching tests at Switching tests at Switching tests at
Temp ( oC)
+25 +125 -55 +25 +125 -55 +25 +125 -55 +25 +125 -55
Quality Conformance Inspection
MIL-STD-883, Method 5005
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MICROCIRCUIT DATA SHEET
Features
High impedance LVDS outputs with power-off 3.3V power supply design +/- 350mV differential signaling Low power dissipation. Low differential skew. Low propagation delay Interoperable with existing 5V LVDS devices Military operating temprature range Pin compatible with DS26C31. Compatible with IEEE 1596.3 SCI LVDS standard Compatible with proposed TIA/EIA-644 LVDS standard Typical Rise/Fall times of 800pS. Typical Tri-State Enable/Disable Delays of less than 5nS. CONTROLLING DOCUMENT: DS90LV031AW-QML 5962-9865101QFA DS90LV031AWGQML 5962-9865101QXA
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(Absolute Maximum Ratings)
(Note 1) Supply Voltage (Vcc) -0.3 to +4V Input Voltage (Din) -0.3 to (Vcc+0.3V) Enable Input Voltage (EN, EN*) -0.3 to (Vcc+0.3V) Output Voltage (Dout+, Dout-) -0.3 to +3.9V Storage Temperature Range -65C to +150C Lead Temperature Soldering (4 sec) 260C ESD Rating. 6000 Volts. Maximum Junction Temperature +150C Maximum Power Dissipation @ +25C (Note 2) 16 PIN CERPAK (W Pkg) 16 PIN CERAMIC SOIC (WG Pkg) Thermal Resistance. (Theta JA) 16 PIN CERPAK (W Pkg) 16 PIN CERAMIC SOIC (WG Pkg) Thermal Resistance. (Theta JC) 16 PIN CERPAK (W Pkg) 16 PIN CERAMIC SOIC (WG Pkg) Note 1:
845mW 845mW 148C/W 148C/W 22C/W 22C/W
Note 2:
Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Derate (W & WG Pkgs) at 6.8mW/C for temperatures above +25C.
Recommended Operating Conditions
Supply Voltage 3.0 to 3.6V Operating Free Air Temperature -55 to +125 C
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Electrical Characteristics
DC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.) DC: Vcc = 3.0/3.6V unless otherwise specified SYMBOL Vod1 DVod1 PARAMETER Differential Ouput Voltage Change in Magnitude of Vod1 for complementary output States Offset Voltage Change in Magnitude of Vos for Complementary Output States Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Input Current Input Current Input Clamp Voltage Output Short Circuit Current Power-off Leakage Output TRI-STATE Current No Load Enabled Current Drivers Supply Vin = Vcc or 2.5V, Vcc = 3.6V Vin = Gnd or 0.4V, Vcc = 3.6V Icl = -8mA, Vcc = 3.0V ENABLED Din = Vcc, Dout + = 0V or Din = Gnd, Dout- = 0V Vout = 0V or 3.6V Vcc = 0V or Vcc = Open EN = 0.8V and EN* = 2.0V VOUT = 0V or VCC, VCC = 3.6V Din = Vcc or Gnd RL = 100 Ohms RL = 100 Ohms CONDITIONS NOTES PINNAME Dout-, Dout+ Dout-, Dout+ MIN 250 MAX 450 50 UNIT mV mV SUBGROUPS 1, 2, 3 1, 2, 3
Vos DVos
RL = 100 Ohms RL = 100 Ohms
Dout-, Dout+ Dout-, Dout+
1.125
1.625 50
V mV
1, 2, 3 1, 2, 3
Voh Vol Vih Vil IIH IIL Vcl Ios Ioff Ioz Icc
RL = 100 Ohms RL = 100 Ohms 1 1
Dout-, Dout+ Dout-, Dout+ .9
1.85
V V
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Din, 2.0 EN, EN* Din, Gnd EN, EN* Din, EN, EN* Din, EN, EN* Din, EN, EN* Dout-, Dout+ Dout-, Dout+ Dout-, Dout+ Vcc
Vcc 0.8 +10 +10 -1.5 -9.0 +20 +10 18
V V uA uA V mA uA uA mA
Iccl
Loaded Drivers Enabled Supply Current Loaded or No Load Drivers Disabled Supply Current
Rl = 100 ohms All Channels, Din = Vcc or Gnd (all inputs) Din = Vcc or Gnd, En = Gnd, En* = Vcc
Vcc
35
mA
Iccz
Vcc
12
mA
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MNDS90LV031A-X REV 1C0
MICROCIRCUIT DATA SHEET
Electrical Characteristics
AC PARAMETERS
(The following conditions apply to all the following parameters, unless otherwise specified.) AC: VCC = 3.0/3.3/3.6V, RL = 100 Ohms, CL = 20pF SYMBOL tPHLD PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Skew tPHLD-tPLHD Channel to Channel Skew Chip to Chip Skew Note 1: Note 2: Note 3: 2 3 CONDITIONS NOTES PINNAME MIN 0.3 MAX 3.5 UNIT ns SUBGROUPS 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11
tPLHD
0.3
3.5
ns
tSKD tSK1 tSK2
1.5 1.75 3.2
ns ns ns
Tested during VOH/VOL tests. Channel to Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on the inputs. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
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Graphics and Diagrams
GRAPHICS# W16ARL WG16ARC DESCRIPTION CERPACK (W), 16 LEAD (P/P DWG) CERAMIC SOIC (WG), 16 LEAD (P/P DWG)
See attached graphics following this page.
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Revision History
Rev
0A0 1A0
ECN #
Rel Date
Originator
Mike Fitzgerald Mike Fitzgerald
Changes
Initial MDS Release Added WG pkg NSID's, split out Pkg references under the "Absolute Maximum Ratings" section for Thermal Resistance, and Power Dissipation. Added WG pkg Marketing Outline Drawing. Update MDS: MNDS90LV031A-X, Rev. 1A0 to MNDS90LV031A-X, Rev. 1B0. Added to Main Table NS Part Number DS90LV031AW-MLS. Moved reference to SMD number from Main Table to Features Section. Update MDS: MNDS90LV031A-X, Rev. 1B0 to 1C0. MDS enhancements: Additional verbage to the general discription, Main Table and Added new bullet to the Features Section.
M0003265 03/10/00 M0003630 08/16/02
1B0
M0004034 08/15/03
Rose Malone
1C0
M0004183 08/15/03
Rose Malone
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