NDS8963

N September 1996 ADVANCE INFORMATION NDS8963 Dual N-Channel Enhancement Mode Field Effect Transistor General Description SO-8 N-Channel enhancement mode power field effect transistors are produced using National's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. These devices are particularly suited for low voltage applications such as DC motor control and DC/DC conversion where fast switching, low in-line power loss, and resistance to transients are needed. Features 2.5A, 30V. RDS(ON) = 0.16Ω @ VGS = 10V RDS(ON) = 0.25Ω @ VGS = 4.5V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package. _______________________________________________________________________________________________ 5 6 7 8 4 3 2 1 Absolute Maximum Ratings Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed TA = 25°C unless otherwise note NDS8963 30 ±20 (Note 1a) Units V V A 2.5 7.5 2 Power Dissipation for Dual Operation Power Dissipation for Single Operation (Note 1a) (Note 1b) (Note 1c) W 1.6 1 0.9 -55 to 150 °C TJ,TSTG Operating and Storage Temperature Range THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient (Note 1a) Thermal Resistance, Junction-to-Case (Note 1) 78 40 °C/W °C/W NDS8963 Rev. A ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) ID(on) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = 250 µA VDS = 24 V, VGS = 0 V TJ = 55 C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse (Note 2) o 30 1 10 100 -100 V µA µA nA nA VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = 250 µA VGS = 10 V, ID = 2.5 A VGS = 4.5 V, ID = 2 A VGS = 10 V, VDS = 5 V VGS = 4.5 V, VDS = 5 V 7.5 3 1 ON CHARACTERISTICS Gate Threshold Voltage Static Drain-Source On-Resistance 3 0.16 0.25 V Ω A On-State Drain Current DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A (Note 2) 1.3 1.2 A V P D (t) = T J −T A R θJA (t) = T J −T A R θJC +R θCA (t) = I 2 (t) × R DS(ON)@T J D Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 78oC/W when mounted on a 0.5 in2 pad of 2oz copper. b. 125oC/W when mounted on a 0.02 in2 pad of 2oz copper. c. 135oC/W when mounted on a 0.003 in2 pad of 2oz copper. 1a 1b 1c Scale 1 : 1 on letter size paper. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. NDS8963 Rev. A