NM27C256V150

NM27C256 262 144-Bit (32K x 8) High Performance CMOS EPROM December 1993 NM27C256 262 144-Bit (32K x 8) High Performance CMOS EPROM General Description The NM27C256 is a 256K Electrically Programmable Read Only Memory It is manufactured in National’s latest CMOS split gate EPROM technology which enables it to operate at speeds as fast as 120 ns access time over the full operating range The NM27C256 provides microprocessor-based systems extensive storage capacity for large portions of operating system and application software Its 120 ns access time provides high speed operation with high-performance CPUs The NM27C256 offers a single chip solution for the code storage requirements of 100% firmware-based equipment Frequently-used software routines are quickly executed from EPROM storage greatly enhancing system utility The NM27C256 is configured in the standard EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs The NM27C256 is one member of a high density EPROM Family which range in densities up to 4 Mb Features Y Y Y Y High performance CMOS 120 ns access time JEDEC standard pin configuration 28-pin DIP package 32-pin chip carrier Drop-in replacement for 27C256 or 27256 Manufacturer’s identification code Block Diagram TL D 10833 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation HPCTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL D 10833 RRD-B30M65 Printed in U S A Connection Diagrams 27C080 27C040 27C020 27C010 27C512 A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND XX VPP XX VPP XX VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND TL D 10833 – 2 27C512 27C010 27C020 27C040 27C080 DIP NM27C256 VCC A14 A13 A8 A9 A11 OE VPP A10 CE PGM O7 O6 O5 O4 O3 VCC XX A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 VCC A17 A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 VCC A18 A17 A14 A13 A8 A9 A11 OE A10 O7 O6 O5 O4 O3 VCC A18 A17 A14 A13 A8 A9 A11 OE VPP A10 O7 O6 O5 O4 O3 XX PGM XX PGM CE PGM CE PGM Note Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C256 pins Commercial Temp Range (0 C to a 70 C) VCC e 5V g 10% Parameter Order Number NM27C256 Q N V 120 NM27C256 Q N V 150 NM27C256 Q N V 200 Access Time (ns) 120 150 200 Extended Temp Range (b40 C to a 85 C) VCC e 5V g 10% Parameter Order Number NM27C256 QE NE VE 120 NM27C256 QE NE VE 150 NM27C256 QE NE VE 200 Access Time (ns) 120 150 200 Military Temp Range (b55 C to a 125 C) VCC e 5V g 10% Parameter Order Number NM27C256 QM 150 NM27C256 QM 250 Access Time (ns) 150 250 Note Surface mount PLCC package available for commercial and extended temperature ranges only Package Types NM27C256 Q N V XXX Q e Quartz-Windowed Ceramic DIP N e Plastic OTP DIP V e Surface-Mount PLCC  All packages conform to the JEDEC standard  All versions are guaranteed to function for slower speeds PLCC Pin Names Symbol A0 – A14 CE OE O0 – O7 PGM XX Description Addresses Chip Enable Output Enable Outputs Program Don’t Care (during Read) Top TL D 10833 – 3 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Storage Temperature All Input Voltages except A9 with Respect to Ground VPP and A9 with Respect to Ground VCC Supply Voltage with Respect to Ground b 65 C to a 150 C ESD Protection All Output Voltages with Respect to Ground l 2000V VCC a 1 0V to GND b0 6V Operating Range b 0 6V to a 7V b 0 7V to a 14V b 0 6V to a 7V Range Comm’l Industrial Military Temperature 0 C to a 70 C b 40 C to a 85 C b 55 C to a 125 C VCC a 5V g 10% a 5V g 10% a 5V g 10% Read Operation DC Electrical Characteristics Over Operating Range with VPP e VCC Symbol VIL VIH VOL VOH ISB1 (Note 11) ISB2 ICC1 IPP VPP ILI ILO Parameter Input Low Level Input High Level Output Low Voltage Output High Voltage VCC Standby Current (CMOS) VCC Standby Current (TTL) VCC Active Current TTL Inputs VPP Supply Current VPP Read Voltage Input Load Current Output Leakage Current VIN e 5 5V or GND VOUT e 5 5V or GND IOL e 2 1 mA IOH e b2 5 mA CE e VCC g 0 3V CE e VIH CE e OE e VIL f e 5 MHz Inputs e VIH or VIL I O e 0 mA VPP e VCC VCC b 0 7 b1 b 10 Test Conditions Min b0 5 Max 08 VCC a 1 04 Units V V V V 20 35 100 1 35 10 VCC 1 10 mA mA mA mA V mA mA AC Electrical Characteristics Over Operating Range with VPP e VCC Symbol tACC tCE tOE tDF (Note 2) tOH (Note 2) Parameter Min Address to Output Delay CE to Output Delay OE to Output Delay Output Disable to Output Float Output Hold from Addresses CE or OE Whichever Occurred First 0 100 Max 100 100 50 30 Min 120 Max 120 120 50 35 Min 150 Max 150 150 50 45 Min 200 Max 200 200 50 55 ns Units 0 0 0 3 Capacitance TA e a 25 C Symbol CIN COUT Parameter Input Capacitance Output Capacitance f e 1 MHz (Note 2) Conditions VIN e 0V VOUT e 0V Typ 6 9 Max 12 12 Units pF pF AC Test Conditions Output Load Input Rise and Fall Times 1 TTL Gate and CL e 100 pF (Note 8) s 5 ns Input Pulse Levels Timing Measurement Reference Level Inputs Outputs 0 45 to 2 4V (Note 10) 0 8V and 2 0V 0 8V and 2 0V AC Waveforms (Notes 6 7 and 9) TL D 10833 – 4 Note 1 Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2 This parameter is only sampled and is not 100% tested Note 3 OE may be delayed up to tACC b tOE after the falling edge of CE without impacting tACC Note 4 The tDF and tCF compare level is determined as follows High to TRI-STATE the measured VOH1 (DC) b 0 10V Low to TRI-STATE the measured VOL1 (DC) a 0 10V Note 5 TRI-STATE may be attained using OE or CE Note 6 The power switching characteristics of EPROMs require careful device decoupling It is recommended that at least a 0 1 mF ceramic capacitor be used on every device between VCC and GND Note 7 The outputs must be restricted to VCC a 1 0V to avoid latch-up and device damage Note 8 TTL Gate IOL e 1 6 mA IOH e b 400 mA CL e 100 pF includes fixture capacitance Note 9 VPP may be connected to VCC except during programming Note 10 Inputs and outputs can undershoot to b 2 0V for 20 ns Max Note 11 CMOS inputs VIL e GND g 0 3V VIH e VCC g 0 3V 4 Programming Characteristics (Notes 1 Symbol tAS tOES tVPS tVCS tDS tAH tDH tDF tPW tOE IPP ICC TA VCC VPP tFR VIL VIH tIN tOUT Parameter Address Setup Time OE Setup Time VPP Setup Time VCC Setup Time Data Setup Time Address Hold Time Data Hold Time Output Enable to Output Float Delay Program Pulse Width Data Valid from OE VPP Supply Current during Programming Pulse VCC Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise Fall Time Input Low Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage 2 3 4 and 5) Conditions Min 1 1 1 1 1 0 1 CE e VIL 0 95 CE e VIL CE e VIL 100 60 105 100 30 50 20 60 12 5 5 00 24 08 08 40 20 20 0 45 25 6 25 12 75 30 65 13 0 Typ Max Units ms ms ms ms ms ms ms ns ms ns mA mA C V V ns V V V V Programming Waveforms (Note 3) TL D 10833 – 5 Note 1 National’s standard product warranty applies to devices programmed to specifications described herein Note 2 VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC Note 3 The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification At least a 0 1 mF capacitor is required across VPP VCC to GND to suppress spurious voltage transients which may damage the device Note 4 Programming and program verify are tested with the Fast Program Algorithm at typical power supply voltages and timings Note 5 During power up the PGM pin must be brought high ( t VIH) either coincident with or before power is applied to VPP 5 Fast Programming Algorithm Flow Chart TL D 10833 – 6 FIGURE 1 6 Functional Description DEVICE OPERATION The six modes of operation of the EPROM are listed in Table I It should be noted that all inputs for the six modes are at TTL levels The power supplies required are VCC and VPP The VPP power supply must be at 12 75V during the three programming modes and must be at 5V in the other three modes The VCC power supply must be at 6 25V during the three programming modes and at 5V in the other three modes Read Mode The EPROM has two control functions both of which must be logically active in order to obtain data at the outputs Chip Enable (CE PGM) is the power control and should be used for device selection Output Enable (OE) is the output control and should be used to gate data to the output pins independent of device selection Assuming that addresses are stable address access time (tACC) is equal to the delay from CE to output (tCE) Data is available at the outputs tOE after the falling edge of OE assuming that CE PGM has been low and addresses have been stable for at least tACC – tOE Standby Mode The EPROM has a standby mode which reduces the active power dissipation by over 99% from 385 mW to 0 55 mW The EPROM is placed in the standby mode by applying a CMOS high signal to the CE PGM input When in standby mode the outputs are in a high impedance state independent of the OE input Output Disable The EPROM is placed in output disable by applying a TTL high signal to the OE input When in output disable all circuitry is enabled except the outputs are in a high impedance state (TRI-STATE) Output OR-Typing Because the EPROM is usually used in larger memory arrays National has provided a 2-line control function that accommodates this use of multiple memory connections The 2-line control function allows for a) the lowest possible memory power dissipation and b) complete assurance that output bus contention will not occur To most efficiently use these two control lines it is recommended that CE PGM be decoded and used as the primary device selecting function while OE be made a common connection to all devices in the array and connected to the READ line from the system control bus This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device Programming CAUTION Exceeding 14V on pin 1 (VPP) will damage the EPROM Initially and after each erasure all bits of the EPROM are in the ‘‘1’s’’ state Data is introduced by selectively programming ‘‘0’s’’ into the desired bit locations Although only ‘‘0’s’’ will be programmed both ‘‘1’s’’ and ‘‘0’s’’ can be presented in the data word The only way to change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure The EPROM is in the programming mode when the VPP power supply is at 12 75V and OE is at VIH It is required that at least a 0 1 mF capacitor be placed across VPP VCC to ground to suppress spurious voltage transients which may damage the device The data to be programmed is applied 8 bits in parallel to the data output pins The levels required for the address and data inputs are TTL When the address and data are stable an active low TTL program pulse is applied to the CE PGM input A program pulse must be applied at each address location to be programmed The EPROM is programmed with the Fast Programming Algorithm shown in Figure 1 Each Address is programmed with a series of 100 ms pulses until it verifies good up to a maximum of 25 pulses Most memory cells will program with a single 100 ms pulse The EPROM must not be programmed with a DC signal applied to the CE PGM input Programming multiple EPROM in parallel with the same data can be easily accomplished due to the simplicity of the programming requirments Like inputs of the parallel EPROM may be connected together when they are programmed with the same data A low level TTL pulse applied to the CE PGM input programs the paralleled EPROM Program Inhibit Programming multiple EPROMs in parallel with different data is also easily accomplished Except for CE PGM all like inputs (including OE) of the parallel EPROMs may be common A TTL low level program pulse applied to an EPROM’s CE PGM input with VPP at 12 75V will program that EPROM A TTL high level CE PGM input inhibits the other EPROMs from being programmed 7 Functional Description (Continued) Program Verify A verify should be performed on the programmed bits to determine whether they were correctly programmed The verify may be performed with VPP at 12 75V VPP must be at VCC except during programming and program verify AFTER PROGRAMMING Opaque labels should be placed over the EPROM window to prevent unintentional erasure Covering the window will also prevent temporary functional failure due to the generation of photo currents MANUFACTURER’S IDENTIFICATION CODE The EPROM has a manufacturer’s identification code to aid in programming When the device is inserted in an EPROM programmer socket the programmer reads the code and then automatically calls up the specific programming algorithm for the part This automatic programming control is only possible with programmers which have the capability of reading the code The Manufacturer’s Identification code shown in Table II specifically identifies the manufacturer and device type The code for NM27C256 is ‘‘8F04’’ where ‘‘8F’’ designates that it is made by National Semiconductor and ‘‘04’’ designates a 256K part The code is accessed by applying 12V g 0 5V to address pin A9 Addresses A1–A8 A10–A16 and all control pins are held at VIL Address pin A0 is held at VIL for the manufacturer’s code and held at VIH for the device code The code is read on the eight data pins O0 – O7 Proper code access is only guaranteed at 25 C to g 5 C ERASURE CHARACTERISTICS The erasure characteristics of the device are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms ( ) It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 – 4000 range The recommended erasure procedure for the EPROM is exposure to short wave ultraviolet light which has a wavelength of 2537 The integrated dose (i e UV intensity c exposure time) for erasure should be a minimum of 15W-sec cm2 The EPROM should be placed within 1 inch of the lamp tubes during erasure Some lamps have a filter on their tubes which should be removed before erasure Table III shows the minimum EPROM erasure time for various light intensities An erasure system should be calibrated periodically The distance from lamp to device should be maintained at one inch The erasure time increases as the square of the distance from the lamp (if distance is doubled the erasure time increases by factor of 4) Lamps lose intensity as they age When a lamp is changed the distance has changed or the lamp has aged the system should be checked to make certain full erasure is occurring Incomplete erasure will cause symptoms that can be misleading Programmers components and even system designs have been erroneously suspected when incomplete erasure was the problem SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices The supply current ICC has three segments that are of interest to the system designer the standby current level the active current level and the transient current peaks that are produced by voltage transitions on input pins The magnitude of these transient current peaks is dependent of the output capacitance loading of the device The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors It is recommended that at least a 0 1 mF ceramic capacitor be used on every device between VCC and GND This should be a high frequency capacitor of low inherent inductance In addition at least a 4 7 mF bulk electrolytic capacitor should be used between VCC and GND for each eight devices The bulk capacitor should be located near where the power supply is connected to the array The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces 8 Mode Selection The modes of operation of NM27C256 listed in Table I A single 5V power supply is required in the read mode All inputs are TTL levels except for VPP and A9 for device signature TABLE I Modes Selection Pins Mode Read Output Disable Standby Programming Program Verify Program Inhibit Note 1 X can be VIL or VIH CE PGM VIL X (Note 1) VIH VIL VIH VIH OE VIL VIH X VIH VIL VIH VPP VCC VCC VCC 12 75V 12 75V 12 75V VCC 5 0V 5 0V 5 0V 6 25V 6 25V 6 25V Outputs DOUT High-Z High-Z DIN DOUT High-Z TABLE II Manufacturer’s Identification Code Pins Manufacturer Code Device Code A0 (10) VIL VIH A9 (24) 12V 12V O7 (19) 1 0 O6 (18) 0 0 O5 (17) 0 0 O4 (16) 0 0 O3 (15) 1 0 O2 (13) 1 1 O1 (12) 1 0 O0 (11) 1 0 Hex Data 8F 04 9 10 Physical Dimensions inches (millimeters) UV Window Cavity Dual-In-Line CerDIP Package (Q) Order Number NM27C256QXXX NS Package Number J28AQ 28-Lead Plastic One-Time-Programmable Dual-In-Line Package OrderNumber NM27C256NXXX NS Package Number N28B 11 NM27C256 262 144-Bit (32K x 8) High Performance CMOS EPROM Physical Dimensions inches (millimeters) (Continued) 32-Lead Plastic Leaded Chip Carrier (PLCC) Order Number NM27C256VXXX NS Package Number VA32A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 Semiconductor Drive P O Box 58090 Santa Clara CA 95052-8090 Tel 1(800) 272-9959 TWX (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str 10 D-82256 F4urstenfeldbruck Germany Tel (81-41) 35-0 Telex 527649 Fax (81-41) 35-1 National Semiconductor Japan Ltd Sumitomo Chemical Engineering Center Bldg 7F 1-7-1 Nakase Mihama-Ku Chiba-City Ciba Prefecture 261 Tel (043) 299-2300 Fax (043) 299-2500 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductores Do Brazil Ltda Rue Deputado Lacorda Franco 120-3A Sao Paulo-SP Brazil 05418-000 Tel (55-11) 212-5066 Telex 391-1131931 NSBR BR Fax (55-11) 212-1181 National Semiconductor (Australia) Pty Ltd Building 16 Business Park Drive Monash Business Park Nottinghill Melbourne Victoria 3168 Australia Tel (3) 558-9999 Fax (3) 558-9998 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications