NM93CS46MN

NM93CS06 CS46 CS56 CS66 (MICROWIRE Bus Interface) 256- 1024- 2048- 4096-Bit Serial EEPROM with Data Protect and Sequential Read August 1994 NM93CS06 CS46 CS56 CS66 (MICROWIRE TM Bus Interface) 256- 1024- 2048- 4096-Bit Serial EEPROM with Data Protect and Sequential Read General Description The NM93CS06 CS46 CS56 CS66 devices are 256 1024 2048 4096 bits respectively of CMOS non-volatile electrically erasable memory divided into 16 64 128 256 16-bit registers Selected registers can be protected against data modification by programming the Protect Register with the address of the first register to be protected against data modification (all registers greater than or equal to the selected address are then protected from further change) Additionally this address can be ‘‘locked’’ into the device making all future attempts to change data impossible These devices are fabricated using National Semiconductor floating-gate CMOS process for high reliability high endurance and low power consumption The NM93CSXX Family is offered in an SO package for small space considerations The EEPROM interfacing is MICROWIRE compatible providing simple interfacing to standard microcontrollers and microprocessors There are a total of 10 instructions 5 which operate on the EEPROM memory and 5 which operate on the Protect Register The memory instructions are READ WRITE WRITE ALL WRITE ENABLE and WRITE DISABLE The Protect register instructions are PRREAD PRWRITE PRENABLE PRCLEAR and PRDISABLE Features Y Y Y Y Y Y Y Y Y Y Y Y Write protection in a user defined section of memory Sequential register read Typical active current of 400 mA and standby current of 25 mA No erase required before write Reliable CMOS floating gate technology MICROWIRE compatible serial I O Self timed write cycle Device status during programming mode 40 year data retention Endurance 106 data changes 4 5V to 5 5V operation in all modes of operation Packages available 8-pin SO 8-pin DIP Block Diagram TL D 10750 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation MICROWIRETM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL D 10750 RRD-B30M75 Printed in U S A Connection Diagram Dual-In-Line Package (N) and 8-Pin SO (M8) CS SK DI DO GND TL D 10750–2 Pin Names Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Program Enable Protect Register Enable Power Supply PE PRE VCC Top View NS Package Number N08E and M08A Ordering Information Commercial Temp Range (0 C to a 70 C) Order Number NM93CS06N NM93CS46N NM93CS56N NM93CS66N NM93CS06M8 NM93CS46M8 NM93CS56M8 NM93CS66M8 Extended Temp Range (b40 C to a 85 C) Order Number NM93CS06EN NM93CS46EN NM93CS56EN NM93CS66EN NM93CS06EM8 NM93CS46EM8 NM93CS56EM8 NM93CS66EM8 Military Temp Range (b55 C to a 125 C) Order Number NM93CS06MN NM93CS46MN NM93CS56MN NM93CS66MN NM93CS06MM8 NM93CS46MM8 NM93CS56MM8 NM93CS66MM8 2 Absolute Maximum Ratings (Note 1) Operating Conditions Ambient Operating Temperature NM93CSxx NM93CSxxE NM93CSxxM Power Supply (VCC) 0 C to a 70 C b 40 C to a 85 C b 55 C to a 125 C 4 5V to 5 5V If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering 10 sec ) ESD rating b 65 C to a 150 C a 6 5V to b 0 3V a 300 C 2000V DC and AC Electrical Characteristics VCC e 4 5V to 5 5V unless otherwise specified Throughout this table ‘‘M’’ refers to temperature range ( b55 C to a 125 C) not package Symbol ICCA Parameter Operating Current Part Number NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M NM93CS06–NM93CS66 NM93CS06E–NM93CS06E NM93CS06M–NM93CS06M Conditions CS e VIH SK e 1 0 MHz SK e 1 0 MHz SK e 0 5 MHz CS e VIL Min Max 1 1 1 50 50 100 g b1 Units mA ICCS Standby Current mA IIL IOL VIL VIH VOL1 VOH1 VOL2 VOH2 fSK Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage SK Clock Frequency NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M VIN e 0V to VCC (Note 4) b0 1 mA V V V 2 IOL e 2 1 mA IOH e b400 mA IOL e 10 mA IOH e b10 mA (Note 5) 24 08 VCC a 1 04 02 VCC b 0 2 0 0 0 250 300 500 250 1 1 05 MHz tSKH SK High Time ns ns ns tSKL tSKS SK Low Time SK Setup Time SK Must Be at VIL for tSKS before CS goes high NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M NM93CS06-NM93CS66 NM93CS06E-NM93CS66E NM93CS06M–NM93CS66M NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M (Note 2) 50 50 100 250 250 500 100 50 50 100 70 50 50 100 100 100 200 0 tCS Minimum CS Low Time CS Setup Time PRE Setup Time ns ns ns ns ns tCSS tPRES tDH tPES DO Hold Time PE Setup Time tDIS DI Setup Time ns ns tCSH CS Hold Time 3 DC and AC Electrical Characteristics VCC e 4 5V to 5 5V unless otherwise specified (Continued) Symbol tPEH Parameter PE Hold Time Part Number NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M Conditions Min 250 250 500 50 20 NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M NM93CS06–NM93CS66 NM93CS06E–NM93CS66E NM93CS06M–NM93CS66M CS e VIL 500 500 1000 500 500 1000 500 500 1000 100 100 200 10 Max Units ns ns ns ns tPREH tDIH tPD1 PRE Hold Time DI Hold Time Output Delay to ‘‘1’’ tPD0 Output Delay to ‘‘0’’ ns tSV CS to Status Valid ns tDF CS to DO in TRI-STATE Write Cycle Time ns ms tWP Capacitance (Note 3) TA e 25 C f e 1 MHz Symbol COUT CIN Test Output Capacitance Input Capacitance Typ Max 5 5 Units pF pF Note 1 Stress ratings above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device This is a stress rating only and operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2 CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle (this is shown in the opcode diagrams in the following pages) Note 3 This parameter is periodically sampled and not 100% tested Note 4 Typical leakage values are in the 20 nA range Note 5 The shortest allowable SK clock period e 1 fSK (as shown under the fSK parameter) Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet Within this SK period both tSKH and tSKL limits must be observed Therefore it is not allowable to set 1 fSK e tSKH (minimum) a tSKL (minimum) for shorter SK cycle time operation AC Test Conditions VCC Range 4 5V s VCC s 5 5V (TTL Levels) VIL VIH Input Levels 0 4V 2 4V VIL VIH Timing Level 1 0V 2 0V Output Load 1 TTL Gate (CL e 100 pF) VOL VOH Timing Level 0 4V 2 4V IOL IOH b 2 1 mA 0 4 mA 4 Functional Description The NM93CSxx EEPROM Family has 10 instructions as described below All Data-In signals are clocked into the device on the low-to-high SK transition Read and Sequential Register Read (READ) The READ instruction outputs serial data on the D0 pin After a READ instruction is received the instruction and address are decoded followed by data transfer from the selected memory register into a 16-bit serial-out shift register A dummy bit (logical 0) precedes the 16-bit data output string Output data changes are initiated by a low to high transition of the SK clock In the sequential register read mode of operation the memory automatically cycles to the next register after each 16 data bits are clocked out The dummy-bit is suppressed in this mode and a continuous string of data is obtained Write Enable (WEN) When VCC is applied to the part it ‘‘powers up’’ in the Write Disable (WDS) state Therefore all programming modes must be preceded by a Write Enable (WEN) instruction Once a Write Enable instruction is executed programming remains enabled until a Write Disable (WDS) instruction is executed or VCC is completely removed from the part Write (WRITE) The WRITE instruction is followed by 16 bits of data to be written into the specified address After the last bit of data is put on the data-in (DI) pin CS must be brought low before the next rising edge of the SK clock This falling edge of the CS initiates the self-timed programming cycle The PE pin MUST be held high while loading the WRITE instruction however after loading the WRITE instruction the PE pin becomes a ‘‘don’t care’’ The D0 pin indicates the READY BUSY status of the chip if CS is brought high after the tCS interval D0 e logical 0 indicates that programming is still in progress D0 e logical 1 indicates that the register at the address specified in the instruction has been written with the data pattern specified in the instruction and the part is ready for another instruction Write All (WRALL) The WRALL instruction is valid only when the Protect Register has been cleared by executing a PRCLEAR instruction The WRALL instruction will simultaneously program all registers with the data pattern specified in the instruction Like the WRITE instruction the PE pin MUST be held high while loading the WRALL instruction however after loading the instruction the PE pin becomes a ‘‘don’t care’’ As in the WRITE mode the DO pin indicates the READY BUSY status of the chip if CS is brought high after the tCS interval This function is DISABLED if the Protect Register is in use to lock out a section of memory Write Disable (WDS) To protect against accidental data disturb the Write Disable (WDS) instruction disables all programming modes and should follow all programming operations Execution of a READ instruction is independent of both the WEN and WDS instructions Note For all Protect Register Operations If the PRE pin is not held at VIH all instructions will be applied to the EEPROM array rather than the Protect Register Protect Register Read (PRREAD) The PRREAD instruction outputs the address stored in the Protect Register on the DO pin The PRE pin MUST be held high while loading the instruction sequence Following the PRREAD instruction the 6- or 8-bit address stored in the memory protect register is transferred to the serial out shift register As in the READ mode a dummy bit (logical 0) precedes the 6- or 8-bit address string Protect Register Enable (PREN) The PREN instruction is used to enable the PRCLEAR PRWRITE and PRDS modes Before the PREN mode can be entered the part must be in the Write Enable (WEN) mode Both the PRE and PE pins MUST be held high while loading the instruction sequence Note that a PREN instruction must immediately precede a PRCLEAR PRWRITE or PRDS instruction Protect Register Clear (PRCLEAR) The PRCLEAR instruction clears the address stored in the Protect Register and therefore enables all registers for the WRITE and WRALL instruction The PRE and PE pins must be held high while loading the instruction sequence however after loading the PRCLEAR instruction the PRE and PE pins become ‘‘don’t care’’ Note that a PREN instruction must immediately precede a PRCLEAR instruction Please note that the PRCLEAR instruction and the PRWRITE instruction will both program the Protect Register with all 1s However the PRCLEAR instruction will allow the LAST register to be programmed whereas the PRWRITE instruction e all 1s will PREVENT the last register from being programmed In addition the PRCLEAR instruction will allow the use of the WRALL command where the PRWRITE e all 1s will lock out the Bulk programming opcode Protect Register Write (PRWRITE) The PRWRITE instruction is used to write into the Protect Register the address of the first register to be protected After the PRWRITE instruction is executed all memory registers whose addresses are greater than or equal to the address specified in the Protect Register are protected from the WRITE operation Note that before executing a PRWRITE instruction the Protect Register must first be cleared by executing a PRCLEAR operation and that the PRE and PE pins must be held high while loading the instruction however after loading the PRWRITE instruction the PRE and PE pins become ‘don’t care’ Note that a PREN instruction must immediately precede a PRWRITE instruction Protect Register Disable (PRDS) The PRDS instruction is a ONE TIME ONLY instruction which renders the Protect Register unalterable in the future Therefore the specified registers become PERMANENTLY protected against data changes As in the PRWRITE instruction the PRE and PE pins must be held high while loading the instruction and after loading the PRDS instruction the PRE and PE pins become ‘‘don’t care’’ Note that a PREN instruction must immediately precede a PRDS instruction 5 Instruction Set for the NM93CS06 and NM93CS46 Instruction READ WEN WRITE WRALL WDS PRREAD PREN PRCLEAR PRWRITE SB 1 1 1 1 1 1 1 1 1 Op Code 10 00 01 00 00 10 00 11 01 Address A5–A0 11XXXX A5–A0 01XXXX 00XXXX XXXXXX 11XXXX 111111 A5–A0 D15–D0 D15–D0 Data PRE 0 0 0 0 0 1 1 1 1 PE X 1 1 1 X X 1 1 1 Comments Reads data stored in memory starting at specified address Enable all programming modes Writes address if unprotected Writes all registers Valid only when Protect Register is cleared Disables all programming modes Reads address stored in Protect Register Must immediately precede PRCLEAR PRWRITE and PRDS instructions Clears the Protect Register so that no registers are protected from WRITE Programs address into Protect Register Thereafter memory addresses t the address in Protect Register are protected from WRITE ONE TIME ONLY instruction after which the address in the Protect Register cannot be altered PRDS 1 00 000000 1 1 Note Address bits A5 and A4 become ‘‘Don’t Care’’ for the NM93CS06 Instruction Set for the NM93CS56 and NM93CS66 Instruction READ WEN WRITE WRALL WDS PRREAD PREN PRCLEAR PRWRITE SB 1 1 1 1 1 1 1 1 1 Op Code 10 00 01 00 00 10 00 11 01 Address A7–A0 11XXXXXX A7–A0 01XXXXXX 00XXXXXX XXXXXXXX 11XXXXXX 11111111 A7–A0 D15–D0 D15–D0 Data PRE 0 0 0 0 0 1 1 1 1 PE X 1 1 1 X X 1 1 1 Comments Reads data stored in memory starting at specified address Enable all programming modes Writes address if unprotected Writes all registers Valid only when Protect Register is cleared Disables all programming modes Reads address stored in Protect Register Must immediately precede PRCLEAR PRWRITE and PRDS instructions Clears the ‘‘protect register’’ so that no registers are protected from WRITE Programs address into Protect Register Thereafter memory addresses t the address in Protect Register are protected from WRITE ONE TIME ONLY instruction after which the address in the Protect Register cannot be altered PRDS 1 00 00000000 1 1 Note Address bit A7 becomes ‘‘Don’t Care’’ for the NM93CS56 6 Timing Diagrams Synchronous Data Timing TL D 10750 – 15 READ PRE e 0 PE e X The memory automatically cycles to the next register with continued clocking of SK TL D 10750 – 4 7 Timing Diagrams (Continued) WEN PRE e 0 D0 e TRI-STATE TL D 10750 – 5 WDS PRE e 0 PE e X DO e TRI-STATE TL D 10750 – 6 WRITE PRE e 0 TL D 10750 – 7 8 Timing Diagrams (Continued) WRALL PRE e 0 (PROTECT REGISTER MUST BE CLEARED) TL D 10750 – 8 PRREAD PE e X TL D 10750 – 9 9 Timing Diagrams (Continued) PREN D0 e TRI-STATE (A WEN CYCLE MUST PRECEDE A PREN CYCLE) TL D 10750 – 10 PRCLEAR (A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRCLEAR CYCLE) TL D 10750 – 11 10 Timing Diagrams (Continued) PRWRITE (PREN CYCLES MUST IMMEDIATELY PRECEDE A PRWRITE CYCLE ) TL D 10750 – 12 PRDS ( ONE TIME ONLY INSTRUCTION A PREN CYCLE MUST IMMEDIATELY PRECEDE A PRDS CYCLE ) TL D 10750 – 13 11 12 Physical Dimensions inches (millimeters) Molded Package Small Outline 0 15 Wide 8-Lead (M8) Order Number NM93CS06M8 NM93CS46M8 or NM93CS56M8 NS Package Number M08A 13 NM93CS06 CS46 CS56 CS66 (MICROWIRE Bus Interface) 256- 1024- 2048- 4096-Bit Serial EEPROM with Data Protect and Sequential Read Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number NM93CS06N NM93CS46N NM93CS56 or NM93CS66N NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor 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