NMC27C32BQ

NMC27C32B 32 768-Bit (4096 x 8) CMOS EPROM December 1996 NMC27C32B 32 768-Bit (4096 x 8) CMOS EPROM General Description The NMC27C32B is a 32k UV erasable and electrically reprogrammable CMOS EPROM ideally suited for applications where fast turnaround pattern experimentation and low power consumption are important requirements The NMC27C32B is designed to operate with a single a 5V power supply with g 10% tolerance The NMC27C32B is packaged in a 24-pin dual-in-line package with a quartz window The quartz window allows the user to expose the chip to ultraviolet light to erase the bit pattern A new pattern can then be written electrically into the device by following the programming procedure This EPROM is fabricated with National’s proprietary time proven CMOS double-poly silicon gate technology which combines high performance and high density with low power consumption and excellent reliability Features Y Y Y Y Y Y Y Y Low CMOS power consumption Active Power 55 mW Max Standby Power 0 55 mW Max Extended temperature range b40 C to a 85 C Fast and reliable programming TTL CMOS compatible inputs outputs TRI-STATE output Manufacturer’s identification code for automatic programming High current CMOS level output drivers Compatible with NMOS 2732 Block Diagram Pin Names A0 – A11 CE OE VPP O0 –O7 VCC GND Addresses Chip Enable Output Enable Programming Voltage Outputs Power Supply Ground TL D 8827 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1996 National Semiconductor Corporation TL D 8827 RRD-B30M17 Printed in U S A http www national com Connection Diagram 27C256 27256 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 27C128 27128 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND 27C64 2764 VPP A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2 GND TL D 8827 – 2 27C16 2716 NMC27C32B Dual-In-Line Package 27C16 2716 27C64 2764 VCC PGM 27C128 27128 VCC PGM A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 27C256 27256 VCC A14 A13 A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 VCC A8 A9 VPP OE A10 CE O7 O6 O5 O4 O3 NC A8 A9 A11 OE A10 CE O7 O6 O5 O4 O3 Note Socket compatible EPROM pin configurations are shown in the blocks adjacent to the NMC27C32B pins Order Number NMC27C32BQ See NS Package Number J24AQ Commercial Temp Range (0 C to a 70 C) VCC e 5V g 10% Parameter Order Number NMC27C32BQ150 NMC27C32BQ200 NMC27C32BQ250 Access Time (ns) 150 200 250 Extended Temp Range (b40 C to a 85 C) VCC e 5V g 10% Parameter Order Number NMC27C32BQE200 Access Time (ns) 200 http www national com 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Temperature Under Bias Storage Temperature VCC Supply Voltage with Respect to Ground All Input Voltages except A9 and OE VPP with Respect to Ground (Note 9) All Output Voltages with Respect to Ground (Note 9) b 40 C to a 85 C b 65 C to a 150 C a 7 0V to b 0 6V OE VPP Supply and A9 Voltage with Respect to Ground Power Dissipation Lead Temperature (Soldering 10 sec ) a 14 0V to b 0 6V 1 0W 300 C Operating Conditions (Note 6) Temperature Range NMC27C32BQ150 200 250 NMC27C32BQE200 VCC Power Supply 0 C to a 70 C b 40 C to a 85 C a 5V g 10% a 6 5V to b 0 6V VCC a 1 0V to GNDb0 6V READ OPERATION DC Electrical Characteristics Symbol ILI IPP ILO ICC1 ICC2 ICCSB1 ICCSB2 VIL VIH VOL1 VOH1 VOL2 VOH2 Parameter Input Load Current OE VPP Load Current Output Leakage Current VCC Current (Active) TTL Inputs VCC Current (Active) CMOS Inputs VCC Current (Standby) TTL Inputs VCC Current (Standby) CMOS Inputs Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage IOL e 2 1 mA IOH e b400 mA IOL e 10 mA IOH e b10 mA VCC b 0 1 24 01 Conditions VIN e VCC or GND OE VPP e VCC or GND VOUT e VCC or GND CE e VIH CE e VIL f e 5 MHz Inputs e VIH or VIL I O e 0 mA CE e GND f e 5 MHz Inputs e VCC or GND I O e 0 mA CE e VIH CE e VCC b0 2 Min Typ 0 01 Max 1 10 Units mA mA mA mA mA mA mA V V V V V V 0 01 5 3 01 05 1 20 10 1 100 08 VCC a 1 0 45 20 AC Electrical Characteristics NMC27C32B Symbol Parameter Conditions Q150 Min tACC tCE tOE tDF tCF tOH Address to Output Delay CE to Output Delay OE to Output Delay OE High to Output Float CE High to Output Float Output Hold from Addresses CE or OE Whichever Occurred First CE e OE e VIL OE e VIL CE e VIL CE e VIL OE e VIL CE e OE e VIL 0 0 0 ns 0 0 Max 150 150 60 50 50 0 0 Q200 QE200 Min Max 200 200 60 60 60 0 0 Min Q250 Max 250 250 70 70 60 ns ns ns ns ns Units 3 http www national com Capacitance TA e a 25 C Symbol CIN1 CIN2 COUT Parameter f e 1 MHz (Note 2) Conditions Typ Max Units 6 16 9 12 20 12 pF pF pF Input Capacitance except OE VPP VIN e 0V OE VPP Input Capacitance Output Capacitance VIN e 0V VOUT e 0V AC Test Conditions Output Load Input Rise and Fall Times Input Pulse Levels 1 TTL Gate and CL e 100 pF (Note 8) s 5 ns 0 45V to 2 4V Timing Measurement Reference Level Inputs Outputs 0 8V and 2V 0 8V and 2V AC Waveforms (Note 7) TL D 8827 – 3 Note 1 Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note 2 This parameter is only sampled and is not 100% tested Note 3 OE may be delayed up to tACC b tOE after the falling edge of CE without impacting tACC Note 4 The tDF and tCF compare level is determined as follows High to TRI-STATE the measured VOH1 (DC) b 0 10V Low to TRI-STATE the measured VOL1 (DC) a 0 10V Note 5 TRI-STATE may be attained using OE or CE Note 6 The power switching characteristics of EPROMs require careful device decoupling It is recommended that at least a 0 1 mF ceramic capacitor be used on every device between VCC and GND Note 7 The outputs must be restricted to VCC a 1 0V to avoid latch-up and device damage Note 8 1 TTL Gate IOL e 1 6 mA IOH e b 400 mA CL 100 pF includes fixture capacitance Note 9 Inputs and outputs can undershoot to b 2 0V for 20 ns Max except for OE VPP which cannot exceed b 0 2V Note 10 Typical values are for TA e 25 C and nominal supply voltages http www national com 4 Programming Characteristics (Notes 1 Symbol tAS tOES tDS tVCS tAH tDH tCF tPW tOEH tDV tPRT tVR IPP ICC TA VCC VPP tFR VIL VIH tIN tOUT Parameter Address Setup Time OE Setup Time Data Setup Time VCC Setup Time Address Hold Time Data Hold Time Chip Enable to Output Float Delay Program Pulse Width OE Hold Time Data Valid from CE OE Pulse Rise Time During Programming VPP Recovery Time VPP Supply Current During Programming Pulse VCC Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise Fall Time Input Low Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage 23 4) Min 1 1 1 1 0 1 Typ Max Units ms ms ms ms ms ms 60 100 105 250 50 1 ns ms ms ns ns ms 30 10 20 60 12 5 5 00 24 08 08 40 20 20 0 45 25 6 25 12 75 30 65 13 0 mA mA C V V ns V V V V Conditions OE e VIL 0 95 1 OE e VIL CE e VIL OE e VPP Programming Waveforms TL D 8827 – 4 Note 1 National’s standard product warranty applies only to devices programmed to specifications described herein Note 2 VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP The EPROM must not be inserted into or removed from a board with voltage applied to VPP or VCC Note 3 The maximum absolute allowable voltage which may be applied to the VPP pin during programming is 14V Care must be taken when switching the VPP supply to prevent any overshoot from exceeding this 14V maximum specification At least a 0 1 mF capacitor is required across VCC to GND to suppress spurious voltage transients which may damage the device Note 4 Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings 5 http www national com Fast Programming Algorithm Flow Chart (Note 4) TL D 8827 – 5 FIGURE 1 http www national com 6 Functional Description DEVICE OPERATION The six modes of operation of the NMC27C32B are listed in Table I A single 5V power supply is required in the read mode All inputs are TTL levels except for OE VPP during programming In the program mode the OE VPP input is pulsed from a TTL low level to 12 75V Read Mode The NMC27C32B has two control functions both of which must be logically active in order to obtain data at the outputs Chip Enable (CE) is the power control and should be used for device selection Output Enable (OE) is the output control and should be used to gate data to the output pins independent of device selection Assuming that addresses are stable address access time (tACC) is equal to the delay from CE to output (tCE) Data is available at the outputs tOE after the falling edge of OE assuming that CE has been low and addresses have been stable for at least tACC – tOE The sense amps are clocked for fast access time VCC should therefore be maintained at operating voltage during read and verify If VCC temporarily drops below the spec voltage (but not to ground) an address transition must be performed after the drop to ensure proper output data Standby Mode The NMC27C32B has a standby mode which reduces the active power dissipation by 99% from 55 mW to 0 55 mW The NMC27C32B is placed in the standby mode by applying a CMOS high signal to the CE input When in standby mode the outputs are in a high impedance state independent of the OE input Output OR-Tying Because EPROMs are usually used in larger memory arrays National has provided a 2-line control function that accommodates this use of multiple memory connection The 2-line control function allows for a The lowest possible memory power dissipation and b complete assurance that output bus contention will not occur To most efficiently use these two control lines it is recommended that CE (pin 18) be decoded and used as the primary device selecting function while OE (pin 20) be made a common connection to all devices in the array and connected to the READ line from the system control bus This assures that all deselected memory devices are in their low power standby modes and that the output pins are active only when data is desired from a particular memory device Programming CAUTION Exceeding 14V on pin 20 OE VPP will damage the NMC27C32B Initially and after each erasure all bits of the NMC27C32B are in the ‘‘1’’ state Data is introduced by selectively programming ‘‘0s’’ into the desired bit locations Although only ‘‘0s’’ will be programmed both ‘‘1s’’ and ‘‘0s’’ can be presented in the data word The only way to change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure The NMC27C32B is in the programming mode when OE VPP is at 12 75V It is required that at least a 0 1 mF capacitor be placed across VCC and ground to suppress spurious voltage transients which may damage the device The data to be programmed is applied 8 bits in parallel to the data output pins The levels required for the address and data inputs are TTL When the address and data are stable an active low TTL program pulse is applied to the CE input A program pulse must be applied at each address location to be programmed The NMC27C32B is programmed with the Fast Programming Algorithm shown in Figure 1 Each Address is programmed with a series of 100 ms pulses until it verifies good up to a maximum of 25 pulses Most memory cells will Program with a single 100 ms pulse Note Some programmer manufactures due to equipment limitation may offer interactive program Algorithm (Shown in Figure 2 ) The NMC27C32B must not be programmed with a DC signal applied to the CE input Programming multiple NMC27C32Bs in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements Like inputs of the paralleled NMC27C32B may be connected together when they are programmed with the same data A low level TTL pulse applied to the CE input programs the paralleled NMC27C32B TABLE I Mode Selection Pins Mode Read Standby Program Program Verify Program Inhibit Output Disable CE (18) VIL VIH VIL VIL VIH Don’t Care OE VPP (20) VIL Don’t Care 12 75V VIL 12 75V VIH VCC (24) 5V 5V 6 25V 6 25V 6 25V 5V Outputs (9 – 11 13 – 17) DOUT Hi-Z DIN DOUT Hi-Z Hi-Z 7 http www national com Functional Description (Continued) Program Inhibit Programming multiple NMC27C32B in parallel with different data is also easily accomplished Except for CE all like inputs (including OE) of the parallel NMC27C32B may be common A TTL low level program pulse applied to an NMC27C32B’s CE input with OE VPP at 12 75V will program that NMC27C32B A TTL high level CE input inhibits the other NMC27C32B from being programmed Program Verify A verify should be performed on the programmed bit to determine whether they were correctly programmed The verify is accomplished with OE VPP and CE at VIL Data should be verified tDV after the falling edge of CE MANUFACTURER’S IDENTIFICATION CODE The NMC27C32B has a manufacturer’s identification code to aid in programming The code shown in Table II is two bytes wide and is stored in a ROM configuration on the chip It identifies the manufacturer and the device type The code for the NMC27C32B is ‘‘8F01’’ where ‘‘8F’’ designates that it is made by National Semiconductor and ‘‘01’’ designates a 32k part The code is accessed by applying 12 0V g 0 5V to address pin A9 Addresses A1–A8 A10–A11 CE and OE are held at VIL Address A0 is held at VIL for the manufacturer’s code and at VIH for the device code The code is read out on the 8 data pins Proper code access is only guaranteed at 25 C g 5 C The primary purpose of the manufacturer’s identification code is automatic programming control When the device is inserted in an EPROM programmer socket the programmer reads the code and then automatically calls up the specific programming algorithm for the part This automatic programming control is only possible with programmers which have the capability of reading the code ERASURE CHARACTERISTICS The erasure characteristics of the NMC27C32B are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms ( ) It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 – 4000 range After programming opaque labels should be placed over the NMC27C32B’s window to prevent unintentional erasure Covering the window will also prevent temporary functional failure due to the generation of photo currents The recommended erasure procedure for the NMC27C32B is exposure to short wave ultraviolet light which has a wavelength of 2537 The integrated dose (i e UV intensity c exposure time) for erasure should be a minimum of 15 W-sec cm2 The NMC27C32B should be placed within 1 inch of the lamp tubes during erasure Some lamps have a filter on their tubes which should be removed before erasure Table III shows the minimum NMC27C32B erasure time for various light intensities An erasure system should be calibrated periodically The distance from lamp to unit should be maintained at one inch The erasure time increases as the square of the distance (If distance is doubled the erasure time increases by a factor of 4 ) Lamps lose intensity as they age When a lamp is changed the distance has changed or the lamp has aged the system should be checked to make certain full erasure is occurring Incomplete erasure will cause symptoms that can be misleading Programmers components and even system designs have been erroneously suspected when incomplete erasure was the problem SYSTEM CONSIDERATION The power switching characteristics of EPROMs require careful decoupling of the devices The supply current ICC has three segments that are of interest to the system designer the standby current level the active current level and the transient current peaks that are produced by voltage transitions on input pins The magnitude of these transient current peaks is dependent on the output capacitance loading of the device The associated VCC transient voltage peaks can be suppressed by properly selected decoupling capacitors It is recommended that at least a 0 1 mF ceramic capacitor be used on every device between VCC and GND This should be a high frequency capacitor of low inherent inductance In addition at least a 4 7 mF bulk electrolytic capacitor should be used between VCC and GND for each eight devices The bulk capacitor should be located near where the power supply is connected to the array The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of the PC board traces TABLE II Manufacturer’s Identification Code Pins Manufacturer Code Device Code A0 (8) VIL VIH O7 (17) 1 0 O6 (16) 0 0 O5 (15) 0 0 O4 (14) 0 0 O3 (13) 1 0 O2 (11) 1 0 O1 (10) 1 0 O0 (9) 1 1 Hex Data 8F 01 TABLE III Minimum NMC27C32B Erasure Time Light Intensity (mW cm2) 15 000 10 000 5 000 Erasure Time (Minutes) 20 25 50 http www national com 8 9 http www national com NMC27C32B 32 768-Bit (4096 x 8) CMOS EPROM Physical Dimensions inches (millimeters) unless otherwise noted UV Window Cavity Dual-In-Line Cerdip Package (JQ) Order Number NMC27C32BQ NS Package Number J24AQ LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation Americas Tel 1(800) 272-9959 Fax 1(800) 737-7018 Email support nsc com 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness http www national com National Semiconductor Europe Fax a49 (0) 180-530 85 86 Email europe support nsc com Deutsch Tel a49 (0) 180-530 85 85 English Tel a49 (0) 180-532 78 32 Fran ais Tel a49 (0) 180-532 93 58 Italiano Tel a49 (0) 180-534 16 80 National Semiconductor Southeast Asia Fax (852) 2376 3901 Email sea support nsc com National Semiconductor Japan Ltd Tel 81-3-5620-7561 Fax 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications