NS486SXF

NS486SXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems ADVANCE INFORMATION February 1997 NS486 TM SXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems General Description The NS486SXF is a highly integrated embedded system controller incorporating an Intel486TM -class 32-bit processor all of the necessary System Service Elements and a set of peripheral I O controllers tailored for embedded control systems It is ideally suited for a wide variety of applications running in a segmented protect-mode environment Y Y Y Y Y Y Y Key Features Y Y Y Y Y Y 100% compatible with VxWorks VRTX QNX Neutrino pSOS a TM and other popular real-time executives and operating system kernels Intel486 instruction set compatible (protected mode only) with optimized performance CPU includes a 1 Kbyte Instruction Cache Operation at 25 MHz with 5V supply Low cost 160-pin PQFP package Industry standard interrupt controller timers real time clock UART with IrDA v1 0 (Infrared Data Association) port Y Y Y Y Y Intel 82365 compatible PCMCIA interface Protected WATCHDOGTM timer Optimized DRAM Controller (supports two banks up to 8 Mbytes each) Up to nine versatile programmable chip selects Glueless interface to ISA peripherals Arbitration support for auxiliary processor Four external DMA channels (max transfer rate of 25 MByte sec 25 MHz) support many transfer modes High performance IEEE 1284 (ECP) Bidirectional Parallel Port MICROWIRETM Access bus synchronous serial interfaces LCD Controller for an up to 4 grey scale supertwist Liquid Crystal Displays up to 480 X 320 Reconfigurable I O Up to 29 I O pins can be used as general purpose bidirectional I O lines Flexible programmable multilevel power saving modes maximize power savings NS486SXF Single-Chip Embedded Controller TL EE 12514 – 1 TRI-STATE is a registered trademark of National Semiconductor Corporation NS486TM WATCHDOGTM and MICROWIRETM are trademarks of National Semiconductor Corporation Intel486TM is a trademark of Intel Corporation QNX is a registered trademark of QNX Software Systems Inc VRTX is a registered trademark of Microtec Research Inc VxWorks is a registered trademark of Wind River Systems Inc pSOS a TM is a trademark of Integrated Systems Inc PowerPack is a registered trademark of Microtek International C1996 National Semiconductor Corporation TL EE12514 RRD-B30M27 Printed in U S A http www national com Table of Contents 1 0 SYSTEM OVERVIEW 1 1 NS486SXF System Overview 1 2 32-bit Processor Core 1 3 System Service Elements 1 3 1 DRAM Controller 1 3 2 DMA Controller 1 3 3 Programmable Interval Timer 1 3 4 WATCHDOG Timer 1 3 5 Interrupt Controller 1 3 6 Real Time Clock Calendar 1 3 7 Power Management Features 1 4 NS486SXF System Bus 1 5 Other On-board Peripherals 1 5 1 Reconfigurable I O Lines 1 5 2 IEEE 1284 Bidirectional Port 1 5 3 PCMCIA Interface 1 5 4 MICROWIRE Access bus Interface 1 5 5 UART Serial Port 1 5 6 LCD Controller 1 6 ICE Support 1 7 Other Issues 2 0 PIN DESCRIPTION TABLES 3 0 DEVICE SPECIFICATIONS 3 1 DC Electrical Specifications 5V g 5% 3 1 1 Recommended Operating Conditions 3 1 2 Absolute Maximum Ratings (Notes 2 and 3) 3 1 3 Capacitance TA e 25 C f e 1 MHz 3 1 4 DC Characteristics 3 2 General AC Specifications 3 2 1 Power Ramp Times 3 2 2 PWRGOOD and Power Rampdown Timing 3 3 AC Switching Specifications 3 3 1 DRAM Interface Timing Specification 3 3 2 ISA-like Bus Cycles Timing Specification 3 3 3 Ready Feedback Timing Specifications 3 3 4 OSCX1 AC Specification 3 3 5 Peripheral Timing Specifications 3 4 Physical Description http www national com 2 List of Figures FIGURE 1-1 FIGURE 1-2 FIGURE 2-1 FIGURE 3-1 FIGURE 3-2 FIGURE 3-3 FIGURE 3-4 FIGURE 3-5 FIGURE 3-6 FIGURE 3-7 FIGURE 3-8 FIGURE 3-9 FIGURE 3-10 FIGURE 3-11 FIGURE 3-12 FIGURE 3-13 FIGURE 3-14 FIGURE 3-15 FIGURE 3-16 FIGURE 3-17 FIGURE 3-18 FIGURE 3-19 FIGURE 3-20 FIGURE 3-21 FIGURE 3-22 NS486SXF Internal Resource to Pins Map NS486SXF Internal Busses NS486SXF Package Pinout Diagram Switching Characteristic Measurement Waveforms More Switching Specifications Power Supply Rise and Fall PWGOOD in relation to VDD DRAM Timing Diagram ISA-like Bus Timing Diagram Ready Feedback Timing Diagram TTL Clock Input Timing Diagram DMA Controller Read Timing Diagram DMA Controller Write Timing Diagram PIC Timing Diagram Memory Read Timing Memory Write Timing Diagram I O Read Timing I O Write Timing Diagram Access bus Timing Diagram UART Baud Rate and Infrared Clocks UART IRQ Timing UART Modem Control Timing LCD Controller Timing Diagram Testmode Timing Diagram Plastic Package Specifications 3 http www national com List of Tables TABLE 2-1 TABLE 2-2 TABLE 2-3 TABLE 2-4 TABLE 2-5 TABLE 2-6 TABLE 2-7 TABLE 2-8 TABLE 2-9 TABLE 2-10 TABLE 2-11 TABLE 2-12 TABLE 2-13 TABLE 2-14 TABLE 2-15 TABLE 2-16 TABLE 2-17 TABLE 2-18 TABLE 3-1 TABLE 3-2 TABLE 3-3 TABLE 3-4 TABLE 3-5 TABLE 3-6 TABLE 3-7 TABLE 3-8 TABLE 3-9 TABLE 3-10 TABLE 3-11 TABLE 3-12 TABLE 3-13 TABLE 3-14 TABLE 3-15 TABLE 3-16 TABLE 3-17 TABLE 3-18 Bus Interface Unit Pins DMA Control Pins DRAM Control Pins Power Pins Reset Logic Pins Auxiliary Processor Interface Pins Test Pins Interrupt Control Pins Real Time Clock Pins LCD Interface Pins Oscillator Pins HP-SIR UART Pins PCMCIA pins IEEE-1284 Port (ECP Mode) Timer Pins 3-Wire Serial I O Pins General Purpose Chip Select Pins Summary of Reconfigurable I O Pins VDD Rise and Fall Times VDD Rampdown vs PWRGOOD 4 Cycle Page Miss Preliminary Specifications 3 Cycle Miss Preliminary Specifications No Command Delay ISA-like Bus Specifications One Programmed Command Delay ISA-like Bus Specifications Ready Signal Timing Specifications TTL Clock Input Specification DMA Controller Specifications PIC Timing Specifications Parallel Port Compatibility Mode Handshake Timing Values Parallel Port IEEE 1284 Mode Handshake Timing Values PCMCIA Memory Read Timing Specifications Memory Write Timing PCMCIA I O Read Specifications PCMCIA I O Write Specifications Access Bus Timing Specifications LCD Controller Timing Specifications http www national com 4 1 0 System Overview 1 1 NS486SXF SYSTEM OVERVIEW The NS486SXF is a highly integrated embedded system controller It includes an Intel486-class 32-bit processor all resources required for the System Service Elements of a Real-Time Executive and a generous set of peripherals This ‘‘system-on-a-chip’’ is ideal for implementing a wide variety of embedded applications These include (but are not limited to) fax machines multifunction peripherals (fax scanners printers) mobile companions (both organizer and communicator) television set-top boxes and telephones (mobile and desktop) The 32-bit processor core executes all of the Intel486 instructions with a similar number of clocks per instruction An on-board 1 kbyte instruction cache provides for efficient execution from ROM Intel486 debug features are supported The processor has been optimized for operating system kernels such as VRTX VxWorks pSOS a and QNX These environments only need the ‘486 protected mode operation (no real mode or virtual 8086 support) flat or linear memory addressing (no virtual memory paging) and floating point execution in software only (no co-processor interface) In fact the NS486SXF includes all of the System Service Elements required by a typical kernel including an efficient DRAM controller that supports page-mode DRAMs for data cache-like performance a six-channel DMA controller with two channels supporting data transfers from on-chip peripherals (the IEEE 1284 ECP or Extended Capabilities Port and the LCD controller) and four channels supporting external devices such as scanners and print engines three timer channels (including one configured as a protected WATCHDOG Timer) two programmable 8259 interrupt controllers provide 15 on-chip interrupt sources an industry standard real time clock and calendar (RTC) with battery backup and support for comprehensive power management schemes In addition the NS486SXF also incorporates the key I O peripherals required for implementing a wide variety of embedded applications an IEEE 1284 Bidirectional Parallel Port that includes both Host and Slave modes an Intel 82365-compatible PCMCIA controller for one card slot an industry standard high-performance NS16550-compatible UART with HP-SIR and IrDA v1 0 infrared option an LCD panel interface with DMA supported refresh for many of the standard resolutions an 8254 timer and a general purpose 2- or 3-wire synchronous serial interface for easy interface to low-cost EEPROMs and other serial peripherals System expansion is supported with nine programmable Chip Select (CS) signals and a generic ISA-type bus interface for external devices and memory TL EE 12514 – 2 FIGURE 1-1 NS486SXF Internal Resource to Pins Map 5 http www national com 1 0 System Overview (Continued) Certain I O lines not being used by disabled peripherals can be reconfigured for use as general purpose bidirectional I O lines (up to 29 pins) This gives the designer maximum flexibility in designing various systems using the NS486SXF device It is expected that an NS486SXF system will minimally include the NS486SXF system controller with on-board processor and I O devices boot ROM and working RAM memory Many applications will not require any additional I O support Finally the NS486SXF implements a very flexible power management scheme that permits selective control of individual I O subsystems with varying levels of power consumption NS486SXF provides a cost-effective hardware platform for the design and implementation of a wide range of office automation and communication systems With its powerful embedded ‘486-class processor comprehensive set of onchip peripheral controllers flexible power management structure and reconfigurable I O lines NS486SXF makes possible a variety of end-user systems based on the same hardware Because of its optimized design and on-board resources a very cost effective system can be achieved 1 2 32-BIT PROCESSOR CORE The NS486SXF processor core is an implementation of the protected mode ‘486 instruction set architecture optimized using a RISC-like design philosophy for embedded applications Using this approach the most frequently used instructions are optimized and on an average execute in a lower number of clock cycles than a ‘486 The NS486SXF features a three stage pipeline efficient instruction prefetching mechanism and single cycle instruction decoding for most instructions Additionally a 1 kbyte instruction cache and single cycle DRAM access provide higher memory performance than a larger unified cache implementation The NS486SXF processor provides the same programming model and register set as the standard ‘486 except that real mode virtual memory and floating point support have been eliminated These features have little or no impact in embedded applications and save significant silicon real estate At reset unlike the standard ‘486 the NS486SXF starts up in protected mode instead of real mode All ‘486 instructions appropriate to protected mode and our hardware configuration are supported including debug instructions The NS486SXF is initially available to run 25 MHz at 5V The processor clock is obtained by dividing the crystal frequency by two For example a 25 MHz NS486SXF runs with a 50 MHz crystal oscillator as the master clock As a result of our innovative design the NS486SXF achieves performance equivalent to a standard ‘486 with less circuitry This translates into reduced power consumption and a lower overall system cost It also makes the NS486SXF ideal for ‘‘green’’ systems and battery operated systems 1 3 SYSTEM SERVICE ELEMENTS The NS486SXF controller provides the basic hardware resources required for the O S-defined System Service Elements These include a DRAM controller a DMA controller programmable interval timer a protected WATCHDOG timer a programmable interrupt controller a real-time clock and calendar and comprehensive power management features 6 1 3 1 DRAM Controller The NS486SXF DRAM controller supports one or two adjustable-sized banks of dynamic RAM using a 16-bit data path Support is provided for byte parity (if desired) requiring the DRAM banks to be 18 bits wide when parity is enabled Banks can be up to 8 Mbytes in size The DRAM controller supports page mode read and write operations and can also support both byte and word accesses All access control signals for read write and parity checking are generated as well as an automatic and programmable CASbefore-RAS refresh If self-refresh DRAMs are used refresh can be disabled saving power NS486SXF provides flexible support for use of a number of different DRAM configurations using popular DRAM devices Access is optimized for fast page mode DRAMs and they will provide the highest performance with contiguous data When accessing data bytes or words in the same DRAM page the data access is in one cycle This performance provides fast data access times without the overhead of a separate data cache Page sizes can be 512 1024 2048 or 4096 bytes Flexibility for DRAM timing is provided through programming of the DRAM controller registers 3 or 4 cycle page miss accesses and extended CAS cycles can be selected Memory bank 0 starts at address 0h memory bank 1 can start at any address in the 128 Mbyte address map that is a multiple of its size 1 3 2 DMA Controller The NS486SXF Direct Memory Access (DMA) controller is a high speed 16-bit controller that improves system performance by off-loading from the processor the task of managing data transfers to and from memory and external devices Data transfers are done independently from the processor at a maximum data rate of 2 bytes per 2 clock cycles (A 25 MHz clock yields a 25 megabyte per second transfer rate ) There are six independent DMA channels Requestor and target addresses have a maximum addressable memory range of 64 Mbytes Three standard transfer modes single block and demand are provided giving the designer a wide range of DMA options A special transfer type cascademaster allows an external master to access the NS486SXF ISA-like bus Normal transfers can be from memory to memory memory to I O and I O to memory DMA transfers are controlled by DMA control registers in the NS486SXF control register I O map 1 3 3 Programmable Interval Timer The NS486SXF programmable interval timer is compatible with the Intel 8254 programmable interval timer and contains three identical timers (CH0 – CH2) CH0 and CH1 can be used to generate accurate timing delays under software control CH2 may be configured to provide a WATCHDOG timer function 1 3 4 WATCHDOG Timer The NS486SXF WATCHDOG timer CH2 is a protected 16-bit timer that can be used to prevent system ‘‘lockups or hangups ’’ It uses a 1 kHz clock generated by the on-chip real-time clock circuit If the WATCHDOG timer is enabled and times out a reset or interrupt will be generated allowing graceful recovery from an unexpected system lockup http www national com 1 0 System Overview (Continued) 1 3 5 Interrupt Controller The NS486SXF interrupt controller consists of two cascaded programmable interrupt controllers that are compatible with the Intel 8259A Programmable Interrupt Controller They provide a total of 15 (out of 16) programmable interrupts Three interrupts are reserved for a real time clock-tick interrupt a real time clock interrupt request and a cascade interrupt channel The remaining 13 interrupts can be used by internal or external sources Additional external interrupt controllers can be cascaded as well 1 3 6 Real Time Clock Calendar The NS486SXF Real Time Clock Calendar is a low power clock that provides a time-of-day clock and 100-year calendar with alarm features and battery operation Time is kept in BCD or binary format It includes 50 bytes of general purpose CMOS RAM and 3 maskable interrupt sources It is compatible with the DS1287 and MC146818 RTC Calendar devices except for the general purpose memory size 1 3 7 Power Management Features The NS486SXF power management structure includes a number of power saving mechanisms that can be combined to achieve comprehensive power savings under a variety of system conditions First of all the core processor power consumption can be controlled by varying the processor system clock frequency The internal CPU clock can be divided by 4 8 16 32 or 64 In addition in idle mode the internal processor clock will be disabled Finally if an external crystal oscillator circuit is being used it can be disabled For maximum power savings all internal clocks can be disabled (except for the real-time clock oscillator) The clocks of the on-board peripherals can be individually or globally controlled By setting bits in the power management control registers the internal clocks to the DMA controller the ECP port the three-wire interface the timer the LCD controller the DRAM controller the PCMCIA controller and the UART can be disabled In addition to these internal clocks the external SYSCLK can be disabled via a bit in the power management control registers Using various combinations of these power saving controls with the NS486SXF controller will result in excellent programmable power management for any application 1 4 NS486SXF SYSTEM BUS The NS486SXF system bus provides the interface to offchip peripherals and memory It offers an ISA-compatible interface and is therefore capable of directly interfacing to many ISA peripheral control devices The interface is accomplished through the Bus Interface Unit (BIU) The BIU generates all of the access signals for both internal and external peripherals and memory Depending upon whether the access is to internal peripherals external peripherals or external memory the BIU generates the timing and control signals to access those resources The BIU is designed to support a glueless interface to many ISA-type peripherals For debug purposes the NS486SXF can be set to generate external bus cycles at the same time as an internal peripheral access takes place This gives logic analyzers or other debug tools the ability to track and capture internal peripheral accesses Access to internal peripherals is accomplished in three CPU T-states (clock cycles) The fastest access to off-chip I O is also three T-states When accessing off-chip memory and I O wait state generation is accomplished through a combination of NS486SXF chip select logic and off-chip peripheral feedback signals TL EE 12514 – 3 FIGURE 1-2 NS486SXF Internal Busses 7 http www national com 1 0 System Overview (Continued) When the CPU is in idle mode the BIU is designed to mimic the CPU during DMA interchanges between memory and peripherals By responding to DRQs and generating DACK and HOLDA signals as required the BIU eliminates the need to reactivate the CPU during such transfers as screen updates from memory to the LCD controller This gives the designer added flexibility in conserving power while maintaining basic system functions 1 5 OTHER ON-BOARD PERIPHERALS In addition to those peripherals and system control elements needed for System Service Elements the NS486SXF also includes a number of I O controllers and resources that make implementing a complete embedded system possible with just a single-chip NS486SXF controller These include an IEEE 1284 Extended Capabilities Port a serial UART port a LCD controller a PCMCIA interface and a MICROWIRE or Access bus synchronous serial bus interface In addition unused I O controllers free up their I O pins for general purpose use 1 5 1 Reconfigurable I O Lines The NS486SXF supports reconfigurable I O For example if the UART ECP Parallel Port LCD or PCMCIA functions are not being used the I O pins associated with them can be reconfigured as general purpose bidirectional I O pins Up to 29 pins can be reconfigured for this purpose This capability makes the NS486SXF extremely versatile and ideal for supporting different end product configurations with a single NS486SXF device 1 5 2 IEEE 1284 Bidirectional Port The NS486SXF parallel port is a multifunction 8-bit parallel port that is compatible with the IEEE 1284 bidirectional parallel port standard The operation of the parallel port is set by the content of the NS486SXF parallel port I O control registers The port can operate in one of two modes a standard parallel port mode (PC compatible) or a full Extended Capabilities Port (ECP) mode The NS486SXF ECP port can support both Host and Slave ECP mode In slave mode the NS486SXF becomes a versatile microprocessor for parallel I O peripheral devices 1 5 3 PCMCIA Interface The NS486SXF PCMCIA interface supports the direct connection of a single PCMCIA 2 0 IC card Exchange Card Architecture (ExCA release 1 50) compatibility and eXecute In Place (XIP) capability is also provided Accessing the PCMCIA interface switches the external bus automatically into the PCMCIA mode and permits Memory Window Mapping and Address Offset to be handled inside the NS486SXF device Power management and ‘‘hot’’ card insertion removal options can be implemented using external buffering if required 1 5 4 MICROWIRE Access bus Interface The NS486SXF MICROWIRE Access bus interface provides for full support of either the three-wire MICROWIRE or the two-wire Access bus serial interfaces MICROWIRE has an alternate clock phasing option that supports the SPI bus protocol as well These industry standard interfaces permit easy interfacing to a wide range of low-cost specialty memories and I O devices These include EEPROMs SRAMs timers clock chips A D converters D A converters and peripheral device drivers 1 5 5 UART Serial Port The NS486SXF UART provides complete NS16550 (PC standard) serial communications port compatibility including the performance enhancing 16-byte deep FIFO It performs serial-to-parallel conversion from external devices to the NS486SXF and parallel-to-serial conversion from the NS486SXF to external peripherals Full modem control can be supported A serial IrDA v1 0 and HP-SIR (infrared) mode is also supported making possible low-cost wireless communications between an NS486SXF-based system and other wireless infrared systems 1 5 6 LCD Controller The NS486SXF LCD controller is capable of controlling a variety of monochrome supertwist LCD configurations including 320x240 320x200 and 480x320 black and white or grayscale graphics LCD modules equipped with self-contained screen drivers It uses a video frame buffer in system DRAM with either a 1- or 2-bit per pixel grayscale A 60 Hz to 90 Hz frame refresh rate is supported Special controls permit the fine tuning of display characteristics to precisely optimize visual display quality 1 6 ICE SUPPORT National Semiconductor has worked closely with Microtek International to provide hardware in-circuit emulator support for the NS486SXF The Microtek product (PowerPack EANS486) uses a special bondout version of the NS486SXF to deliver a full-featured hardware emulator that is capable of tracing on chip activity including peripheral interrupt and I O activity The emulator runs at full speed and supports overlay memory and multiple triggers 1 7 OTHER ISSUES NS486SXF provides a comprehensive set of on-board peripherals Also it is designed to easily interface to external peripherals In addition to this ISA-like bus which supports ISA-compatible peripherals the NS486SXF provides an interface to an external master with a shared memory space The external master or auxiliary processor interface allows low cost interfacing to shared external memory belonging to other external masters (including another NS486SXF controller) To program the resources of the NS486SXF a set of internal control registers exists These registers provide precise control over all internal resources and the setup of external NS486SXF control signals It is the designer’s responsibility to ensure the proper initialization of the registers in this I O map In addition the NS486SXF core processor itself requires several descriptor tables and initialization parameters that must be set by user-written start-up software The NS486SXF is designed from the ground up for optimum price performance in embedded systems This makes the NS486SXF the logical choice as the base hardware platform for executing an embedded operating system kernel such as those available from Microtec International Wind River ISI QNX and many others Any Operating System or Real-Time Executive that will operate in a segmented or flat memory model protect mode environment is a suitable complement to the NS486SXF Also there are many third party tool sets that will allow an executable application to be built to run directly on the target hardware without an O S environment 8 http www national com 2 0 Pin Description Tables TL EE 12514 – 4 FIGURE 2-1 NS486SXF Package Pinout Diagram The NS486SXF single chip controller is provided in a compact 160-pin industry standard JEDEC PQFP package The following tables detail the Symbol Type and Description of each pin The tables divide the pins into functional groups as follows Bus Interface Unit Pins DMA Control Pins DRAM Control Pins Power Pins Reset Logic Pins Auxiliary Processor Interface Pins Test Pins Interrupt Control Pins Real Time Clock Pins LCD Interface Pins Oscillator Pins UART IrDA Pins PCMCIA Pins IEEE-1284 Port (ECP Mode) Pins Timer Pins 3-Wire Serial I O Pins General Purpose Chip Select Pins and Reconfigurable I O Pins Twenty-nine I O pins are multipurpose In their standard modes they perform specific I O controller functions When those particular I O functions are not required in the system however those pins can be reprogrammed to become general purpose bidirectional I O lines Note In the above figure and in the following tables all active low signals are shown with an overbar 9 http www national com 2 0 Pin Description Tables (Continued) TABLE 2-1 Bus Interface Unit Pins Symbol SA 25 0 Pins 130 133 135 137 139 141 143 146 149 151 153 156 159 132 134 136 138 140 142 145 148 150 152 155 158 160 Type O Function System Address bus These output-only signals carry the latched address for the current access DRAM accesses multiplex the row and column addresses for the DRAMs on the SA 12 1 pins During Interrupt Acknowledge cycles the internal master interrupt controller’s cascade line signals CAS 2 0 are driven onto SA 25 23 respectively SA 0 is sampled at the end of reset to determine if the part will run normally or enter ICE TRI-STATE mode SD 15 0 2356 8 9 10 11 13 15 16 18 19 20 21 22 129 IO System Data bus This bi-directional data bus provides the data path for all memory and I O accesses During transfers with 8-bit devices the upper data byte is not used (SD 15 8 ) SBHE O Byte High Enable This active-low signal indicates that the high byte (odd address byte) is being transferred External 16-bit devices should use this signal to help them determine that a data byte is to be transferred on the upper byte of the System Data bus (SD 15 8 ) 8-bit devices should ignore this signal SBHE is sampled at the end of power good reset to determine if the boot ROM is 8- or 16-bit wide IO Read command This active-low signal instructs an I O device to place data onto the system data bus IO Write command This active-low signal indicates to an I O device that a write operation is in process on the system bus MEMory Read command This active-low signal instructs a memory mapped device to place data onto the system data bus MEMory Write command This active-low signal indicates to a memory mapped device that a write operation is in process on the system bus Chip Select 16-bit This active-low feedback signal indicates that the device being accessed is a 16-bit device This signal should be driven by external devices with an open collector driver If a chip select is programmed to force 16-bit accesses this signal will be asserted (low) during the access ReaDY An external device may drive this signal inactive low to insert wait states and extend the external bus cycle This signal should be driven with an open collector or be TRI-STATE driven IOR IOW MEMR MEMW CS16 124 125 126 127 122 O O O O IO RDY 123 I http www national com 10 2 0 Pin Description Tables (Continued) TABLE 2-2 DMA Control Pins Symbol DRQ 4 DRQ 3 DRQ 2 DRQ 0 DACK DACK DACK DACK 4 3 2 0 Pins 34 32 36 38 35 33 37 39 Type I O Function DMA ReQuest A DRQn signal requests the internal DMA Controller to transfer data between the Requesting Device and memory DMA ACKnowledge When the CPU has relinquished control of the bus to a requesting DMA channel the appropriate active-low DACKn signal acknowledges the winning DRQn TC EOP 40 IO Terminal Count End Of Process This signal may operate either as a terminal count output or an active-low End of Process input As TC an active-high pulse occurs on this signal when the terminal count for any DMA channel has been reached As EOP an external device may terminate the DMA transfer by driving this signal active-low TABLE 2-3 DRAM Control Pins Symbol RAS 1 0 Pins 30 31 Type O Function Row Address Strobe On the falling edge of these active-low signals Bank 1 and Bank 0 respectively should latch in the row address off of SA 12 1 If only one bank of DRAMs are supported RAS0 will support that bank and RAS1 will be unused Column Address Strobe (High Byte) These active-low signals indicate when the column access is being made to the high byte of DRAM Bank 1 and DRAM Bank 0 respectively If only one bank of DRAMs are supported CASH0 will support the high byte of that bank and CASH1 will be unused Column Address Strobe (Low Byte) These active-low signals indicate when the column access is being made to the low byte of DRAM Bank 1 and DRAM Bank 0 respectively If only one bank of DRAMs are supported CASL0 will support the low byte of that bank and CASL1 will be unused Write Enable Active low signal for writing the data into the DRAM bank DRAM Data Parity DRAM data parity may be enabled or disabled if disabled these two pins will be unused Otherwise for DRAM writes the NS486SXF’s DRAM Controller will generate odd parity and drive the odd parity onto these two pins For DRAM reads the NS486SXF’s DRAM Controller will read the values driven on these two pins and check it for odd parity in association with the appropriate data byte CASH 1 0 25 26 O CASL 1 0 28 29 O WE DPH DPL 23 1 12 O IO 11 http www national com 2 0 Pin Description Tables (Continued) TABLE 2-4 Power Pins Symbol VDD Pins 7 17 27 47 63 87 101 131 147 157 4 14 24 44 61 84 98 128 144 154 Type I a 5V power to core and I O Function VSS I Ground to core and I O TABLE 2-5 Reset Logic Pins Symbol RESET RESET PWGOOD Pins 119 120 60 Type O O I Function RESET system output driver This active high signal resets or initializes system peripheral logic during power up or during a low line voltage outage Inverse of RESET for peripherals requiring active low reset PoWer GOOD This active-high (Schmitt Trigger) input will cause a hardware reset to the NS486SXF whenever this input goes low This pin will typically be driven by the power supply and PWGOOD will remain low until the power supply determines that stable and valid voltage levels have been achieved TABLE 2-6 Auxiliary Processor Interface Pins Symbol EREQ CS6 RTS Pins 102 Type O Function This pin has three programmable options controlled by the Modem Signal Control Register (refer to the UART section) 1 External bus REQuest (active-low) to an auxiliary processor 2 Chip Select 6 (active-low) pin 3 Request To Send When low this signal informs the MODEM or data set that the UART is ready to exchange data The RTS output signal can be set to an active low by programming bit 2 (RTS) of the MODEM Control Register A Master Reset operation sets this signal to its inactive (high) state Loop mode operation holds this signal in its inactive state EACK CS7 DSR 103 IO I O I This pin has three possible programmable options controlled by the Modem Signal Control Register (refer to the UART section) 1 External bus ACKnowledge (active-low) from an auxiliary processor 2 Chip Select 7 (active-low) pin 3 Data Set Ready When low it indicates that the MODEM or data set is ready to link with the UART The DSR signal is a MODEM status input whose condition can be tested by the CPU reading bit 5 (DSR) of the MODEM Status Register Bit 5 is the complement of the DSR signal Bit 1 (DDSR) of the MODEM Status Register indicates whether the DSR input has changed state since the previous reading of the MODEM Status Register Note Whenever the DSR bit of the MODEM Status Register changes state an interrupt is generated if the MODEM Status Interrupt is enabled DRV CS8 DTR 104 O This pin has three possible programmable options controlled by the Modem Signal Control Register (refer to the UART section) 1 DSP shared memory DRiVe control signal 2 Chip Select 8 (active-low) pin 3 Data Terminal Ready When low this signal informs the MODEM or data set that the UART is ready to establish a communications link The DTR output signal can be set to an active low by programming bit 0 (DTR) of the MODEM Control Register to a high level A Master Reset operation sets this signal to its inactive (high) state Loop mode operation holds this signal in its inactive state http www national com 12 2 0 Pin Description Tables (Continued) TABLE 2-7 Test Pins Symbol TEST Pins 66 Type IO Function Reserved for testing and development system support TABLE 2-8 Interrupt Control Pins Symbol NMI INTA IRQ 5 0 Pins 105 106 107 108 109 110 111 112 Type I O I Function Non-Maskable Interrupt This active-high signal will generate a non-maskable interrupt to the CPU when it is active high Normally this signal is used to indicate a serious system error INTerrupt Acknowledge During each interrupt acknowledge cycle this signal will strobe low it should be used by external cascaded interrupt controllers Interrupt ReQuests These inputs are either rising edge or low-level sensitive interrupt requests depending on the configuration of the internal interrupt controllers These interrupt requests may also be programmed to support externally cascaded interrupt controller(s) The IRQ pins are also used to select a particular test in test mode If the PCMCIA controller is enabled IRQ 5 becomes the IREQ signal TABLE 2-9 Real Time Clock Pins Symbol RTCX1 RTCX2 Vbat Pins 62 64 65 Type I O I Function Real Time Clock crystal oscillator input 32 kHz crystal Real Time Clock crystal oscillator output 32 kHz crystal External a battery input for real time clock TABLE 2-10 LCD Interface Pins Symbol LCD 3 0 CL2 CL1 CLF Pins 51 52 53 54 50 49 48 Type O O O O Function Data Output Word to LCD 1 e White 0 e Blue black Word CLock to LCD Row CLock to LCD Frame CLock to LCD TABLE 2-11 Oscillator Pins Symbol SYSCLK Pins 121 Type O Function SYStem CLocK This clock output pin will either be driven with a signal half the frequency of the OSCX1 input clock frequency or the CPU’s clock frequency which is determined in the Power Management Control Register 1 The source selection for this signal is determined by bit 1 of the Power Management Control Register 3 OSCillator Crystal 1 input This pin should either be driven by a TTL oscillator or be connected to an external crystal circuit This signal is the fundamental clock source for all clocked elements in the NS486SXF except the Real-Time Clock which has its own crystal pins OSCillator Crystal 2 output This is the output side of the NS486SXF on-chip circuitry provided to support an external crystal circuit If a TTL oscillator drives OSCX1 this pin should be a no connect OSCX1 45 I OSCX2 46 O 13 http www national com 2 0 Pin Description Tables (Continued) TABLE 2-12 HP-SIR UART Pins Symbol Tx Rx UCLK Pins 57 58 59 Type O I O Function UART Transmit data In HP-SIR mode this pin is the UART output encoded for the serial infrared link Otherwise it is the transmit output of the 16550 UART UART Receive data In HP-SIR mode this pin is routed through the serial infrared decoder Otherwise it is the receive input to the 16550 Uart CLocK Output of programmable rate UART MODEM clock Typically used for the Infrared Modulator TABLE 2-13 PCMCIA Pins Symbol CD RST Pins 68 67 Type O I Function CarD ReSeT This active high signal resets the PCMCIA card during a soft-reset IO port IS 16 bits Write Protect When a PCMCIA card is configured as an IO card this signal is asserted to indicate the currently addressed IO port is 16 bits wide When a PCMCIA card is configured as a memory card an active high signal indicates the card is currently write protected Battery Voltage Detect bit 2 SPeaKeR output When a PCMCIA card is configured as a memory card this input along with BVD 1 will provide status information about the card’s onboard battery condition When a PCMCIA card is configured as an IO card this pin will act as the audio output of the card to the system Battery Voltage Detect bit 1 STatuS ChaNGe output When a PCMCIA card is configured as a memory card this input along with BVD 2 will provide status information about the card’s onboard battery state When a PCMCIA card is configured as an I O card the status change signal indicates one or more of the memory status signals (BVD 2 1 WP RDY or BSY) has changed states PCMCIA VCC SELect When this signal is low the VCC power to the PCMCIA card should be enabled PCMCIA VPP SELect 1 and 2 These signals indicate the voltage with which the VPP power to the PCMCIA card should be driven General Purpose Input This signal is a general purpose input signal used with a PCMCIA card to indicate a valid VPP state a pending card eject insertion or as an interrupt source Card Detect Both signals are low when the PCMCIA card is correctly inserted DIRection Used to control the direction of the data line buffers to the PCMCIA interface ENABLE PCMCIA Enables the buffer drivers to the PCMCIA interface Low true signal REG PCMCIA card support IOIS16 WP BVD2 SPKR 74 I BVD1 STSCNG 73 I VCC SEL VPP SEL1 VPP SEL2 GPI CD2 CD1 DIR ENABLE REG 69 70 71 72 76 75 77 78 79 O O I I O O O Note If PCMCIA is enabled Chip Selects 1 and 2 become Card Enable 1 and 2 See Table 2-17 ‘‘General Purpose Chip Select Pins’’ Also IRQ 5 becomes the PCMCIA IREQ signal http www national com 14 2 0 Pin Description Tables (Continued) TABLE 2-14 IEEE-1284 Port (ECP Mode) Symbol PD 7 0 Pins 81 83 86 89 82 85 88 90 Type OI Function Parallel Data Bi-directional data pins transfer data and address information to and from the parallel port SLIN STB AFD 91 92 93 OI OI OI SeLect INput Used in a closed-loop handshake with BUSY to transfer data or address information from the host to the peripheral Host driven data STroBe Driven high by the host while in ECP Mode Asserted low by host to terminate ECP Mode and return link to Compatibility Mode Host driven Automatic FeeD The host asserts this line low for flow control in the reverse direction It is used in a interlocked handshake with ACK Provides command information in the forward direction Host driven Active low INITialize When this signal is asserted low to place the data channel in the reverse direction the peripheral is allowed to drive the data bus Host driven Active low ACKnowledge Used in closed-loop handshake with AFD to transfer data to the host Peripheral device drive Active low Peripheral Error Asserted low to acknowledge INIT reverse request Peripheral device drive SeLeCT Asserted high when selected or indicating an affirmative response for each respective extensibility byte Peripheral device drive Active high ERROR This input is asserted low by the peripheral to request host communications Valid only in the forward direction Peripheral device drive Active low BUSY This is asserted low by the peripheral for flow control in the forward direction de-asserted to acknowledge transfer of data or address completion Peripheral device drive Active low TABLE 2-15 Timer Pins INIT ACK PE SLCT ERR BUSY 94 95 96 97 99 100 OI IO IO IO IO IO Symbol T0 Pins 55 Type IO Function Programmable Timer pin 0 This Bidirectional pin may be selected to control one of the following four functions via bits 1-0 of the Timer I O Control Register 1 The GATE input into Timer 0 2 The GATE input into Timer 1 3 The OUT output from Timer 0 4 The CLK input into Timer 1 T1 56 IO Programmable Timer pin 1 This Bidirectional pin may be selected to control one of the following four functions via bits 3-2 of the Timer I O Control Register 1 The GATE input into Timer 0 2 The GATE input into Timer 1 3 The OUT output from Timer 1 4 The CLK input into Timer 0 15 http www national com 2 0 Pin Description Tables (Continued) TABLE 2-16 3-Wire Serial I O Pins Symbol SO DCD Pins 41 Type IO Function This pin has two possible programmable options controlled by the Modem Signal Control Register (refer to the UART section) 1 The Serial data Output signal for MICROWIRE 2 Data Carrier Detect When low this input signal indicates that the data carrier has been detected by the MODEM or data set The DCD signal is a MODEM status input whose condition can be tested by the CPU reading bit 7 (DCD) of the MODEM Status Register Bit 7 is the complement of the DCD signal Bit 3 (DDCD) of the MODEM Status Register indicates whether the DCD input has changed state since the previous reading of the MODEM Status Register DCD has no effect on the receiver Note Whenever the DCD bit of the MODEM Status Register changes state an interrupt is generated if the MODEM Status Interrupt is enabled SI CTS 42 IO This pin has two possible programmable options controlled by the Modem Signal Control Register (refer to the UART section) 1 The Serial data Input signal for MICROWIRE or the serial data I O for Access bus 2 Clear To Send When low this input signal indicates that the MODEM or data set is ready to exchange data The CTS signal is a MODEM status input whose conditions can be tested by the CPU reading bit 4 (CTS) of the MODEM Status Register Bit 4 is the complement of the CTS signal Bit 0 (DCTS) of the MODEM Status Register indicates whether the CTS input has changed state since the previous reading of the MODEM Status Register CTS has no effect on the Transmitter Note Whenever the CTS bit of the MODEM Status Register changes state an interrupt is generated if the MODEM Status Interrupt is enabled SCLK RI 43 IO O I This pin has two possible programmable options controlled by the Modem Signal Control Register (refer to the UART section) 1 The Serial CLocK signal for MICROWIRE and Access bus 2 Ring Indicator When low this input signal indicates that a telephone ringing signal has been received by the MODEM or data set The RI signal is a MODEM status input whose condition can be tested by the CPU reading bit 6 (RI) of the MODEM Status Register Bit 6 is the complement of the RI signal Bit 2 (TERI) of the MODEM Status Register indicates whether the RI input signal has changed from a low to high state since the previous reading of the MODEM Status Register Note Whenever the CTS bit of the MODEM Status Register changes state an interrupt is generated if the MODEM Status Interrupt is enabled Note Whenever the RI bit of the MODEM Status Register changes from a high to a low state an interrupt is generated if the MODEM Status Interrupt is enabled Note For MICROWIRE Slave Mode a pin must be selected to be the Chip Select Input http www national com 16 2 0 Pin Description Tables (Continued) TABLE 2-17 General Purpose Chip Select Pins Symbol CS 0 CS 5 1 Pins 118 113 114 115 116 117 Type O IO Function Chip Select 0 This output is used as the chip-select for the system boot ROM It defaults to the upper 64 kbytes of memory Chip Select 1-5 These pins can be programmed to be either memory or I O mapped chip selects which are used for glue-less connection to external peripherals When the PCMCIA Controller is enabled CS 1 and CS 2 become PCMCIA Card Enable outputs 1 and 2 (CE1 and CE2 respectively) TABLE 2-18 Summary of Reconfigurable I O Pins Symbol REG ENABLE DIR GPI VPP SEL2 VPP SEL1 VCC CD CLF CL2 CL1 LCD 3 0 PD 7 0 Rx UCLK CS 4 CS 3 CS 2 CS 1 SEL RST Pins 1 1 1 1 1 1 1 1 1 1 1 4 8 1 1 1 1 1 1 Type IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Pin 79 78 77 72 71 70 69 68 48 50 49 51 52 53 54 81 82 83 85 86 88 89 90 58 59 114 115 116 117 Original Function PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA PCMCIA LCD LCD LCD LCD ECP UART UART CS4 CS3 CS2 CS1 Power Up State TRI-STATE 1 0 TRI-STATE 0 0 1 TRI-STATE 0 0 0 0000 TRI-STATE TRI-STATE Oscillating 1 1 1 1 These 29 pins typically used for various I O peripheral purposes as defined in the above tables can be reconfigured for use as general purpose I O pins if the normally defined I O function is not required 17 http www national com 3 0 Device Specifications 3 1 DC ELECTRICAL SPECIFICATIONS 5V g 5% 3 1 1 Recommended Operating Conditions Symbol VDD TA Parameter Supply Voltage Operating Temperature ESD Tolerance CZAP e 100 pF RZAP e 1 5 kX (Note 1) 3 1 2 Absolute Maximum Ratings (Notes 2 and 3) Symbol VDD VDDA VI VO TSTG TL Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Lead Temperature Soldering (10 sec ) Condition Min b0 5 b0 5 b0 5 b 65 Condition Min 4 75 0 2000 Typ 50 Max 5 25 a 70 Units V C V Max 70 VDD a 0 5 VDD a 0 5 a 165 a 260 Units V V V C C 3 1 3 Capacitance TA e 25 C f e 1 MHz Symbol CIN CIN1 CIO CO Parameter Input Pin Capacitance Clock Input Capacitance I O Pin Capacitance Output Pin Capacitance Condition Min Typ 5 8 10 6 Max 7 10 12 8 Units pF pF pF pF http www national com 18 3 0 Device Specifications (Continued) 3 1 4 DC Characteristics (Under Recommended Operating Conditions) Symbol VIH VIL ICC Parameter Input High Voltage Input Low Voltage VDD Average Supply Current VIL e 0 5V VIH e 2 4V No Load Condition Min 20 b0 5 Typ Max VDD 08 Units V V mA Note 1 Value based on test complying with NSC SOP5-028 human body model ESD testing using the ETS-910 tester Note 2 Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 3 Unless otherwise specified all voltages are referenced to ground 3 1 4 1 EXTERNAL BUS Symbol VOH Parameter Output High Voltage Condition IOH e b6 mA (Nch Quiet-drive) or IOH e b24 mA (High-drive) on SA12–1 DP1 – 0 SD15 – 0 IOH e b12 mA on SA0 SA25 – 13 SA0 b min 10 kX pullup IOL e 20 mA on SA12– 1 DP1 –0 SD15 –0 IOL e 12 mA on SA0 SA25 – 13 BHE Min Max Units Notes Max Load on SA12 – 1 is 100 pF and SD0 – 15 is 50 pF 24 V VOL Output Low Voltage 04 V 3 1 4 2 DMA CONTROL UNIT Symbol VOH Parameter Output High Voltage Condition IOH e b6 mA on TC EOP IOH e b4 mA on DACK4 DACK3 DACK2 DACK0 IOL e 6 mA on TC EOP IOL e 4 mA on DACK4 DACK3 DACK2 DACK0 Min Max Units Notes 24 V VOL Output Low Voltage 04 V 3 1 4 3 DRAM CONTROL UNIT Symbol VOH Parameter Output High Voltage Condition IOH e b6 mA(Nch Quiet-drive) or IOH e b24 mA (High-drive) on RAS0–1 CASH0 – 1 CASL0 – 1 WE VOL Output Low Voltage IOL e 20 mA on RAS1–0 CASH1 – 0 CASL1 – 0 WE Min Max Units Notes Max load on RAS1 – 0 CASH1 –0 and CASL1 –0 is 63 pF Max load on WE is 100 pF 24 V 04 V 19 http www national com 3 0 Device Specifications (Continued) 3 1 4 4 AUXILIARY PROCESSOR INTERFACE Symbol VOH VOL Parameter Output High Voltage Output Low Voltage Condition IOH e b6 mA on EACK IOH e b4 mA on DRV EREQ IOL e 6 mA on EACK IOL e 4 mA on DRV EREQ Min 24 04 Max Unit V V Notes 3 1 4 5 HP-SIR UART Symbol VOH VOL Parameter Output High Voltage Output Low Voltage Condition IOH e b100 mA IOH e b6 mA on Tx UCLK Rx IOL e 100 mA IOL e 6 mA on Tx UCLK Rx Min VCC b 0 2 24 02 04 Max Unit V V V V Notes 3 1 4 6 EXTERNAL BUS CONTROL Symbol VOH Parameter Output High Voltage Condition IOH e b12 mA on IOR IOW MEMR MEMW RESET RESET CS16 BHE CS16 - min 10 kX pullup IOL e 12mA on IOR IOW MEMR MEMW RESET RESET CS16 BHE Min Max Unit Notes 24 V VOL Output Low Voltage 04 V 3 1 4 7 OSCILLATOR (CPUX1 CLK) Symbol VOH VOL VIH VIL Parameter Output High Voltage Output Low Voltage OSCX1 Input High Voltage OSCX2 Input Low Voltage Condition IOH e b12 mA on SYSCLK IOL e 12 mA on SYSCLK 24 04 V Min 24 04 Max Unit V V OSCX2 is the output Notes 3 1 4 8 LCD INTERFACE Symbol VOH VOH VOL Parameter Output High Voltage Output High Voltage Output Low Voltage Condition IOH e b2 6 mA on LCD 3 0 CL1 CL2 CLF IOH e b6 mA on LCD 3 0 CL1 CL2 CLF IOL e 6 mA on LCD 3 0 CL1 CL2 CLF Min VCC b 0 8 24 04 Max Unit V V V Notes CMOS Level TTl Level http www national com 20 3 0 Device Specifications (Continued) 3 1 4 9 REAL TIME CLOCK (RTCX1 CLK) Symbol VIH VIL VBAT IBAT Parameter RTCX1 Input High Voltage RTCX1 Input Low Voltage Battery Voltage Battery Current VBAT e 3 0 V 24 3 Condition Min 20 04 V V mA Lithium Battery Max Unit Notes RTCX2 is the output 3 1 4 10 PCMCIA (RIO8-15) Symbol VOH Parameter Output High Voltage IOH e b12 mA on VCC SEL VPP SEL1 VPP SEL2 IOH e b6 mA on DIR ENABLE REG CD RST BUSY LED GPI RSV (RSV is a reserved usage pin) VOL Output Low Voltage IOL e 12 mA on VCC SEL VPP SEL VPP SEL2 IOL e 6 mA on DIR ENABLE REG CD RST BUSY LED GPI RSV (RSV is a reserved usage pin) 24 V Condition Min Max Unit Notes Power Switch 1 Card at a 50 pF Load 04 V 3 1 4 11 IEEE-1284 PORT (ECP MODE) AND (RIO16-31) Symbol ICH Parameter High-Level Output Current (Note 4) Low-Level Output Current Condition VOH e 2 4V on PD 7 0 SLIN STB AFD PE INIT ACK SLCT ERR BUSY VOL e 0 4V on PD 7 0 SLIN STB AFD PE INIT ACK SLCT ERR BUSY Min 14 Max Unit mA Notes ICL 14 mA Note 4 When ECP mode 0 or ECP mode 2 and bit 1 of PCR is 0 for the parallel port are selected pins AFD INIT SLIN and STB are open drain supports 4 7 kX resistors should be used The ECP I Os have over-voltage protection against being backdriven by higher external voltages when the I Os are at TRI-STATE The I Os also isolate the NS486SXF power-rail from external voltages when the chip is powered down The maximum power-down leakage is 1 mA to ground 3 1 4 12 TIMER Symbol VOH VOL Parameter Output High Voltage Output Low Voltage Condition IOH e b6 mA on T0 T1 IOL e 6 mA on T0 T1 Min 24 04 Max Unit V V Notes 21 http www national com 3 0 Device Specifications (Continued) 3 1 4 13 GENERAL PURPOSE CHIP SELECTS Symbol VOH VOL Parameter Output High Voltage Output Low Voltage Condition IOH e b6 mA on CS5 – 0 IOL e 6 mA on CS5 – 0 Min 24 04 Max Unit V V Notes 3 1 4 14 INTERRUPT CONTROLLER Symbol VOH VOL Parameter Output High Voltage Output Low Voltage Condition IOH e b12 mA on INTA IOL e 12 mA on INTA Min 24 04 Max Unit V V Notes 3 1 4 15 3-WIRE I O (AND ACCESS BUS) Symbol VOH VOL Parameter Output High Voltage Output Low Voltage Condition IOH e b12 mA on SO SI SCLK IOL e 12 mA on SO SI SCLK Min 24 04 Max Unit V V Notes http www national com 22 3 0 Device Specifications (Continued) 3 2 GENERAL AC SPECIFICATIONS AC TEST CONDITIONS Note 1 S1 e VCC for tPZL and tPLZ measurements S1 e GND for tPZL and tPHZ measurements S1 e Open for push-pull outputs Note 2 RL e 1 1k Note 3 CL includes scope and jig capacitance Test Circuit for Output Tests TL H 12514 – 5 Propagation Delay Waveforms Setup and Hold Time Waveforms TL H 12514 – 6 TL H 12514 – 7 Note Waveform for negative edge sensitive circuits will be invert Input Pulse Width Waveforms Except for Clock Pins TRI-STATE Output Enable and Disable Waveforms TL H 12514 – 8 TL H 12514 – 9 FIGURE 3-1 Switching Characteristic Measurement Waveforms 23 http www national com 3 0 Device Specifications (Continued) LCD Output Specification Standard Hysteresis Input Specification Standard TL H 12514 – 11 VHYS e 200 mV Switching thresholds not specified TL H 12514–10 FIGURE 3-2 More Switching Specifications 3 2 1 Power Ramp Times TL H 12514 – 12 FIGURE 3-3 Power Supply Rise and Fall TABLE 3-1 VDD Rise and Fall Times Symbol tPF tPR Parameter VDD Falling Time from 4 5V to 0V VDD Rising Time from 0V to 4 5V Min 5 5 Max Unit ms ms Note The rising falling rate is assumed linear 3 2 2 PWRGOOD and Power Rampdown Timing TABLE 3-2 VDD Rampdown vs PWRGOOD Symbol tVPG tPGV Parameter VDD (4 5V) to PWGOOD High PWGOOD Falling to VDD (4 5V) Min 1 1 Max Unit ms ms TL H 12514 – 13 Note The rising falling rate is assumed linear FIGURE 3-4 PWGOOD in Relation to VDD http www national com 24 3 0 Device Specifications (Continued) 3 3 AC SWITCHING SPECIFICATIONS The following pages list some of the preliminary AC Specifications for the NS486SXF All parameters are listed in alphabetical order according to their Symbol The Tables consist of the following Parameter A short description of the specification being documented Symbol A quick reference between the timing diagram and the Table entries Formula An equation which in addition to the Minimum and Maximum Specifications can be used to determine the actual timing provided at any operating frequency Min Minimum Specification when added to the value produced by the formula Max Maximum Specification when added to the value produced by the formula How to calculate the actual specification at a given frequency In the formula column one will see many formulae which contain the variable T The T represents one period (or one T-state) of the CPU Clock So if the CPU is running at 25 MHz T is equivalent to 40 ns similarly if the CPU is running at 20 MHz T is equivalent to 50 ns EXAMPLE Calculate the minimum guaranteed Column Address Setup Time e At 25 MHz Formula a Min Spec e (0 5T) a (b20 ns) 0 5 (40 ns) a (b20 ns) e e 0 ns 20 ns b 20 ns e At 20 MHz Formula a Min Spec e (0 5T) a (b20 ns) 0 5 (50 ns) a (b20 ns) e e 5 ns 25 ns b 20 ns As the frequency varies so will many of the specifications One should always calculate the specification based on the CPU’s operating frequency 25 http www national com http www national com 26 3 0 Device Specifications (Continued) 3 3 1 DRAM Interface Timing Specification TL H 12514 – 14 The CLK signal is only included as a reference no specifications are guaranteed to this signal FIGURE 3-5 DRAM Timing Diagram TABLE 3-3 4-Cycle Page Miss Preliminary Specifications Symbol tASC tASR tCAC tCAH tCAS tCP tDH tDS tOFF tRAS tRAH tRCD tRCH tRCS tRP tWCH tWCS Parameter Column Address Setup Time Row Address Setup Time Access Time from CAS Column Address Hold Time CAS Pulse Width Page Mode CAS Precharge Write Data Hold Time Write Data Setup Time Read Data Valid Hold Time RAS Pulse Width Row Address Hold Time RAS to CAS Delay Time Read Command Hold Time Read Command Setup Time RAS Precharge Time Write Command Hold TIme Write Command Setup Time 0 5T a 1 5T a 0 5T a 0 5T a 2 5T a 0 5T a 1 5T a Formula 0 5T a 0 5T a 0 5T a 0 5T a 0 5T a 0 5T a 0 5T a 0 5T a b5 Min b 20 b 20 Max b5 0 b 10 b5 b 20 10 0 b 15 b 10 b 20 Programmable 0 b 20 b 10 b5 b 20 27 http www national com 3 0 Device Specifications (Continued) TABLE 3-4 3 Cycle Miss Preliminary Specifications Symbol tASC tASR tCAC tCAH tCAS tCP tDH tDS tOFF tRAS tRAH tRCD tRCH tRCS tRP tWCH tWCS Parameter Column Address Setup Time Row Address Setup Time Access Time From CAS Column Address Hold Time CAS Pulse Width Page Mode CAS Precharge Write Data Hold Time Write Data Setup Time Read Data Valid Hold Time RAS Pulse Width Row Address Hold Time RAS to CAS Delay Time Read Command Hold Time Read Command Setup Time RAS Precharge Time Write Command Hold TIme Write Command Setup Time 0 5T a 1 0T a 0 5T a 0 5T a 2 0T a 0 5T a 1 0T a Formula 0 5T a 0 5T a 0 5T a 0 5T a 0 5T a 0 5T a 0 5T a 0 5T a b5 Min b 20 b 20 Max b5 0 b 10 b5 b 20 10 0 b 15 b 10 b 20 PROG 0 b 20 0 b5 b 20 3 3 2 ISA-like Bus Cycles Timing Specification TL H 12514 – 15 The CLK signal is only included as a reference no specifications are guaranteed to this signal FIGURE 3-6 ISA-like Bus Timing Diagram http www national com 28 3 0 Device Specifications (Continued) TABLE 3-5 No Command Delay ISA-like Bus Specifications Symbol tAHCD tASCD tCDPW tCHCD tCSCD tDOFF tRCAT tRCDH tWCDH tWCVD tWCS Parameter Address Hold Time from CMD Address Setup TIme to CMD Command Pulse Width Chip Select Hold Time from CMD Chip Select Setup Time to CMD Read Data TRI-STATE Read CMD Data Access TIme Read CMD Data Hold TIme Write CMD Data Hold Time Write CMD to Valid Data Write Command Setup Time 0 5T a b 20 Formula 1 0T a 1 0T a 1 0T a (Wait)T a 1 0T a 1 0T a 1 0T a 1 0T a (Wait)T a Min b 20 b 20 b 10 b 25 b 40 Max b25 b 30 0 1 0T a b 25 5 Note The value of (Wait) in the above formulae is the number of programmed wait states associated with that access cycle (default value is 7 but may be programmed to 0–7) TABLE 3-6 One Programmed Command Delay ISA-like Bus Specifications Symbol tAHCD tASCD tCDPW tCHCD tCSCD tDOFF tRCAT tRCDH tWCDH tWCVD tWCS Parameter Address Hold Time from CMD Address Setup TIme to CMD Command Pulse Width Chip Select Hold Time from CMD Chip Select Setup Time to CMD Read Data TRI-STATE Read CMD Data Access TIme Read CMD Data Hold TIme Write CMD Data Hold Time Write Valid Data to CMD (Note 2) Write Command Setup Time 1 0T a 1 0T a 0 5T a Formula 1 0T a 2 0T a 1 0T a (Wait)T a 1 0T a 2 0T a 1 0T a 1 0T a (Wait)T a 0 b 25 b5 b 20 Min b 20 b 20 b 10 b 25 b 40 Max b25 b 30 Note 1 The value of (Wait) in the above formulae is the number of programmed wait states associated with that access cycle (default value is 7 but may be programmed to 0–7) Note 2 For this case Valid Write Data Sets-up to the leading edge of the Command Strobe 29 http www national com 3 0 Device Specifications (Continued) 3 3 3 Ready Feedback Timing Specifications TL H 12514 – 16 FIGURE 3-7 Ready Feedback Timing Diagram TABLE 3-7 Ready Signal Timing Specifications Symbol tRACD tRDYH tRDYI Parameter RDY Active to CMD Rising RDY Hold Time from CMD CMD to RDY Inactive Feedback 1 0T a (Wait)T a (E Formula RDY)T a Min 0 0 b30 Max Note The value of (Wait) in the above formulae is the number of programmed wait states associated with that access cycle (default value is 7 but may be programmed to 0–7) The value of (E RDY) in the above formulae is the number of programmed extended ready states associated with every access cycle (default number is 2 but may be programmed to 0–2) 3 3 4 OSCX1 AC Specification TL H 12514 – 17 FIGURE 3-8 TTL Clock Input Timing Diagram TABLE 3-8 TTL Clock Input Specification Symbol tCTp tCTh tCTl tCTr tCTf Parameter CTTL Clock Period CTTL High Time (Note) CTTL Low Time (Note) CTTL Rise Time CTTL Fall Time Min 40 (0 5 X tCTp) b 4 (0 5 X tCTp) b 4 4 4 Max 870 Unit ns ns ns ns ns Note Except for the cycle in which the core frequency is changed In this cycle tCTh and tCTl relate to different tCTp cycles http www national com 30 3 0 Device Specifications (Continued) 3 3 5 Peripheral Timing Specifications 3 3 5 1 DMA CONTROLLER TL H 12514 – 18 FIGURE 3-9 DMA Controller Read Timing Diagram TL H 12514 – 19 FIGURE 3-10 DMA Controller Write Timing Diagram TABLE 3-9 DMA Controller Specifications Symbol trdyl trdyh teoprci teopwci tdrqlwci tdrqlrci tdckrca Parameter RDY Inactive Low Setup to CMD Active RDY Active High Setup to CMD Inactive 45 ns 2T a 5 ns 2T a 36 ns T a 40 ns 2T a 2 2 ns Min b 15 ns Typ Max 2T a 15 ns 31 http www national com 3 0 Device Specifications (Continued) 3 3 5 2 PIC AC SPECS TL H 12514 – 20 FIGURE 3-11 PIC Timing Diagram TABLE 3-10 PIC Timing Specifications Symbol tpicjljh tpicahrl tpicrlrh tpicrhax tpicrldv tpicrhdz tpicrhrl 10 100 Parameter Min 100 0 235 0 200 Typ Max http www national com 32 3 0 Device Specifications (Continued) 3 3 5 3 PARALLEL PORT TABLE 3-11 Parallel Port Compatibility Mode Handshake Timing Values Symbol Tready Tsetup(host) Tsetup (peripheral) Tstrobe(host) Tstrobe (peripheral) Thold(host) Thold (peripheral) Tbusy Treply Tack Tnbusy Tnext Measured At Host Output Host Output Peripheral Input Host Output Peripheral Input Host Output Peripheral Input Peripheral Output Peripheral Output Peripheral Output Peripheral Output Host Output Measured From Busy VIL Data Stable Data Stable Strobe VOL Strobe VIL Strobe VOH Strobe VIL Strobe VIL Strobe VIL Ack VOL Ack VOH Ack VIL Measured to Strobe VOH Strobe VOH Strobe VIH Strobe l VOL Strobe l VIL Data or AutoFd Change Data or AutoFd Change Busy VOH Ack VOH Ack VOL Busy VOH Strobe VOH Value (min max) 0 min 750 ns min 500 ns max 750 ns min 500 ms max 500 ns max 750 ns min 500 ns max 500 ns max 0 min 500 ns min 10 ms max 0 min 0 min Compliance Compatible Hosts Compatible Hosts Compatible Peripherals Compatible Hosts Compatible Peripherals Compatible Hosts Compatible Peripherals Compliant Peripherals Compatible Peripherals Compatible Peripherals Compliant Peripherals Compliant Hosts Note 1 For more information on the history of Centronics Standard Parallel and PC-Compatible Parallel Interfaces see annex Ca and in particular C 6 2 for Busyto-Ack timing variations Note 2 VIL is the low-level voltage input VOL is the low-level voltage output VOH is the high-level voltage output VIH is the high-level voltage input The maximum value stated for peripherals in this table are referenced to the peripheral For example the peripheral cannot require more than 500 ns data setup time Recognize that complementary signal changes may have overlapping signal transistions The zero minimum value cannot be guaranteed TABLE 3-12 Parallel Port IEEE 1284 Mode Handshake Timing Values Symbol TH T% TL TR TS TP TD TES TEL TER Parameter Host Response Time Infinite Response Time Peripheral Response Time Peripheral Response Time (ECP Mode Only) Host Recovery Time (ECP Mode Only) Minimum Setup or Pulse Width Minimum Data Setup Time (ECP EPP Modes Only) Short Response Time (EPP Mode Only) Long Response Time (EPP Mode Only) Termination Pulse Width (EPP Mode Only) Min 0 0 0 0 35 ms 0 5 ms 0 0 0 50 ms 125 ms 10 ms Infinite Max 1 0s Infinite 35 ms 33 http www national com 3 0 Device Specifications (Continued) 3 3 5 4 PCMCIA CONTROLLER TL EE 12514 – 21 FIGURE 3-12 Memory Read Timing TABLE 3-13 PCMCIA Memory Read Timing Specifications Symbol tpcavgl tpghax tpcglwtv tpcavqv tpcghqz tpcglqv 0 ns 125 ns Parameter Condition Min 50 ns 20 ns 35 ns 250 ns Typ Max TL EE 12514 – 22 FIGURE 3-13 Memory Write Timing Diagram TABLE 3-14 Memory Write Timing Diagram Symbol tpcavgl tpcax tpcwlwh tpcdvwh tpcwmdx tpcwlwtv http www national com Parameter Condition Min 50 ns 20 ns 60 ns a (tsysclk) 100 ns 30 ns Typ Max # (number of waitstates) 35 ns 34 3 0 Device Specifications (Continued) TL EE 12514 – 23 FIGURE 3-14 I O Read Timing TABLE 3-15 PCMCIA I O Read Specifications Symbol tpcavigl tpcighax tpcigligh tpcavisl tpcavish tpciglwtl tpciglqv tpcighqx tpcwthqv 0 ns 35 ns Parameter Condition Min 100 ns 20 ns 180 ns 35 ns 35 ns 35 ns 120 ns Typ Max 35 http www national com 3 0 Device Specifications (Continued) TL EE 12514 – 24 FIGURE 3-15 I O Write Timing Diagram TABLE 3-16 PCMCIA I O Write Specifications Symbol tpcaviwl tpciwhax tpcavisl tpcavish tpciwlwtl tpcdviwl tpcwthiwh tpciwhdx 80 ns 0 ns 30 ns Parameter Condition Min 100 ns 20 ns 35 ns 35 ns 35 ns Typ Max http www national com 36 3 0 Device Specifications (Continued) 3 3 5 5 MICROWIRE (3-WIRE) ACCESS BUS TL EE 12514 – 25 FIGURE 3-16 Access bus Timing Diagram TABLE 3-17 Access Bus Timing Specifications Symbol fsclk tbuf tlow thigh tdhold tdset tsu sto tsu sta Parameter SCLK Clock Frequency Bus Free Time between STOP and START Condition Low Period of the SCLK Clock High Period of the SCLK Clock Data Hold Time Data Setup Time Setup Time for STOP Condition Hold Time for START Condition 4 7 ms 4 7 ms 4 0 ms 250 250 4 0 ms 4 7 ms Formula Min Max 100 kHz 37 http www national com 3 0 Device Specifications (Continued) 3 3 5 6 FIFO UART Symbol D D tBHD tBLD Parameter OSC Clock Divider Baud Divisor Baud Output Positive Edge Delay Baud Output Negative Edge Delay Condition Min 1 1 Max 63 65535 56 56 Units CLKs CLKs ns ns TL EE 12514 – 26 Symbol tIRTXW tIRRXW Parameter IRTX Pulse Width IRRX Pulse Width Condition Min 1 6 ms 1 6 ms Max 3 16 6 16 Units BAUD OUT Cycles BAUD OUT Cycles TL EE 12514 – 27 FIGURE 3-17 UART Baud Rate and Infrared Clocks http www national com 38 3 0 Device Specifications (Continued) Symbol tSINT tSTI tSI tIRS tMDO tRIM tSIM BAUDOUT Cycle e Parameter Delay from Stop Bit to Set Interrupt Delay from Start Bit to IRQ Delay from Initial Write to IRQ Delay from IRQ Reset to Tx Start Delay from Write to Output Delay to Reset IRQA from Read Delay to Set IRQ from Modem Input Input Clock Frequency 16 x Baudrate Divisor OSCX1 Frequency UART Clock Divisor 16 8 Min Max 2 8 24 24 40 78 40 Units BAUDOUT Cycles BAUDOUT Cycles BAUDOUT Cycles BAUDOUT Cycles ns ns ns Input Clock Frequency e Registers Divisor Latch Holds Baudrate Divisor EF70 holds UART Clock Divisor TL EE 12514 – 28 TL EE 12514 – 29 FIGURE 3-18 UART IRQ Timing 39 http www national com 3 0 Device Specifications (Continued) TL EE 12514 – 30 FIGURE 3-19 UART Modem Control Timing http www national com 40 3 0 Device Specifications (Continued) 3 3 5 7 LCD CONTROLLER TL EE 12514 – 31 FIGURE 3-20 LCD Controller Timing Diagram TABLE 3-18 LCD Controller Timing Specifications Symbol tlcclf tlccl2 tlcds tlcdh tlcdd tlcfp tlcbp tlcfs tlcfh tllsu tllcl2 tw Parameter Frame Period Dot Clock Period LCD Data Situp CL2 Fall LCD Data Hold CL2 Fall LCD Data Delay CL2 Rise CL2 Falling to CL1 Rising CL1 Falling to CL2 Rising CLF Setup to CL1 Fall CLF Hold from CL1 Fall CL1 Load Setup Time CL1 Falling to CL2 Falling Pulse Width Condition Programmable Programmable Oscx1 6 (tlccl2) 2-50 ns (tlccl2) 2-50 ns (tlccl2) 2-50 ns (tlccl2) 2-50 ns (tlccl2) 2-50 ns tlccl2 (tlccl2) 2-20 ns (tlccl2) 2-50 ns (tlccl2) 2-50 ns (tlccl2) 2-50 ns 50 ns Min Typ 14 3 ms Max 41 http www national com 3 0 Device Specifications (Continued) 3 3 5 8 SUPPORTED TESTMODES Symbol tAND tHILO tTRI tTOG Parameter AND Function Result Delay HI LO Function Drive Delay TRI-STATE Outputs Delay Toggle Function Delay Conditions Min Max 1 1 1 1 Units ms ms ms ms TL EE 12514 – 32 FIGURE 3-21 Testmode Timing Diagram http www national com 42 43 http www national com NS486SXF Optimized 32-Bit 486-Class Controller with On-Chip Peripherals for Embedded Systems 3 0 Device Specifications (Continued) 3 4 Physical Dimensions inches (millimeters) The NS486SXF is provided in a 160-lead 28mm x 28mm PQFP package 160-Lead Plastic Quad Flatpak JEDEC (VUL) NS Package Number VUL160A FIGURE 3-22 Plastic Package Specifications LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation Americas Tel 1(800) 272-9959 Fax 1(800) 737-7018 Email support nsc com 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness http www national com National Semiconductor Europe Fax a49 (0) 180-530 85 86 Email europe support nsc com Deutsch Tel a49 (0) 180-530 85 85 English Tel a49 (0) 180-532 78 32 Fran ais Tel a49 (0) 180-532 93 58 Italiano Tel a49 (0) 180-534 16 80 National Semiconductor Southeast Asia Fax (852) 2376 3901 Email sea support nsc com National Semiconductor Japan Ltd Tel 81-3-5620-7561 Fax 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications