PC87351

PC87351 PC98 and ACPI Compliant SuperI/O with System Wake-Up Control PRELIMINARY May 1998 PC87351 PC98 and ACPI Compliant SuperI/O with System Wake-Up Control Highlights General Description The PC87351, a member of National Semiconductor’s SuperI/O family of integrated PC peripherals, is a 128-pin, PC98 and ACPI compliant SuperI/O that offers a single-chip solution to the most commonly used ISA peripherals. The PC87351 incorporates: a Floppy Disk Controller (FDC) which is available also on the Parallel Port pins as a multiplexed option (PPM), two enhanced Serial Ports, Infrared Comunication Port (HP-SIR, Sharp-IR, and Consumer Electronics-IR), a full IEEE 1284 Parallel Port, a Keyboard and Mouse Controller (KBC), System Wake-Up Control (SWC), General-Purpose Input/Output (GPIO) Ports with assert interrupt capability, and Fan Speed Control (FSC). Outstanding Features • • • Fan Speed Control for two fans 11 General-Purpose I/O Ports, bi-directional, with interrupt assertion capability System Wake-Up Control powered by VSB, generates power-up request in response to preprogrammed keyboard or mouse sequence, modem, telephone ring, and two general-purpose events without an external clock Serial or parallel IRQ support Programmable write protect for Floppy Disk Controller Power-fail recovery support • • • Block Diagram Parallel Port/ Floppy Drive Interface Serial Interface Serial Infrared Interface Interface Floppy Drive Interface ISA Interface SERIRQ PPM Serial Port 1 Serial Port 2 with IR Floppy Disk Controller IEEE 1284 Parallel Port Host Interface VSB VBAT System Wake-Up Control Fan Speed Control General-Purpose I/O Keyboard and Mouse Controller Wake-Up PWUREQ Events FANOUT0 FANOUT1 I/O Ports Keyboard and Mouse Ports Interface IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation. Microsoft® and Windows® are registered trademarks of Microsoft Corporation. TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation www.national.com Highlights (Continued) Features • Serial Port 2 with Infrared — — — — — — — Software compatible with the 16550A and the 16450 Shadow register support for write-only bit monitoring UART data rates up to 1.5 Mbaud HP-SIR ASK-IR option of SHARP-IR DASK-IR option of SHARP-IR Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80 — Non-standard DMA support − 1 or 2 channels • PC98 and ACPI Compliant — PnP Configuration Register structure — Flexible resource allocation for all logical devices t Relocatable base address t 9 Parallel IRQ or 15 Serial IRQ routing options t 3 optional 8-bit DMA channels (where applicable) • Floppy Disk Controller (FDC) — Software compatible with the PC8477, which contains a superset of the FDC functions in the µDP8473, the NEC µPD765A and the N82077 — 16-byte FIFO — Burst and non-burst modes — High-performance, digital data separator that does not require any external filter components — Standard 5.25" and 3.5" Floppy Disk Drive (FDD) support — Perpendicular recording drive support — Three-mode FDD support — Full support for IBM Tape Drive Register (TDR) implementation of AT and PS/2 drive types — Programmable write protect • Keyboard and Mouse Controller (KBC) — 8-bit microcontroller — Software compatible with the 8042AH and PC87911 microcontrollers — 2 KB custom-designed program ROM — 256 bytes RAM for data — Four programmable dedicated open-drain I/O lines — Asynchronous access to two data registers and one status register during normal operation — Support for both interrupt and polling — 93 instructions — 8-bit timer/counter — Support for binary and BCD arithmetic — Operation at 8 MHz,12 MHz or 16 MHz (programmable option) — Can be customized by using the PC87323, which includes a RAM-based KBC as a development platform for KBC code • Parallel Port — Software or hardware control — Enhanced Parallel Port (EPP) compatible with new version EPP 1.9 and IEEE 1284 compliant — EPP support for version EPP 1.7 of the Xircom specification — EPP support as mode 4 of the Extended Capabilities Port (ECP) — IEEE 1284 compliant ECP, including level 2 — Selection of internal pull-up or pull-down resistor for Paper End (PE) pin — PCI bus utilization reduction by supporting a demand DMA mode mechanism and a DMA fairness mechanism — Protection circuit that prevents damage to the parallel port when a printer connected to it powers up or is operated at high voltages, even if the device is in power-down — Output buffers that can sink and source 14 mA • 11 General-Purpose Bi-Directional I/O (GPIO) Ports — 11 GPIO pins with interrupt assertion capability — Programmable drive type for each output pin (opendrain, push-pull or output disable) — Programmable option for internal pull-up resistor on each input pin — Output lock option — Back-drive protection circuit • System Wake-Up Control (SWC) — Power-up request upon detection of Keyboard, Mouse, RI1, RI2, RING, PME1 and PME2 activity, as follows: t Preprogrammed Keyboard or Mouse sequence t External modem ring on serial ports t Ring pulse or pulse train on the RING input t General purpose events, PME1 and PME2 — Optional routing of power-up request on IRQ line — Powered by VSB — Battery-backed wake-up setup — Power-fail recovery support • Parallel Port Multiplexer (PPM) — Additional set of FDC signals multiplexed on Parallel Port pins — Optional connection of additional, external FDD on Parallel Port connector • Serial Port 1 — Software compatible with the 16550A and the 16450 — Shadow register support for write-only bit monitoring — UART data rates up to 1.5 Mbaud www.national.com 2 Highlights (Continued) • Fan Speed Control — Supports different fan types — Two speed control lines with Pulse Width Modulation (PWM) t Output signal in the range of 6 Hz to 93.75 KHz t Duty cycle resolution of 1/256 • Clock Sources — 48 MHz clock input — On-chip low frequency clock generator for wake-up — 33 MHz PCI clock input for Serial IRQ 3 www.national.com Datasheet Revision Record Revision Date January 1998 March 1998 May 1998 Status Comments Advanced Information First pass with pin assignment Preliminary Preliminary Implemented: Item 1, Important Notice, pin reassignment Implemented: Items 2-31 below Paginated Datasheet Revision Record in datasheet body Item 2 3 4 5 6 7 Pin description Topic Change/Correction Table describing KBCLK, KBDAT, MCLK and MDAT signals enhanced to identify pin drivers All references deleted 9 logical devices Modified Hardware reset explanation modified REGISTER TYPE ABBREVIATIONS added before the existing section; all subsequent numbering changed Reserved Bits 65 00 01 10 11 Bits 210 00X 011 010 10X 11X Location Section 1.4.7 Chapter 2 Section 2.1 Section 2.2.3, Table 2-7 Section 2.2.5 Section 2.3 PPM power save mode Device architecture Index 74h, 75h DMA Channel Select 0, 1 VSB Power-Up Reset New section added 8 9 SuperI/O Configuration 1 Register Bit 3 SuperI/O Configuration 2 Register Section 2.4.3 Section 2.4.4 Function GPIO17 KBRST (default) P12 PNF (PPM mode enabled) Function GPIO14 (default) GPIO14 IRQ9 IRRX2/IRSL0 P17 Section 2.4.7 10 11 12 13 14 15 SuperI/O Revision ID Register Keyboard and Mouse Controller Implementation GPIO Configuration Registers’ Access GPIO Pin Configuration Select Register Bits 5-4 Fan Speed Control Location and Type added All references to TEST0 and TEST1 changed to T0 Section 2.11.1 and T1, respectively. Ports 1 and 2 description deleted Drawing modified Section 2.12.2 Figure 2-6 01, 10: Binary value of the port number, 1-2 respectively Section 2.12.4 11: Reserved General Description modified; nomenclature of Fan Section 2.13 Control Duty Cycle and Fan Control Pre-Scale registers changed; references to Fan Speed Monitor deleted; configuration parameters (Reset and Type) modified Number of events changed to seven Section 3.2 16 System events www.national.com 4 Datasheet Revision Record Item 17 18 19 20 21 22 23 24 25 26 27 Topic Keyboard Data Shift Register Mouse Data Shift Register Ports with fewer than 8 bits (Continued) Change/Correction Description modified Description modified Implementation description Bit nomenclature modified Location Section 3.4.6 Section 3.4.7 Chapter 4 Section 4.3 Section 4.4.1 Section 4.4.3 Section 4.4.4 Section 4.4.5 Section 4.4.6 Section 5.2 Section 5.3.3 Interrupt Assertion and Handling GPIO Pin Configuration Access Register Bit nomenclature and descriptions changed GPIO Data Out Register GPIO Data In Register GPIO Interrupt Enable Register GPIO Status Register Functional Description Fan Control Duty Cycle Register Bits 7-0 Bitmap and Reset values added Bitmap and Reset values added Bitmap and Reset values added Bitmap and Reset values added Corrected and enhanced 00h: PWM output is continuously low 01h-FEh: PWM output is high for [Duty Cycle Value] clock cycles and low for [256-Duty Cycle Value] clock cycles FFh: PWM output is continuously high 28 29 30 31 Device Specifications VBAT Battery Supply Current Host Interface I/O Cycle Timing Serial IRQ Timing Timing diagrams drawn more precisely Conditions and Max modified Chapter 11 Section 11.1.4 tRDYA, tRDYl and tRWl added to table; footnote 2 added Section 11.2.3 to table; IOCHRDY timing diagram added Output timing diagram modified Section 11.2.6 www.national.com 5 Contents at a Glance This datasheet is organized to reflect two major topics: device specific issues (Highlights through Chapter 2), and proprietary functional blocks (Chapters 3 through 10). Chapter 11 summarizes the AC/DC device characteristics. Highlights ................................................................................................................................................ 1 This chapter provides a description and block diagram of the PC87351 major functional blocks, the features that make this device outstanding as compared with comparable devices, and the features of each functional block. Datasheet Revision Record ................................................................................................................... 4 This chapter serves two functions: it provides a record of the datasheet revisions; it documents the major changes of this revision as compared with the previous one. Each change is cross-referenced and linked to the change location within the datasheet. 1 Signal/Pin Connection and Description ............................................................................................. 11 This chapter includes four major sections: a connection diagram that shows all pins and their related signals; an alphabetical directory of all signals/pins linked to a table where more detailed information is provided; a summary of all multiplexed signals and how to configure them for default and alternate settings, and functionally grouped tables that describe each signal/pin in detail. 2 Device Architecture and Configuration .............................................................................................. 24 This chapter presents all PC87351 device specific information on the relevant functional blocks, as well as hardware and software configuration procedures and the related configuration registers. 3 System Wake-Up Control (SWC) ......................................................................................................... 51 This chapter describes the system wake-up capabilities of the PC87351, designed to maximize device functionality while minimizing power consumption. 4 General-Purpose Input/Output (GPIO) Port ....................................................................................... 57 This chapter describes a single 8-bit GPIO port, whose operation is associated with two register sets. Refer to the Device Architecture and Configuration chapter for the specific implementation in this device. 5 Fan Speed Control................................................................................................................................ 64 This chapter describes the Fan Speed Control, a programmable Pulse Width Modulation (PWM) generator whose output is used to control the fan’s power voltage. Refer to the Device Architecture and Configuration chapter for the specific implementation in this device. 6-10 Legacy Functional Blocks Please refer to the PC87307, PC87309 or PC87317 Datasheet for information on the Keyboard and Mouse Controller (KBC), Serial Port 1, Serial Port 2 with IR, Parallel Port and Floppy Disk Controller (FDC). 11 Device Characteristics ....................................................................................................................................... 72 This chapter provides DC electrical characteristics, both general and of all device pins, as well as AC electrical characteristics. www.national.com 6 Table of Contents Highlights ....................................................................................................................................................... 1 Datasheet Revision Record .................................................................................................................... 4 1.0 Signal/Pin Connection and Description 1.1 1.2 1.3 1.4 CONNECTION DIAGRAM ......................................................................................................... 11 SIGNAL/PIN DIRECTORY ........................................................................................................ 12 PIN MULTIPLEXING ................................................................................................................. 16 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 17 1.4.1 Clock ............................................................................................................................ 17 1.4.2 Fan Speed Control ...................................................................................................... 17 1.4.3 FDC (Including PPM) ................................................................................................... 17 1.4.4 General-Purpose Input/Output (GPIO) Ports ............................................................... 19 1.4.5 Host Interface .............................................................................................................. 20 1.4.6 Infrared (IR) ................................................................................................................. 20 1.4.7 Keyboard and Mouse Controller (KBC) ....................................................................... 21 1.4.8 Parallel Port ................................................................................................................. 22 1.4.9 Power and Ground ...................................................................................................... 22 1.4.10 Serial Ports 1 and 2 ..................................................................................................... 23 1.4.11 Strapping ..................................................................................................................... 23 1.4.12 System Wake-Up Control ............................................................................................ 23 2.0 Device Architecture and Configuration 2.1 2.2 OVERVIEW ............................................................................................................................... 24 CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 25 2.2.1 The Index-Data Register Pair ...................................................................................... 25 2.2.2 Banked Logical Device Registers ................................................................................ 25 2.2.3 Standard PnP Register Definitions .............................................................................. 26 2.2.4 Overview of PnP Standard Registers .......................................................................... 28 2.2.5 Default Configuration Setup ........................................................................................ 29 2.2.6 Address Decoding ....................................................................................................... 29 2.2.7 The Internal Clocks ...................................................................................................... 29 REGISTER TYPE ABBREVIATIONS ........................................................................................ 30 SUPERI/O CONFIGURATION AND CONTROL REGISTERS ................................................. 30 2.4.1 SuperI/O Register Map ................................................................................................ 30 2.4.2 SuperI/O ID Register (SID) .......................................................................................... 30 2.4.3 SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 31 2.4.4 SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 32 2.4.5 SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 33 2.4.6 SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 34 2.4.7 SuperI/O Revision ID Register (SRID) ........................................................................ 34 PARALLEL PORT MULTIPLEXER (PPM) ................................................................................ 35 2.5.1 PPM Mode ................................................................................................................... 35 2.5.2 TRI-STATE Control of Parallel Port Pins ..................................................................... 36 FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0 ................................................... 37 2.3 2.4 2.5 2.6 7 www.national.com Table of Contents 2.6.1 2.6.2 2.6.3 2.6.4 2.7 (Continued) General Description ..................................................................................................... 37 Configuration ............................................................................................................... 37 FDC Configuration Register ........................................................................................ 38 Drive ID Register ......................................................................................................... 38 PARALLEL PORT - LOGICAL DEVICE 1 ................................................................................. 39 2.7.1 General Description ..................................................................................................... 39 2.7.2 Configuration ............................................................................................................... 39 2.7.3 Parallel Port Configuration Register ............................................................................ 40 SERIAL PORT 2 - LOGICAL DEVICE 2 .................................................................................... 41 2.8.1 General Description ..................................................................................................... 41 2.8.2 Configuration ............................................................................................................... 41 2.8.3 Serial Port 2 Configuration Register ............................................................................ 41 SERIAL PORT 1 - LOGICAL DEVICE 3 .................................................................................... 42 2.9.1 Configuration ............................................................................................................... 42 2.9.2 Serial Port 1 Configuration Register ............................................................................ 42 SYSTEM WAKE-UP CONTROL (SWC) - LOGICAL DEVICE 4 ................................................ 43 2.10.1 Configuration ............................................................................................................... 43 KEYBOARD AND MOUSE CONTROLLER (KBC) - LOGICAL DEVICES 5 AND 6 .................. 44 2.11.1 General Description ..................................................................................................... 44 2.11.2 Configuration ............................................................................................................... 45 2.11.3 KBC Configuration Register ........................................................................................ 45 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7 ..................... 46 2.12.1 General Description ..................................................................................................... 46 2.12.2 Implementation ............................................................................................................ 46 2.12.3 Configuration ............................................................................................................... 46 2.12.4 GPIO Pin Configuration Select Register ...................................................................... 47 2.12.5 GPIO Pin Configuration Access Register .................................................................... 48 FAN SPEED CONTROL - LOGICAL DEVICE 8 ........................................................................ 49 2.13.1 General Description ..................................................................................................... 49 2.13.2 Configuration ............................................................................................................... 49 2.13.3 Fan Speed Control Configuration Register .................................................................. 50 2.8 2.9 2.10 2.11 2.12 2.13 3.0 System Wake-Up Control (SWC) 3.1 3.2 3.3 OVERVIEW ............................................................................................................................... 51 FUNCTIONAL DESCRIPTION .................................................................................................. 51 EVENT DETECTION ................................................................................................................. 51 3.3.1 Modem Ring ................................................................................................................ 51 3.3.2 Telephone Ring ........................................................................................................... 51 3.3.3 Keyboard and Mouse Activity ...................................................................................... 51 3.3.4 General-Purpose Events ............................................................................................. 51 SWC REGISTERS ..................................................................................................................... 52 3.4.1 SWC Register Map ...................................................................................................... 52 3.4.2 Wake-Up Events Control Register (WKCR) ................................................................ 52 3.4.3 Wake-Up Events Status Register (WKSR) .................................................................. 53 8 3.4 www.national.com Table of Contents 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.5 4.0 (Continued) Wake-Up Configuration Register (WKCFG) ................................................................ 54 PS/2 Protocol Control Register (PS2CTL) ................................................................... 54 Keyboard Data Shift Register (KDSR) ......................................................................... 55 Mouse Data Shift Register (MDSR) ............................................................................. 55 PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) ...................................... 56 SWC REGISTER BITMAP ......................................................................................................... 56 General-Purpose Input/Output (GPIO) Port 4.1 4.2 OVERVIEW ............................................................................................................................... 57 BASIC FUNCTIONALITY .......................................................................................................... 58 4.2.1 Configuration Options .................................................................................................. 58 4.2.2 Operation ..................................................................................................................... 58 INTERRUPT ASSERTION AND HANDLING ............................................................................ 59 4.3.1 Interrupt Configuration ................................................................................................. 59 4.3.2 Interrupt Assertion ....................................................................................................... 59 GPIO PORT REGISTERS ......................................................................................................... 60 4.4.1 GPIO Pin Configuration Access Register .................................................................... 60 4.4.2 GPIO Port Runtime Register Map ............................................................................... 61 4.4.3 GPIO Data Out Register (GPDO) ................................................................................ 62 4.4.4 GPIO Data In Register (GPDI) .................................................................................... 62 4.4.5 GPIO Interrupt Enable Register (GPIEN) .................................................................... 63 4.4.6 GPIO Status Register (GPST) ..................................................................................... 63 4.3 4.4 5.0 Fan Speed Control 5.1 5.2 5.3 OVERVIEW ............................................................................................................................... 64 FUNCTIONAL DESCRIPTION .................................................................................................. 64 FAN SPEED CONTROL REGISTERS ...................................................................................... 65 5.3.1 Fan Speed Control Register Map ................................................................................ 65 5.3.2 Fan Control Pre-Scale Register (FCPSR) ................................................................... 65 5.3.3 Fan Control Duty Cycle Register (FCDCR) ................................................................. 65 FAN SPEED CONTROL BITMAP ............................................................................................. 66 5.4 6.0 Floppy Disk Controller (FDC) Refer to PC87307, PC87309 or PC87317 datasheet. 7.0 Parallel Port Refer to PC87307, PC87309 or PC87317 datasheet. 8.0 Serial Port 2 with IR Refer to PC87307, PC87309 or PC87317 datasheet. 9.0 Serial Port 1 Refer to PC87307, PC87309 or PC87317 datasheet. 10.0 Keyboard and Mouse Controller (KBC) Refer to PC87307, PC87309 or PC87317 datasheet. 9 www.national.com Table of Contents 11.0 (Continued) Device Characteristics 11.1 DC ELECTRICAL CHARACTERISTICS ................................................................................... 72 11.1.1 Recommended Operating Conditions ......................................................................... 72 11.1.2 Absolute Maximum Ratings ......................................................................................... 72 11.1.3 Capacitance ................................................................................................................. 72 11.1.4 Power Consumption under Recommended Operating Conditions .............................. 73 11.1.5 Input, PCI 5V ............................................................................................................... 73 11.1.6 Strap Pin ...................................................................................................................... 73 11.1.7 Input, TTL Compatible ................................................................................................. 73 11.1.8 Input with TTL Schmitt Trigger .................................................................................... 74 11.1.9 Output, Totem-Pole Buffer ........................................................................................... 74 11.1.10 Output, Open-Drain Buffer ........................................................................................... 74 AC ELECTRICAL CHARACTERISTICS .................................................................................... 75 11.2.1 AC Test Conditions ...................................................................................................... 75 11.2.2 Clock Timing ................................................................................................................ 75 11.2.3 Host Interface I/O Cycle Timing ................................................................................... 76 11.2.4 Host Interface DMA Cycle Timing ............................................................................... 78 11.2.5 PCICLK Timing Specifications ..................................................................................... 79 11.2.6 Serial IRQ Timing ........................................................................................................ 80 11.2.7 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing ............................. 81 11.2.8 Modem Control Timing ................................................................................................ 82 11.2.9 FDC Write Data Timing ............................................................................................... 82 11.2.10 FDC Drive Control Timing ........................................................................................... 83 11.2.11 FDC - Read Data Timing ............................................................................................. 83 11.2.12 Standard Parallel Port Timing ...................................................................................... 84 11.2.13 Enhanced Parallel Port Timing .................................................................................... 84 11.2.14 Extended Capabilities Port (ECP) Timing .................................................................... 85 11.2 www.national.com 10 1.0 Signal/Pin Connection and Description 1.0 Signal/Pin Connection and Description 1.1 CONNECTION DIAGRAM WGATE TRK0 WP RDATA HDSEL DSKCHG NC IRRX1 IRTX NC TC DACK3 DACK2 VSS DACK1 DRQ3 DRQ2 DRQ1 MR CLKIN NC GPIO16/IRQ12 GPIO15/IRQ11/P12/P17 GPIO14/IRQ9/IRRX2/P17 GPIO13/IRQ7 GPIO12/IRQ6 WDATA STEP DIR MTR1 DR0 DR1 MTR0 INDEX DRATE0 DENSEL NC NC SLCT/WGATE PE/WDATA BUSY/WAIT/MTR1 ACK/DR1 PD7/MSEN1 PD6/DRATE0 PD5/MSEN0 PD4/DSKCHG VSS VDD PD3/RDATA SLIN/ASTRB/STEP PD2/WP INIT/DIR PD1/TRK0 ERR/HDSEL PD0/INDEX AFD/DSTRB/DENSEL STB/WRITE NC NC KBRST/GPIO17/P12/PNF GA20/GPIO20 KBCLK KBDAT MCLK 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GPIO11/IRQ5 GPIO10/IRQ4 NC SERIRQ/IRQ3 PCICLK/IRQ1 NC IOWR IORD IOCHRDY AEN A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 VSS VDD A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 NC NC PC87351-xxx/VLA xxx = Three character identifier for National data, and keyboard ROM and/or customer identification code MDAT DCD1 DSR1 SIN1 RTS1 SOUT1 CTS1 BADDR/DTR1/BOUT1 RI1 GPIO10/DCD2 GPIO11/DSR2 GPIO12/SIN2 GPIO13/RTS2 VSS GPIO14/SOUT2 GPIO15/CTS2 GPIO16/DTR2/BOUT2 RI2 NC VBAT VSB PWUREQ RING/PME1 SUSP/PME2 GPIO21/FANOUT0/P12/PNF GPIO22/FANOUT1/IRRX2/P17 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87351-xxx/VLA See NS Package Number VLA128A 11 www.national.com SIGNAL/PIN DIRECTORY 1.0 Signal/Pin Connection and Description 1.2 SIGNAL/PIN DIRECTORY (Continued) See Table 1-2 for an alphabetical listing of all signals, cross-referenced to additional information for detailed functional descriptions, electrical DC characteristics, and pin multiplexing. The DC characteristics are denoted by a buffer type symbol, described briefly in Table 1-1 and in detail in Sections 11.1.6 to 11.1.10. The pin multiplexing information refers to three different types of multiplexing: • MUX - Multiplexed functions. Pins are shared between two different functions. Each function is associated with different board connectivity, and normally, the function selection is determined by the board design and cannot be changed dynamically. The multiplexing options must be configured by the BIOS upon power-up, in order to comply with the board implementation. MM - Multiple Mode. Pins have two or more modes of operation within the same function. These modes are associated with the same external (board) connectivity. Mode selection may be controlled by the device driver, through the registers of the functional block, and do not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O configuration perspective. The mode selection method (registers and bits) as well as the signal specification in each mode, are described within the functional description of the relevant functional blocks. PPM - Parallel Port MUX. This special multiplexing of the FDC signals on the Parallel Port pins allows connection of the external FDC through the Parallel Port connector. This multiplexing is dynamic, controlled by hardware, and does not require any special BIOS setup except for enabling the PPM function. The PPM functionality and a listing of the pins that are multiplexed are described in Section 2.5. Table 1-1. Buffer Types Name GND INPCI INSTRP INT INTS INULR Op/n ODn PWR Description Ground pin Input, PCI 5V Input, Strap pin (min VIH is 0.6VDD) with weak pull-down during strap time Input, TTL compatible Input, TTL compatible with Schmitt trigger Input, with serial UL Resistor Section N/A 11.1.5 11.1.6 11.1.7 11.1.8 N/A • • Output, Totem-Pole buffer that is capable of sourcing p mA and sinking n mA 11.1.9 Output, Open-Drain output buffer that is capable of sinking n mA Power pin 11.1.10 N/A Table 1-2. Signal/Pin Directory Functional Group Signal A15-0 ACK AEN AFD/DSTRB ASTRB BADDR BOUT1 BOUT2 BUSY/WAIT CLKIN www.national.com DC Characteristics Multiplexed Buffer Type INT INT INT Section 11.1.7 11.1.7 11.1.7 MM/PPM PPM Pin/s Name 28-19, 16-11 Host Interface 80 29 94 Parallel Port Host Interface Parallel Port Section 1.4.5 1.4.8 1.4.5 1.4.8 OD14, O14/14 11.1.10, 11.1.9 See SLIN/ASTRB 110 Strapping 1.4.11 INSTRP 11.1.6 MUX See DTR1/BOUT1 See DTR2/BOUT2 79 45 Parallel Port Clock 1.4.8 1.4.1 12 INT INT 11.1.7 11.1.7 MM/PPM SIGNAL/PIN DIRECTORY 1.0 Signal/Pin Connection and Description (Continued) Table 1-2. Signal/Pin Directory (Continued) Functional Group Signal CTS1 CTS2 D7-0 DACK1-3 DCD1 DCD2 DENSEL 94 67 DIR 90 DR0 DR1 80 73 DRATE0 82 DRQ1-3 DSKCHG 84 DSR1 DSR2 DSTRB DTR1/BOUT1 DTR2/BOUT2 ERR FANOUT0 FANOUT1 GPIO17-10 GPIO22-20 105 113 Serial Port 1 Serial Port 2 1.4.10 1.4.10 47-49 59 FDC 1.4.3 Host Interface 1.4.5 FDC 1.4.3 69 70 FDC 1.4.3 FDC 1.4.3 FDC 1.4.3 109 118 10-3 50, 52-53 104 112 74 FDC 1.4.3 Pin/s Name Serial Port 1 Serial Port 2 Host Interface Host Interface Serial Port 1 Serial Port 2 Section 1.4.10 1.4.10 1.4.5 1.4.5 1.4.10 1.4.10 Buffer Type INTS INTS INT O15/24 INT INTS INTS OD24, O4/24 Section 11.1.8 11.1.8 11.1.7 11.1.9 11.1.7 11.1.8 11.1.8 11.1.10, 11.1.9 PPM 11.1.10, 11.1.9 PPM 11.1.10, 11.1.9 11.1.10, 11.1.9 PPM 11.1.9 PPM 11.1.9 11.1.7 PPM 11.1.8 11.1.8 MUX MUX MUX DC Characteristics Multiplexed OD24, O4/24 OD24, O4/24 OD24, O4/24 O6/12 O15/24 INT INTS INTS See AFD/DSTRB 110 119 92 127 128 Serial Port 1 Serial Port 2 Parallel Port 1.4.10 1.4.10 1.4.8 O6/12 O6/12 INT O2/20 O2/20 INTS OD12, O6/12 INTS OD12, O6/12 OD24, O4/24 11.1.9 11.1.9 11.1.7 11.1.9 11.1.9 11.1.8 11.1.10, 11.1.9 11.1.8 11.1.10, 11.1.9 11.1.10, 11.1.9 PPM 11.1.7 PPM MM MM/MUX PPM MUX MUX MUX MUX Fan Speed Control 1.4.2 Fan Speed Control 1.4.2 1.4.4 1.4.4 98, 37-43 or GPIO Port 1 112-5, 117-9 127-128, 99 60 GPIO Port 2 HDSEL 92 72 INDEX 93 FDC 1.4.3 FDC 1.4.3 INT 13 www.national.com SIGNAL/PIN DIRECTORY 1.0 Signal/Pin Connection and Description (Continued) Table 1-2. Signal/Pin Directory (Continued) Functional Group Signal GA20 INIT IOCHRDY IORD IOWR IRQ1, 3-7, 9, 11-12 IRRX1 IRRX2/IRSL0 IRRX2 IRSL0 IRTX KBCLK KBDAT KBRST MCLK MDAT MR MSEN0 MSEN1 MTR0 MTR1 79 P12 P17 PCICLK PD7-0 PE PME1 PME2 42, 98, 127 41, 42, 128 34 KBC KBC Host Interface 1.4.7 1.4.7 1.4.5 1.4.8 1.4.8 1.4.12 1.4.12 99 90 30 31 32 Pin/s Name KBC Parallel Port Host Interface Host Interface Host Interface Section 1.4.7 1.4.8 1.4.5 1.4.5 1.4.5 1.4.5 1.4.5 1.4.5 Buffer Type OD4 Section 11.1.10 MUX PPM DC Characteristics Multiplexed OD14, O14/14 11.1.10, 11.1.9 OD24 INT INT 11.1.10 11.1.7 11.1.7 34, 35, 37-43 Host Interface 57 41, 128 Infrared Infrared INT 11.1.7 OD24, O15/24 11.1.10, 11.1.9 INT INT O6/12 11.1.7 11.1.7 11.1.9 MUX MM/MUX See IRRX2/IRSL0 See IRRX2/IRSL0 56 100 101 98 102 103 46 83 81 71 68 FDC 1.4.3 Infrared Wake-Up KBC Wake-Up KBC KBC Wake-Up KBC Wake-Up KBC Host Interface FDC FDC FDC 1.4.5 1.4.12 1.4.7 1.4.12 1.4.7 1.4.7 1.4.12 1.4.7 1.4.12 1.4.7 1.4.5 1.4.3 1.4.3 1.4.3 O6/12 INT OD4 INT OD4 OD4 INT OD4 INT OD4 INTS INT INT OD24, O4/24 OD24, O4/24 OD4 OD4 INT 11.1.9 11.1.7 11.1.10 11.1.7 11.1.10 11.1.10 11.1.7 11.1.10 11.1.7 11.1.10 11.1.8 11.1.7 11.1.7 11.1.10, 11.1.9 11.1.10, 11.1.9 PPM 11.1.10 11.1.10 11.1.7 MUX MUX MUX PPM PPM MUX MUX PPM PPM MUX 81-84, 87, 89, Parallel Port 91, 93 78 125 126 Parallel Port Wake-Up Wake-Up INT 11.1.7 OD14, O14/14 11.1.10, 11.1.9 INT INTS INTS 11.1.7 11.1.8 11.1.8 www.national.com 14 SIGNAL/PIN DIRECTORY 1.0 Signal/Pin Connection and Description (Continued) Table 1-2. Signal/Pin Directory (Continued) Functional Group Signal PNF PWUREQ RDATA 87 RI1 RI2 RING RTS1 RTS2 SERIRQ SIN1 SIN2 SLCT SLIN/ASTRB SOUT1 SOUT2 STEP 88 STB/WRITE SUSP TC TRK0 91 VBAT VDD VSB VSS WAIT WDATA 78 122 17, 86 123 18, 51, 85, 116 Power and Ground 1.4.11 Power and Ground 1.4.9 Power and Ground 1.4.12 Power and Ground 1.4.12 95 126 54 63 FDC 1.4.3 Parallel Port Wake-Up Host Interface 1.4.8 1.4.12 1.4.5 111 120 125 107 115 35 106 114 77 88 108 117 66 FDC 1.4.3 Wake-Up Serial Port 1 Wake-Up Serial Port 2 Wake-Up Serial Port 1 Serial Port 2 Host Interface Serial Port 1 Serial Port 2 Parallel Port Parallel Port Serial Port 1 Serial Port 2 1.4.12 1.4.10 1.4.12 1.4.10 1.4.12 1.4.10 1.4.10 1.4.5 1.4.10 1.4.10 1.4.8 1.4.8 1.4.10 1.4.10 Pin/s Name 98, 127 124 61 FDC 1.4.3 Parallel Port Wake-Up Section 1.4.8 1.4.12 Buffer Type INT OD12 INT INTS INTS INTS O6/12 O6/12 INTS O15/24 INTS INTS INT Section 11.1.7 11.1.10 11.1.7 PPM 11.1.8 11.1.8 11.1.8 11.1.9 11.1.9 11.1.8 11.1.9 11.1.8 11.1.8 11.1.7 MUX PPM MM/PPM MUX MUX MUX MUX DC Characteristics Multiplexed OD14, O14/14 11.1.10, 11.1.9 O6/12 O6/12 OD24, O4/24 11.1.9 11.1.9 11.1.10, 11.1.9 MUX PPM MM MUX OD14, O14/14 11.1.10, 11.1.9 INTS INT INT INULR PWR PWR GND 11.1.8 11.1.7 11.1.7 PPM N/A N/A N/A N/A See BUSY/WAIT 65 FDC 1.4.3 OD24, O4/24 11.1.10, 11.1.9 PPM 15 www.national.com PIN MULTIPLEXING 1.0 Signal/Pin Connection and Description (Continued) Table 1-2. Signal/Pin Directory (Continued) Functional Group Signal 64 WGATE 77 62 WP 89 WRITE See STB/WRITE FDC 1.4.3 Pin/s Name FDC 1.4.3 Section Buffer Type OD24, O4/24 Section 11.1.10, 11.1.9 PPM 11.1.7 PPM DC Characteristics Multiplexed INT 1.3 PIN MULTIPLEXING There are three categories of pins with multiple names: Multiplexed (MUX), Multiple Mode (MM) and Parallel Port MUX (PPM). See Section 1.2 for descriptions of these categories. All the multiplexing options in the MUX category and their associated setup configuration are described in Table 1-3. A multiplexing option may be chosen on one pin only per group. Table 1-3. Pin Multiplexing Configuration Default Pin Signal 34 PCICLK 35 SERIRQ 37 GPIO10 38 GPIO11 39 GPIO12 40 GPIO13 43 GPIO16 41 GPIO14 SIOCF2, Bits 2-1 = 00 I/O or Bits 2-0 = 011 42 GPIO15 SIOCF2, Bits 4-3 = 00 I/O or Bits 4-3, 0 = 011 98 KBRST I/O SIOCF2, Bits 6-5 = 01 I/O SIOCF2, Bit 0 = 0 I/O I Configuration SIOCF2, Bit 0 = 0 Signal IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ12 IRQ9 IRRX2/IRSL0 P17 IRQ11 P12 P17 GPIO17 P12 PNF 99 GA20 I/O SIOCF2, Bit 7 = 1 GPIO20 I/O SIOCF2, Bits 2-0 = 010 I/O SIOCF2, Bits 2-1 = 10 I/O SIOCF2, Bits 2-1 = 11 O SIOCF2, Bits 4-3, 0 = 010 I/O SIOCF2, Bit 0 = 1 I/O Configuration I/O SIOCF2, Bit 0 = 1 I/O SIOCF2, Bit 0 = 1 Alternate I/O SIOCF2, Bit 0 = 0 I/O SIOCF2, Bits 4-3 = 10 I/O SIOCF2, Bits 4-3 = 11 I/O SIOCF2, Bits 6-5 = 00 I/O SIOCF2, Bits 6-5 = 10 I/O SIOCF2, Bits 6-5 = 11 I/O SIOCF2, Bit 7 = 0 www.national.com 16 DETAILED SIGNAL/PIN DESCRIPTIONS 1.0 Signal/Pin Connection and Description (Continued) Table 1-3. Pin Multiplexing Configuration (Continued) Default Pin Signal 112 GPIO10 113 GPIO11 114 GPIO12 115 GPIO13 117 GPIO14 118 GPIO15 119 GPIO16 125 RING 126 SUSP 127 GPIO21 I/O SIOCF3, Bits 2-1 = 00 I I SIOCF4, Bit 0 = 0 SIOCF4, Bit 2 = 0 I/O SIOCF3, Bit 0 = 0 I/O Configuration Signal DCD2 DSR2 SIN2 RTS2 SOUT2 CTS2 DTR2/BOUT2 PME1 PME2 FANOUT0 P12 PNF 128 GPIO22 I/O SIOCF3, Bits 4-3 = 00 FANOUT1 IRRX2/IRSL0 P17 I/O I I I O O I O I I SIOCF4, Bit 0 = 1 SIOCF4, Bit 2 = 1 SIOCF3, Bit 0 = 1 Configuration Alternate I/O SIOCF3, Bits 2-1 = 01 I/O SIOCF3, Bits 2-1 = 10 I/O SIOCF3, Bits 2-1 = 11 I/O SIOCF3, Bits 4-3 = 01 I/O SIOCF3, Bits 4-3 = 10 I/O SIOCF3, Bits 4-3 = 11 1.4 1.4.1 DETAILED SIGNAL/PIN DESCRIPTIONS Clock Pin/s 45 I/O I Buffer Type INT Description Clock In. A 48MHz clock input. Signal CLKIN 1.4.2 Fan Speed Control Pin/s 127, 128 I/O O Buffer Type O2/20 Description Fan Output 0, 1. Pulse Width Modulation (PWM) signals, that are used to control the speed of cooling fans by controlling the voltage supplied to the fan’s motor. Signal FANOUT0 FANOUT1 1.4.3 FDC (Including PPM) The Parallel-Port/FDC MUX (PPM) provides a means to connect an external FDD on the Parallel Port connector, in addition to the internal FDD on the FDC header. This is done by physically connecting internally each FDC pin to a corresponding Parallel Port pin while isolating it from the Parallel Port logic. The Parallel Port becomes an additional connecting point to the FDC interface as long as the PPM is in active mode. The functional descriptions in this table apply to both the FDC pin and to the corresponding PPM pin. For a detailed description of PPM functionality, see Section 2.5. 17 www.national.com DETAILED SIGNAL/PIN DESCRIPTIONS 1.0 Signal/Pin Connection and Description (Continued) Signal DENSEL Pin/s 74 I/O O Buffer Type O4/24 Description Density Select. Indicates that a high FDC density data rate (500 Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is selected. DENSEL polarity is controlled by bit 5 of the FDC Configuration Register. This pin provides an additional density select signal in PPM mode when PNF = 0. 94 DIR 67 O OD24-O4/24 Direction. Determines the direction of the Floppy Disk Drive (FDD) head movement (active = step in, inactive = step out) during a seek operation. During reads or writes, DIR is inactive. This pin provides an additional direction signal in PPM mode when PNF = 0. 90 DR0 DR1 69 70 80 DRATE0 73 O O6/12 O O OD24-O4/24 OD24-O4/24 Drive Select 0. Decoded drive select output signal. DR0 is controlled by Digital Output Register (DOR) bit 0. Drive Select 1. Decoded drive select output signal. DR1 is controlled by Digital Output Register (DOR) bit 1. This pin provides an additional drive select 1 signal in PPM mode when PNF = 0. Data Rate 0. Reflects the value of bit 0 of the Configuration Control Register (CCR) or the Data Rate Select Register (DSR), whichever was written to last. Output from the pin is totem-pole buffered. This pin provides an additional FDC data rate signal in PPM mode, when PNF = 0. 82 DSKCHG 59 I INT Disk Change. Indicates if the drive door has been opened. The state of this pin is stored in the Digital Input Register (DIR). This pin can also be configured as the RGATE data separator diagnostic input signal via the MODE command. This pin provides an additional FDC Disk Change signal in PPM Mode when PNF = 0. 84 HDSEL 60 92 INDEX 72 93 MSEN0, MSEN1 MTR0 82, 80 71 I O INT OD24, O4/24 I INT O OD24, O4/24 Head Select. Determines which side of the FDD is accessed. Active low selects side 1, inactive selects side 0. This pin provides an additional head select signal in PPM mode when PNF = 0. Index. Indicates the beginning of an FDD track. This pin provides an additional index signal in PPM mode when PNF = 0. Media Sense Signals 0 and 1. Provide media sense signals only in PPM mode when PNF = 0. Motor Select 0. Active low, motor enable line for drive 0, controlled by bits D7-4 of the Digital Output Register (DOR). This signal is not available on the PPM, assuming that the external FDD is either drive 1 or 3. Motor Select 1. Active low, motor enable line for drive 1, controlled by bits D7-4 of the Digital Output Register (DOR). This pin provides an additional motor select 1 signal in PPM mode when PNF = 0. This pin is the motor enable line for drive 1 or drive 0, according to the TDR Register. MTR1 68 79 O OD24, O4/24 RDATA 61 87 I INT Read Data. Raw serial input data stream read from the FDD. This pin provides an additional read data signal in PPM mode when PNF = 0. www.national.com 18 DETAILED SIGNAL/PIN DESCRIPTIONS 1.0 Signal/Pin Connection and Description Signal STEP Pin/s 66 88 TRK0 63 91 WDATA 65 O OD24, O4/24 I INT I/O O Buffer Type OD24, O4/24 (Continued) Description Step. Issues pulses to the disk drive at a software programmable rate to move the head during a seek operation. This pin provides an additional step signal in PPM mode when PNF = 0. Track 0. Indicates to the controller that the head of the selected floppy disk drive is at track 0. This pin provides an additional Track 0 signal in PPM Mode when PNF = 0. Write Data. Carries out the write pre-compensated serial data that is written to the selected floppy disk drive. Pre-compensation is software selectable. This pin provides an additional WDATA signal in PPM mode when PNF = 0. 78 WGATE 64 O OD24, O4/24 Write Gate. Enables the write circuitry of the selected disk drive. WGATE is designed to prevent glitches during power up and power down. This prevents writing to the disk when power is cycled. This pin provides an additional WGATE signal in PPM mode when PNF = 0. 77 WP 62 I INT Write Protected. Indicates that the disk in the selected drive is write protected. A software programmable configuration bit (FDC configuration at Index F0h, Logical Device 0) can force an active write-protect indication to the FDC regardless of the status of this pin. This pin provides an additional WP signal in PPM mode when PNF = 0. 89 1.4.4 General-Purpose Input/Output (GPIO) Ports Pin/s I/O I/O Buffer Type INTS/ OD12, O6/12 Description General-Purpose I/O Port 1, bits 0-7. Each pin is configured independently as input or I/O, with or without static pull-up, and with either open-drain or totem-pole output type. The port support interrupt assertion and each pin can be enabled or masked as interrupt source. These pins provide alternate GPIO location options. I/O INTS/ OD12, O6/12 General-Purpose I/O Port 2, bits 0-2. Same as Port 1. Signal GPIO17 98 GPIO16-10 43-37 GPIO 16-10 119-117, 115-112 GPIO22-20 128, 127, 99 19 www.national.com DETAILED SIGNAL/PIN DESCRIPTIONS 1.0 Signal/Pin Connection and Description 1.4.5 Host Interface Pin/s 11-16, 19-28 29 45 50, 52, 53 47-49 30 31 32 I/O I I I/O I Buffer Type INT INT INT/O15/24 INT (Continued) Signal A15-A0 AEN D7-D0 DACK1-3 Description Address. These address lines of the ISA bus determine which internal register is accessed. A15-A0 are don’t cares during DMA transfer. Address Enable. This input disables function selection via A15-A0 when it is high. Access during DMA transfer is NOT affected by this pin. Data. Bi-directional data lines of the ISA bus. D7 is the MSB and D0 is the LSB. DMA Acknowledge 1, 2 and 3. These active low signals acknowledge a request for DMA services and enable the IORD and the IOWR input signals during DMA transfer. DMA Request 1, 2, and 3. These active high output signals inform the DMA controller that a data transfer is needed. I/O Channel Ready. This is the I/O channel ready open drain output signal. When IOCHRDY is driven low, the EPP extends the host cycle. I/O Read. An active low RD input signal indicates that the microprocessor has read data. I/O Write. WR is an active low input signal that indicates a write operation from the microprocessor to the controller. Interrupt Request 1, 3-7, 9, 11-12. IRQ polarity and output type selection is software configurable by the logical device mapped to the IRQ line. Master Reset. An active high MR input signal resets the device with its default settings. PCI Clock. Up to 33 MHz. Serial IRQ. Encoded interrupts on a serial line. DMA Terminal Count. The DMA controller issues TC to indicate the termination of a DMA transfer. TC is accepted only when a DACK signal is active. TC is active high in PC-AT mode, and active low in PS/2 mode. DRQ1-3 IOCHRDY IORD IOWR O O I I I/O I I I/O I O15/24 OD24 INTS INTS INT/ OD24, O15/24 INTS INPCI INT/O15/24 INT IRQ1,3-7, 9, 34,35, 37-43 11-12 MR PCICLK SERIRQ TC 46 34 35 54 1.4.6 Infrared (IR) Pin/s 57 I/O I Buffer Type INT INT/O6/12 Description IR Reception 1. Primary input to receive serial data from the IR transceiver module. IRRX2 - IR Reception 2. Auxiliary IR receiver input to support two transceiver modules. IRSL0 - IR Control Signals 0. Output to control the IR analog front end. IR Transmit. IR serial output data. Signal IRRX1 IRRX2/ IRSL0 IRTX 41, 128 I/O 56 O O6/12 www.national.com 20 DETAILED SIGNAL/PIN DESCRIPTIONS 1.0 Signal/Pin Connection and Description 1.4.7 Keyboard and Mouse Controller (KBC) Pin/s 99 100 I/O I/O I/O Buffer Type INTS/OD4 INTS/OD4 (Continued) Signal GA20 KBCLK Description Gate A20. KBC gate A20 (P21) output. Keyboard Clock. Transfers the keyboard clock between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P26 signal, and is connected internally to the T0 signal of the KBC. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. However, to enable the activity during power off, it must be pulled up to Keyboard and Mouse standby voltage. Keyboard Data. Transfers the keyboard data between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P27 signal, and is connected internally to KBC P10. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity, it must be pulled up to Keyboard and Mouse standby voltage. KBD Reset. Keyboard Reset (P20) output. Mouse Clock. Transfers the mouse clock between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P23 signal, and is connected internally to KBC’s T1. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity, it must be pulled up to Keyboard and Mouse standby voltage. Mouse Data. Transfers the mouse data between the SuperI/O chip and the external keyboard using the PS/2 protocol. This pin is driven by the internal, inverted KBC P22 signal, and is connected internally to KBC’s P11. External pull-up resistor to 5V is required (for PS/2 compliance). The pin is monitored for wake-up event detection. To enable the activity, it must be pulled up to Keyboard and Mouse standby voltage. I/O Port. KBC open-drain signal for general-purpose input and output, controlled by KBC firmware. I/O Port. KBC open-drain signal for general-purpose input and output, controlled by KBC firmware. KBDAT 101 I/O INTS/OD4 KBRST MCLK 98 102 I/O I/O INTS/OD4 INTS/OD4 MDAT 103 I/O INTS/OD4 P12 P17 42, 98, 127 41, 42, 128 I/O I/O INTS/OD4 INTS/OD4 21 www.national.com DETAILED SIGNAL/PIN DESCRIPTIONS 1.0 Signal/Pin Connection and Description 1.4.8 Parallel Port Pin/s 80 94 I/O I O Buffer Type INT OD14, O14/14 (Continued) Signal ACK AFD/ DSTRB Description Acknowledge. Pulsed low by the printer to indicate that it has received data from the Parallel Port. AFD - Automatic Feed. When low, instructs the printer to automatically feed a line after printing each line. This pin is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pullup resistor should be attached to this pin. DSTRB - Data Strobe (EPP). Active low, used in EPP mode as a data strobe. Busy. Set high by the printer when it cannot accept another character. Wait. In EPP mode, the Parallel Port device uses this active low signal to extend its access cycle. Error. Set active low by the printer when it detects an error. Initialize. When low, initializes the printer. This signal is in TRI-STATE after a 1 is loaded into the corresponding control register bit. Use an external 4.7 KΩ pull-up resistor. Parallel Port Data. Transfer data to and from the peripheral data bus and the appropriate Parallel Port data register. These signals have a high current drive capability. Paper End. Set high by the printer when it is out of paper. This pin has an internal weak pull-up or pull-down resistor. Printer Not Floppy. This input from the Parallel Port connector is used to detect that a floppy drive is connected to the Parallel Port, and to activates the PPM. The PNF pin is driven to 1 when a parallel device is connected, and to 0 when external FDD is connected. This pin is functional only when the PPM mode is enabled. Select. Set active high by the printer when the printer is selected. SLIN - Select Input. When low, selects the printer. This signal is in TRISTATE after a 0 is loaded into the corresponding control register bit. Uses an external 4.7 KΩ pull-up resistor. ASTRB - Address Strobe (EPP). Active low, used in EPP mode as an address strobe. STB - Data Strobe. Indicates to the printer that valid data is available at the printer port. This signal is in TRI-STATE after a 0 is loaded into the corresponding control register bit. An external 4.7 KΩ pull-up resistor should be employed. WRITE - Write Strobe. In EPP mode, this active low signal is a write strobe. BUSY/WAIT 79 I INT ERR INIT 92 90 I O INT OD14-O14/14 PD7-0 81-84, 87, 89, 91, 93 78 98, 127 I/O INT/ OD14, O14/14 INT INT PE PNF I I SLCT SLIN/ ASTRB 77 88 I O INT OD14, O14/14 STB/ WRITE 95 O OD14, O14/14 1.4.9 Power and Ground Pin/s 122 Buffer Type INULR Description Battery Power Supply. Provides battery back-up to the System Wake-Up Control registers, when VSB is lost (power-fail). The pin is connected to the internal logic through a series resistor for UL protection. Main 5V Power Supply. Standby Power Supply. Provides 5V power to the Wake-Up Control circuitry, while the main power supply is turned off. Ground. Signal VBAT VDD VSB VSS 17, 86 123 18, 51, 85, 116 PWR PWR GND www.national.com 22 DETAILED SIGNAL/PIN DESCRIPTIONS 1.0 Signal/Pin Connection and Description 1.4.10 Serial Ports 1 and 2 Signal CTS1, CTS2 DCD1, DCD1 DSR1, DSR2 DTR1/ BOUT1, DTR2/ BOUT2 Pin/s 109, 118 3, 94 105, 113 110, 119 I/O I I I O Buffer Type INTS INTS INTS O6/12 (Continued) Description Clear to Send. When low, indicate that the modem or other data transfer device is ready to exchange data. Data Carrier Detected. When low, indicate that the modem or other data transfer device has detected the data carrier. Data Set Ready. When low, indicate that the data transfer device, e.g., modem, is ready to establish a communications link. Data Terminal Ready. When low, indicate to the modem or other data transfer device that the Serial Port is ready to establish a communications link. After system reset, these pins provides the DTR function, sets these signals to inactive high, and loopback operation holds them inactive. Baud Output. Provides the associated serial channel baud rate generator output signal if test mode is selected, i.e., bit 7 of the EXCR1 Register is set. DTR1/BOUT1 is used also as BADDR. Ring Indicators (Modem). When low, indicate that a telephone ring signal has been received by the modem. These pins may issue wake-up event. Request to Send. When low, indicate to the modem or other data transfer device that the corresponding Serial Port is ready to exchange data. A system reset sets these signals to inactive high, and loopback operation holds them inactive. Serial Input. Receive composite serial data from the communications link (peripheral device, modem or other data transfer device). Serial Output. Send composite serial data to the communications link (peripheral device, modem or other data transfer device). The SOUT2,1 signals are set active high after system reset. RI1, RI2 RTS1, RTS2 111, 120 107, 115 I O INTS O6/12 SIN1, SIN2 SOUT1, SOUT2 106, 114 108, 117 I O INTS O6/12 1.4.11 Strapping Signal BADDR Pin/s 110 I/O I Buffer Type INSTRP Description Base Address Strap. Determines the base address of the Index and Data registers. It is pulled down by an internal 30 Kohm resistor to get base address 2Eh for the Index register, and 2Fh for the Data register. If the respective base addresses are 15Ch and 15Dh, use an external 10 Kohm pull-up resistor (to VDD). 1.4.12 System Wake-Up Control Signal PME1, PME2 PWUREQ Pin/s 125, 126 124 I/O I O Buffer Type INTS OD6/12 Description Power Management Event 1, 2. Detection of an event on PME1 or PME2 may activate the PWUREQ signal (wake-up event). Power Up Request. Low level (active) indicates that wake-up event has occurred. This may cause the chipset to turn the power supply on, or to exit its current sleep state. The open-drain output must be pulled up to VSB, in order to function during power-off. Telephone Line Ring. Detection of a pulse-train on the RING pin, is a wake-up event that can activate the power-up request (PWUREQ). Suspend Power. Power Supply On control signal. RING SUSP 125 126 I I INTS INTS 23 www.national.com FDC Internal Bus Control Signals GPIO17-10 GPIO22-20 Figure 2-1. Detailed PC87351 Block Diagram www.national.com 24 D7-0 A15-0 AEN IORD IOWR IOCHRDY PCICLK SERIRQ BADDR CLKIN MR 2.0 Device Architecture and Configuration 2.0 Device Architecture and Configuration The SuperI/O device comprises a collection of generic functional blocks. Each functional block is described in a separate chapter in this book. However, some parameters in the implementation of each functional block may vary per SuperI/O device. This chapter describes the PC87351 structure and provides all device specific information, including special implementation of generic blocks, host interface and device configuration. 2.1 OVERVIEW The PC87351 consists of 9 logical devices, a host interface, and a central configuration register set, all built around a central, internal bus. The internal bus is a replication of an 8-bit ISA bus protocol. The host interface serves as a bridge between the external ISA interface and the internal bus. It supports 8-bit I/O read, 8bit I/O write and 8-bit DMA transactions, as defined in Personal Computer Bus Standard P996. The central configuration register set supports ACPI compliant PnP configuration. The configuration registers are structured as a subset of the Plug and Play Standard Registers, defined in Appendix A of the Plug and Play ISA Specification Version 1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space, DMA channels and IRQ lines) are configured in, and managed by, the central configuration register set. In addition, some function-specific parameters are configurable through this unit and distributed to the functional blocks through special control signals. FANOUT0 FANOUT1 VBAT VSB PME1 PME2 SUSP RING PWUREQ STB/WRITE PD0/INDEX PD1/TRK0 PD2/WP PD3/RDATA PD4/DSKCHG PD5/MSEN0 PD6/DRATE0 PD7/MSEN1 ACK/DR1 BUSY/MTR1/WAIT PE/WDATA SLCT/WGATE AFD/DENSEL/DSTRB ERR/HDSEL INIT/DIR SLIN/STEP/ASTRB PNF Fan Speed Control System Wake-Up Serial Port 1 PPM Parallel Port Serial Port 2 with IR SIN1 SOUT1 RTS1 DTR1/BOUT1 CTS1 DSR1 DCD1 RI1 SIN2 SOUT2 RTS2 DTR2/BOUT2 CTS2 DSR2 DCD2 RI2 IRRX2,1 IRTX IRSL0 P12,P17 GA20, KBRST KBCLK KBDAT MDAT MCLK Configuration and Control Registers RDATA WDATA WGATE HDSEL DIR STEP TRK0 INDEX DSKCHG WP MTR1,0 DR1,0 DENSEL DRATE0 Keyboard and Mouse Controller GPIO Ports Host Interface TC DACK3-1 DRQ3-1 IRQ9,11-12 IRQ1,3-7 CONFIGURATION STRUCTURE AND ACCESS 2.0 Device Architecture and Configuration 2.2 2.2.1 CONFIGURATION STRUCTURE AND ACCESS The Index-Data Register Pair (Continued) This section describes the structure of the configuration register file, and the method of accessing the configuration registers. The SuperI/O configuration access is performed via an Index-Data register pair, using only two system I/O byte locations. The base address of this register pair is determined during reset, according to the state of the hardware strapping option on the BADDR pin. Table 2-1 shows the selected base addresses as a function of BADDR. Table 2-1. BADDR Strapping Options I/O Address BADDR Index Register 0 1 002Eh 015Ch Data Register 002Fh 015Dh The Index Register is an 8-bit R/W register located at the selected base address (Base+0). It is used as a pointer to the configuration register file, and holds the index of the configuration register that is currently accessible via the Data Register. Reading the Index Register returns the last value written to it (or the default of 00h after reset). The Data Register is an 8-bit virtual register, used as a data path to any configuration register. Accessing the data register results with physically accessing the configuration register that is currently pointed by the index register. 2.2.2 Banked Logical Device Registers Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks, where each bank holds the standard PnP configuration registers of the corresponding logical device. Table 2-2 shows the LDNs of the device functional blocks. Figure 2-2 shows the structure of the standard PnP configuration register file. The SIO Control and Configuration registers are not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and device configuration registers are duplicated over 9 banks for 9 logical devices. Therefore, accessing a specific register in a specific bank is performed by two dimensional indexing, where the LDN Register selects the bank (or logical device) and the Index Register selects the register within the bank. Accessing the Data Register while the Index Register holds a value of 30h or higher results in a physical access to the configuration register currently pointed to by the Index Register, within the logical device currently selected by the LDN Register. 07h 20h 2Eh 30h 60h 63h 70h 71h 74h 75h F0h F2h 9 Banks - One per Logical Device Logical Device Number Register SuperI/O Configuration Registers Logical Device Control Register Logical Device Configuration PnP Standard Registers Bank Select Logical Device Configuration Special (Vendor-defined) Registers Figure 2-2. Structure of the PnP Standard Registers 25 www.national.com CONFIGURATION STRUCTURE AND ACCESS 2.0 Device Architecture and Configuration (Continued) Table 2-2. Logical Device Number (LDN) Assignments LDN 00h 01h 02h 03h 04h 05h 06h 07h 08h Functional Block Floppy Disk Controller (FDC) Parallel Port Serial Port 2 with IR Serial Port 1 System Wake-Up Control (SWC) Keyboard and Mouse Controller (KBC) - Mouse interface Keyboard and Mouse Controller (KBC) - Keyboard interface General-Purpose I/O (GPIO) Fan Speed Control (FSC) When accessing unimplemented registers (i.e. accessing the Data Register while the Index Register points to a non-existing register or the LDN is higher than 08h), write is ignored and read returns 00h on all addresses except for 74h, 75h (PnP DMA Configuration Registers) which returns 04h (no DMA channel is active). The configuration registers are accessible immediately after reset. 2.2.3 Standard PnP Register Definitions Tables 2-3 through 2-8 describe the standard PnP registers. For more detailed information on these registers, refer to the Plug and Play ISA Specification, Version 1.0a, May 5, 1994. Unless otherwise noted: • • • All registers are read/write. All reserved bits return 0 on reads. To prevent unpredictable results, they must not be modified. Using read-modifywrite is recommended to prevent the values of reserved bits from being changed during write. Write only registers should not use read-modify-write during updates. Table 2-3. PnP Standard Control Registers Index 07h 20h - 2Fh Name Logical Device Number SuperI/O Configuration Registers Description This register selects the current logical device. SuperI/O Configuration Registers and ID Registers Table 2-4. PnP Logical Device Control Registers Index 30h Name Activate Description Bit 0 - Logical Device Activation Control 0: Disabled 1: Enabled Bits 7-1 - Reserved www.national.com 26 CONFIGURATION STRUCTURE AND ACCESS 2.0 Device Architecture and Configuration (Continued) Table 2-5. PnP I/O Space Configuration Registers Index 60h Name Description I/O Port Base Indicates selected I/O lower limit address bits 15-8 for I/O descriptor 0 Address Bits (15-8) Descriptor 0 I/O Port Base Indicates selected I/O lower limit address bits 7-0 for I/O descriptor 0 Address Bits (7-0) Descriptor 0 I/O Port Base Indicates selected I/O lower limit address bits 15-8 for I/O descriptor 1 Address Bits (15-8) Descriptor 1 I/O Port Base Indicates selected I/O lower limit address bits 7-0 for I/O descriptor 1 Address Bits (7-0) Descriptor 1 Table 2-6. PnP Interrupt Configuration Registers 61h 62h 63h Index 70h Name Description Interrupt Request Indicates selected interrupt number Number Select Bits 3-0 select the interrupt number. A value of 1 selects IRQ1, a value of 2 selects IRQ2, etc. (up to IRQ15). IRQ0 is not a valid interrupt selection. Interrupt Request Indicates the type and level of the interrupt request number selected in the previous Type Select register Bit 0 - Type of interrupt request selected in previous register 0: Edge 1: Level Bit 1 - Level of interrupt request selected in previous register 0: Low polarity 1: High polarity Table 2-7. PnP DMA Configuration Registers 71h Index 74h Name DMA Channel Select 0 Description Indicates selected DMA channel for DMA 0 Bits 2-0 select the DMA channel for DMA 0. The valid choices are 1-3, where a value of 1 selects DMA channel 1, 2 selects DMA channel 2, etc. A value of 4 indicates that no DMA channel is active. The values 5-7 are reserved. Indicates selected DMA channel for DMA 1 Bits 2-0 select the DMA channel for DMA 1. The valid choices are 1-3, where a value of 1 selects DMA channel 1, 2 selects DMA channel 2, etc. A value of 4 indicates that no DMA channel is active. The values 5-7 are reserved. 75h DMA Channel Select 1 Table 2-8. PnP Logical Device Configuration Registers Index F0h-FEh Name Logical Device Configuration Vendor-defined Description 27 www.national.com CONFIGURATION STRUCTURE AND ACCESS 2.0 Device Architecture and Configuration 2.2.4 Overview of PnP Standard Registers Index 07h 20h 21h SuperI/O Control and Configuration Registers 22h 23h 24h 27h 2Eh 30h 60h 61h 62h 63h Logical Device Control and Configuration Registers one per logical device (some are optional) 70h 71h 74h 75h F0h F1h F2h (Continued) Name Logical Device Number Register SuperI/O ID Register SuperI/O Configuration 1 Register SuperI/O Configuration 2 Register SuperI/O Configuration 3 Register SuperI/O Configuration 4 Register SuperI/O Revision ID Register Reserved exclusively for National use Logical Device Control Register (Activate) I/O Base Address Descriptor 0 Bits 15-8 I/O Base Address Descriptor 0 Bits 7-0 I/O Base Address Descriptor 1 Bits 15-8 I/O Base Address Descriptor 1 Bits 7-0 IRQ Number Select IRQ Type Select DMA Channel Select 0 DMA Channel Select 1 Device Specific Logical Device Configuration 1 Device Specific Logical Device Configuration 2 Device Specific Logical Device Configuration 3 Figure 2-3. PnP Register Map SuperI/O Control and Configuration Registers The only implemented PnP control register in the PC87351 is the Logical Device Number Register at index 07h. All the other standard PnP control registers are associated with PnP protocol for ISA add-in cards, and are not supported by the PC87351. The SuperI/O Configuration registers at indexes 20h and 27h are mainly used for part identification, global power management and the selection of pin multiplexing options. For details, see Section 2.5. Logical Device Control and Configuration Registers A subset of these registers is implemented for each logical device. Control The only implemented logical device control register is the activate register at index 30. Bit 0 of the activate register controls the activation of the associated function block. Activation of the block enables access to the block’s registers, and attaches its system resources, which are unused as long as the block is not activated. Other effects may apply, on a function-specific basis (such as clock enable and active pinout signaling). Standard Configuration The standard configuration registers are used to manage the PnP resource allocation to the functional blocks. The I/O port base address descriptor 0 is a pair of registers at Index 60-61, holding the (first or only) 16-bit base address for the register set of the functional block. An optional second base-address (descriptor 1) at index 62-63 is used for devices with more than one continuous register set. IRQ Number Select (index 70h) and IRQ Type Select (index 71h) allocate an IRQ line to the block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where applicable. DMA Channel Select 1 (index 75h) allocates a second DMA channel, where applicable. www.national.com 28 CONFIGURATION STRUCTURE AND ACCESS 2.0 Device Architecture and Configuration Special Configuration (Continued) The vendor-defined registers, starting at index F0h are used to control function-specific parameters such as operation modes, power saving modes, pin TRI-STATE, clock rate selection, and non-standard extensions to generic functions. 2.2.5 Default Configuration Setup The device has four reset types, described below. See specific register descriptions for bits affected by each register type. • • • Software Reset This reset is enabled by bit 1 of the SIOCF1 Register, which resets all logical devices. A software reset also resets most bits in the SuperI/O Configuration and Control Registers. Hardware Reset This reset is activated by the assertion of the MR input. It resets all logical devices, with the exception of the SWC. It also resets all SuperI/O Configuration and Control Registers, with the exception of the SIOCF4 Register. VPP Power-Up Reset This reset is activated when either VSB or VBAT is powered on after both have been off. VPP is an internal voltage which is a combination of VSB and VBAT. VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in the Device Characteristics chapter; otherwise, VBAT is used as the VPP source. This reset resets all registers whose values are retained by VPP. VSB Power-Up Reset This is an internally generated reset that resets the SWC, excluding those SWC registers whose values are retained by VPP. In the event of a hardware reset: — The configuration base address is 2Eh or 15Ch, according to the BADDR strap pin value, as shown in Table 2-1. — The Keyboard Controller (KBC) is active and all other logical devices are disabled, with the exception of the SWC which remains functional but whose registers cannot be accessed. — All the multiplexed GPIO pins, except KBRST/GPIO17/P12/PNF and GA20/GPIO20, are configured as GPIO pins and are in TRI-STATE (default direction is input). KBRST/GPIO17/P12/PNF is configured as KBRST and GA20/GPIO20 is configured as GA20. • • The PC87351 wakes up with the default setup, as follows: • In the event of either a hardware or a software reset: — The legacy devices are assigned with their legacy system resource allocation. — The National proprietary functions are not assigned with any default resources and the default values of their base addresses are all 00h. 2.2.6 Address Decoding A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional blocks. However, the number of configurable bits in the base address registers vary for each device. The lower 1, 2, 3 or 4 address bits are decoded within the functional block to determine the offset of the accessed register, within the device’s I/O range of 2, 4, 8 or 16 bytes, respectively. The rest of the bits are matched with the base address register to decode the entire I/O range allocated to the device. Therefore the lower bits of the base address register are forced to 0 (read-only), and the base address is forced to be 2, 4, 8 or 16 byte aligned, according to the size of the IO range. The base address of the FDC, Serial Port 1, Serial Port 2 and KBC are limited to the I/O address range of 00h to 7FXh only (bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses of the non-legacy devices are configurable within the full 16-bit address range (up to FFFXh). In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the PP). The KBC has two I/O descriptors with some implied dependency between them. For more details, please see the detailed description of the base address register for each specific logical device. 2.2.7 The Internal Clocks The source of the device internal clocks is a 48 MHz clock signal, which is routed through the CLKIN pin. Wake-up on KBD, Mouse and RING pulse train detection operates on internally generated clock. 29 www.national.com REGISTER TYPE ABBREVIATIONS 2.0 Device Architecture and Configuration 2.3 REGISTER TYPE ABBREVIATIONS (Continued) The register maps in this chapter use the following abbreviations for Type: • R/W = Read/Write • • • • 2.4 R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. W = Write RO = Read Only R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. SUPERI/O CONFIGURATION AND CONTROL REGISTERS SuperI/O Register Map This section describes the registers with first level indexes in the range 07h - 2Fh. 2.4.1 Index Mnemonic 07h 20h 21h 22h 23h 24h 27h LDN SID SIOCF1 SIOCF2 SIOCF3 SIOCF4 SRID Name Logical Device Number Register SuperI/O ID Register SuperI/O Configuration 1 Register SuperI/O Configuration 2 Register SuperI/O Configuration 3 Register SuperI/O Configuration 4 Register SuperI/O Revision ID Register Type R/W RO R/W R/W R/W R/W RO Section 2.2.2 2.4.2 2.4.3 2.4.5 2.4.6 2.4.7 2Eh Reserved exclusively for National use 2.4.2 SuperI/O ID Register (SID) Index 20h RO 7 1 6 1 5 1 4 Chip ID 0 0 0 1 0 3 2 1 0 This register contains the identity number of the chip. The PC87351 is identified by the value E2h. Location: Type: Bit Name Reset www.national.com 30 SUPERI/O CONFIGURATION AND CONTROL REGISTERS 2.0 Device Architecture and Configuration 2.4.3 Type: Bit Name Reset SuperI/O Configuration 1 Register (SIOCF1) Index 21h R/W 7 6 5 Lock Scratch 0 Location: (Continued) 4 PNF Status 1 3 Reserved 0 2 Pin Function Lock 0 1 SW Reset 0 0 Global Device Enable 1 General Purpose Scratch 0 0 Bit 7-6 5 Description General Purpose Scratch. When bit 5 is set to 1, these bits are read only. After reset, these bits can be read or write. Once changed to read only, the bits can be changed back to read/write only by a hardware reset. Lock Scratch. This bit controls bits 7 and 6 of this register. Once this bit is set to 1 by software, it can be cleared to 0 only by a hardware reset. 0: Bits 7 and 6 of this register are read/write bits (default). 1: Bits 7 and 6 of this register are read only bits. PNF Status. This read only bit reflects the value of the PNF pin when PPM mode is enabled. If PPM mode is disabled, this bit is 1. Data written to this bit is ignored. Reserved Pin Function Lock. When this bit is set to 1, all function selection on the associated pins is locked: 4 3 2 • • • All bits of the SIOCF2 Register Bits 4-0 of the SIOCF3 Register Bits 3-0 of the SIOCF4 Register. When this bit is set to 1 by software, it can only be cleared to 0 by MR or power-off. 0: No effect (default) 1: Pin function locked 1 SW Reset. Read always returns 0. 0: Ignored (default) 1: Resets all the devices that are reset by MR (with the exception of the lock bits) and the registers of the SWC Global Device Enable. This bit controls the function enable of all the logical devices in the PC87351, except the SWC. It allows them to be disabled simultaneously by writing to a single bit. 0: All logical devices in the PC87351 disabled, except SWC 1: Each logical device enabled according to its Activate Register at index 30h (default) 0 31 www.national.com SUPERI/O CONFIGURATION AND CONTROL REGISTERS 2.0 Device Architecture and Configuration 2.4.4 SuperI/O Configuration 2 Register (SIOCF2) Index 22h R/W 7 Pin 99 Function Select 1 6 5 (Continued) This register controls pin multiplexing of pins: 34, 35, 37-43, 98 and 99. Location: Type: Bit Name Reset 4 3 2 1 0 Select Serial IRQ 1 Pin 98 Function Select 0 1 Pin 42 Function Select 0 0 Pin 41 Function Select 0 0 Bit 7 Pin 99 Function Select 0: GPIO20 1: GA20 (default). Pin 98 Function Select Bits 65 0 0 1 1 4-3 0 1 0 1 Function GPIO17 KBRST (default) P12 PNF (PPM mode enabled) Description 6-5 Pin 42 Function Select. The setting of bit 0 of this register effects the function selected, as follows: Bits 430 0 0 0 1 1 0 1 1 0 1 X 1 0 X X Function GPIO15 (default) GPIO15 IRQ11 P12 P17 2-1 Pin 41 Function Select. The setting of bit 0 of this register effects the function selected, as follows: Bits 210 0 0 0 1 1 0 1 1 0 1 X 1 0 X X Function GPIO14 (default) GPIO14 IRQ9 IRRX2/IRSL0 P17 0 Select Serial IRQ 0: Pins 34, 35, 37-40 and 43 function as IRQ1, IRQ3-7 and IRQ12, respectively 1: Pins 34 and 35 function as PCICLK and SERIRQ, respectively. Pins 37-40 and 43 function as GPIO (default). www.national.com 32 SUPERI/O CONFIGURATION AND CONTROL REGISTERS 2.0 Device Architecture and Configuration 2.4.5 SuperI/O Configuration 3 Register (SIOCF3) Index 23h R/W 7 6 Reserved 0 0 0 5 (Continued) This register controls multiplexing of pins: 112-115, 117-119 and 127-128. Location: Type: Bit Name Reset 0 Select Pin 128 Function Select Pin 127 Function Select Serial Port 2 0 0 0 0 0 4 3 2 1 Bit 7-5 4-3 Reserved Pin 128 Function Select Bits 43 0 0 1 1 2-1 0 1 0 1 Function GPIO22 (default) FANOUT1 IRRX2/IRSL0 P17 Description Pin 127 Function Select Bits 21 0 0 1 1 0 1 0 1 Function GPIO21 (default) FANOUT0 P12 PNF (PPM mode enabled) 0 Select Serial Port 2 0: Pins 112-115 and 117-119 function as GPIO10-16 (default) 1: Pins 112-115 and 117-119 function as Serial Port 2 33 www.national.com SUPERI/O CONFIGURATION AND CONTROL REGISTERS 2.0 Device Architecture and Configuration 2.4.6 SuperI/O Configuration 4 Register (SIOCF4) (Continued) This register controls the multiplexing of two pins. Its value is retained by VPP, and is not affected by either hardware or software reset. Location: Type: Bit Name Reset Index 24h R/W 7 SUSP Value X 6 5 4 3 PME2 Debounce Enable 1 2 Pin 126 Function Select 0 1 PME1 Debounce Enable 1 0 Pin 125 Function Select 0 General Purpose Scratch 0 0 0 Bit 7 6-4 3 Description SUSP Value. Last value of SUSP pin prior to VSB loss (power-fail). General Purpose Scratch. Battery-backed. PME2 Debounce Enable 0: Debounce disabled 1: 16mS debounce enabled (VPP power-up default) Pin 126 Function Select 0: Pin 126 functions as SUSP (VPP power-up default) 1: Pin 126 functions as PME2 2 1 PME1 Debounce Enable 0: Debounce disabled 1: 16mS debounce enabled (VPP power-up default) Pin 125 Function Select 0: RING (VPP power-up default) 1: PME1 0 2.4.7 SuperI/O Revision ID Register (SRID) Index 27h RO This read only register contains the identity number of the chip revision. SRID is incremented on each revision. Location: Type: www.national.com 34 PARALLEL PORT MULTIPLEXER (PPM) 2.0 Device Architecture and Configuration 2.5 PARALLEL PORT MULTIPLEXER (PPM) (Continued) The Parallel Port Multiplexer (PPM) logic allows connection of an external Floppy Disk Drive (FDD) through the Parallel Port connector (25-pin DIN), instead of, or in addition to, the internal FDD on the normal FDC header. This is done by turning the Parallel Port pins (normally used by the Parallel Port) into an additional set of FDC pins, while isolating them from the Parallel Port functionality. A printer (or any other parallel device) may be exchanged with an external FDD, without turning the system off. The PPM logic automatically detects whether a parallel device or the FDD is connected, and routes the Parallel Port pins to either the Parallel Port or the FDC functional blocks, accordingly. See Figure 2-4. PPM mode is enabled by selecting the PNF pin. When PPM mode is enabled, it is controlled by the PNF input pin, as follows: • • When PNF = 1, PPM is inactive and the Parallel Port pins are assigned Parallel Port functionality. When PNF = 0, PPM is active and the Parallel Port pins are assigned FDC functionality. When PPM mode is disabled, the Parallel Port pins are assigned Parallel Port functionality, regardless of the value of PNF. The internal FDD (on the normal FDC pins) and the external FDD (on the Parallel Port pins) can be assigned as Drive A and Drive B respectively, or vice versa. FDC Outputs FDC Pins FDC 0 1 PPM Active and Drive 1 or 3 Selected FDC Outputs FDC Inputs FDC Inputs PPM Active Parallel Port Pins Parallel Port Outputs Parallel Port Parallel Port Inputs 0 1 Default “Non-Connect” Parallel Port Input Values Figure 2-4. PPM Routing 2.5.1 PPM Mode The Parallel Port pins function as FDD interface for either drive 1 or drive 3. See Figure 2-4 for the internal routing between the PPM and FDC, and the Parallel Port and FDC pin-sets when PPM mode is active. The FDC output signals are driven simultaneously both on the normal FDC pins and on the corresponding Parallel Port pins. The FDC inputs are received from the FDC pins when either drive 0 or drive 2 are selected, and from the corresponding Parallel Port pins when either drive 1 or drive 3 is selected. The Parallel Port output signals are isolated from the Parallel Port pins. The Parallel Port input signals, as reflected by STR Register, assume their default values (BUSY = 1, PE = 0, SLCT = 0, ACK = 1), indicating that nothing is connected to the Parallel Port. 35 www.national.com PARALLEL PORT MULTIPLEXER (PPM) 2.0 Device Architecture and Configuration 2.5.2 TRI-STATE Control of Parallel Port Pins (Continued) Normally, the pins of most of the SuperI/O functions can be put in TRI-STATE when the function is disabled. If the TRISTATE control bit of a logical device (normally bit 0 of the Configuration Register at index F0) is set to 1, and its Activate bit (bit 0 of Activate Register at index 30) is cleared to 0, the output pins of that device are floating. The same is true for the Parallel Port pins, but TRI-STATE control depends on the current functionality of the pins. When the PPM is disabled or when a parallel device is connected to the port, then the TRI-STATE of the Parallel Port pins is controlled by the Parallel Port Activate bit and TRI-STATE control bit. However, when the PPM is enabled and the external FDD is connected (PNF=0), TRI-STATE is controlled by the corresponding FDC configuration bits. Table 2-9 shows the standard 25-pin, D-type connector definition for Parallel Port operations in PPM mode. Table 2-9. Parallel Port Connector Signal Multiplexing D-Type Connector Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 23 24 25 98 or 1271 Parallel Port PC87351 Pin Signal 95 93 91 89 87 84 83 82 81 80 79 78 77 94 92 90 88 STB/WRITE PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 ACK BUSY/WAIT PE SLCT AFD/DSTRB ERR INIT SLIN/ASTRB GND PNF = Ground GND I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I/O I I/O I/O TRK0 WP RDATA DSKCHG MSEN0 DRATE0 MSEN1 DR1 MTR1 WDATA WGATE DENSEL HDSEL DIR STEP GND PNF = 1 GND I Signal INDEX I/O I I I I I I I O I O O O O O O O O FDC 1. The PNF signal is the inverse of pin 24 of the connector (PNF). www.national.com 36 FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0 2.0 Device Architecture and Configuration 2.6 2.6.1 General Description (Continued) FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0 The generic FDC is a standard FDC with a digital data separator, and is DP8473 and N82077 software compatible. The FDC supports 14 of the 17 standard FDC signals on the normal FDD interface pins, as described in Section 2.4.1. Additionally, the FDC supports another 16 pins, multiplexed on the Parallel Port pins, for external FDD support. See Section 2.5.2 for details on these pins in PPM mode and Section 1.4.3 for signal/pin descriptions. Table 2-10. FDC Registers Offset 00h 01h 02h 03h 04h 05h 06h 07h The FDC is implemented as follows: DIR CCR Mnemonic SRA SRB DOR TDR MSR DSR FIFO Name Status Register A Status Register B Digital Output Register Tape Drive Register Main Status Register Data Rate Select Register Data (FIFO) Register N/A Digital Input Register Configuration Control Register Type RO RO R/W R/W R W R/W X R W • Automatic media sense is not supported on the standard FDC connector (MSEN0-1 pins are not implemented), but is supported instead on the Parallel Port pins. Configuration Index 30h 60h 61h 70h 71h 74h 75h F0h F1h Configuration Register or Action Activate. See also bit 0 of the SIOCF1 Register. Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b. Base Address LSB Register. Bits 2 and 0 (for A2 and A0) are read only, 00b. Interrupt Number Interrupt Type. Bit 1 is read/write; other bits are read only. DMA Channel Select Report no second DMA assignment FDC Configuration Register Drive ID Register Type R/W R/W R/W R/W R/W R/W R R/W R/W Reset 00h 03h F2h 06h 03h 02h 04h 24h 00h 2.6.2 37 www.national.com FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0 2.0 Device Architecture and Configuration 2.6.3 FDC Configuration Register This register is reset by hardware to 20h. Location: Index F0h Type: R/W Bit Name Reset Required 7 Four Drive Control 0 6 TDR Register Mode 0 5 DENSEL Polarity Control 1 (Continued) 4 Reserved 0 0 3 Write Protect 0 2 1 PC-AT or PS/2 Drive Reserved Mode Select 1 0 0 TRI-STATE Control 0 Bit 7 Description Four Drive Control 0: Two floppy drives directly controlled by DR1-0 and MTR1-0 (default) 1: Four floppy drives controlled with the aid of external logic TDR Register Mode 0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are ignored (default) 1: Enhanced drive mode DENSEL Polarity Control 0: Active low for 500 Kbps or 1 Mbps data rates 1: Active high for 500 Kbps or 1 Mbps data rates (default) Reserved. Must be 0. Write Protect. This bit allows forcing of write protect by software. When set, write to the floppy disk drive is disabled. This effect is identical to WP when it is active. 0: Write protected according to WP signal (default) 1: Write protected regardless of value of WP signal PC-AT or PS/2 Drive Mode Select 0: PS/2 drive mode 1: PC-AT drive mode (default) Reserved TRI-STATE Control. When disabled, this bit controls the TRI-STATE status of the logical device output pins. 0: Disabled (default) 1: Enabled when device inactive Drive ID Register 6 5 4 3 2 1 0 2.6.4 This read/write register is reset by hardware to 00h. These bits control bits 5 and 4 of the enhanced TDR Register. Location: Index F1h Type: R/W Bit Name Reset 7 0 6 Reserved 0 0 0 0 5 4 3 Drive 1 ID 0 0 2 1 Drive 0 ID 0 0 Bit 7-4 3-2 1-0 Reserved Description Drive 1 ID. These bits are reflected on bits 5 and 4 of the TDR Register, respectively, when drive 1 is accessed. Drive 0 ID. These bits are reflected on bits 5 and 4 of the TDR Register, respectively, when drive 0 is accessed. Usage Hints: Some BIOS implementations support automatic media sense FDD, and bit 5 of the TDR is interpreted as valid media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support automatic media sense, bits 1 and/or 3 of the Drive ID Register should be set to 1 respectively, to indicate non-valid media sense, when the corresponding drive is selected and the Drive ID bit is reflected on bit 5 of TDR. www.national.com 38 PARALLEL PORT - LOGICAL DEVICE 1 2.0 Device Architecture and Configuration 2.7 2.7.1 PARALLEL PORT - LOGICAL DEVICE 1 General Description (Continued) The PC87351 Parallel Port device offers a wide range of operational configurations. It utilizes the most advanced protocols in current use, while maintaining full backward compatibility to support existing hardware and software. It supports two Standard Parallel Port (SPP) modes of operation for parallel printer ports, two Enhanced Parallel Port (EPP) modes of operation, and one Extended Capabilities Port (ECP) mode. This versatility is achieved by user software control of the mode in which the device functions. The following table lists the Parallel Port Registers used in each mode of operation. Note: The Parallel Port does not support zero wait states. Table 2-11. Parallel Port Registers Classified by Mode Offset 00h 01h 02h 03h 04h 05h 06h 07h 400h SPP DTR STR CTR X X X X X X DTR STR CTR ADDR DATA0 DATA1 DATA2 DATA3 X EPP ECP DATAR (modes 0,1) AFIFO (mode 3) DSR DCR X X X X X CFIFO (mode 2) DFIFO (mode 3) TFIFO (mode 6) CNFGA (mode 7) CNFGB ECR EIR1 EDR1 EAR1 401h 402h 403h 404h 405h X X X X X X X X X X 1. These registers are extended, and not standard 1284 registers. They are accessible only when enabled by bit 4 of the Parallel Port Configuration Register (see Section 2.7.3). 2.7.2 Configuration Index Configuration Register or Action Type R/W R/W R/W R/W R/W Reset 00h 02h 78h 07h 02h 30h Activate. See also bit 0 of the SIOCF1 Register. 60h Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b. 61h Base Address LSB Register. Bits 1 and 0 (for A1 and A0) are read only, 00b. 70h Interrupt Number 71h Interrupt Type Bits 7-2 are read only. Bit 1 is a read/write bit. Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation mode and configured by the Parallel Port Configuration Register. This bit is set to 1 (level interrupt) in Extended Mode and cleared (edge interrupt) in all other modes. 74h DMA Channel Select 75h Report no second DMA assignment F0h Parallel Port Configuration Register R/W RO R/W 04h 04h F2h 39 www.national.com PARALLEL PORT - LOGICAL DEVICE 1 2.0 Device Architecture and Configuration 2.7.3 Parallel Port Configuration Register This register is reset by hardware to F2h. (Continued) Note: For normal operation and to maintain compatibility with future chips, do not change bits 7 through 4. Location: Type: Bit Name Reset Index F0h R/W 7 6 5 4 Extended Register Access 1 0 3 Reserved 0 2 1 Power Mode Control 1 0 TRI-STATE Control 0 Parallel Port Mode Select 1 1 1 Bit 7-5 Description Parallel Port Mode Select. Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled by bit 4 of the Control2 Configuration Register of the parallel port at offset 02h. Bits 765 000 001 010 011 100 101 110 111 Mode SPP Compatible; PD7-0 always output signals SPP Extended; PD7-0 direction controlled by software EPP 1.7 EPP 1.9 IEEE1284 (selects IEEE1284 register set), without embedded EPP support Reserved Reserved IEEE1284 (selects IEEE1284 register set), with EPP mode selectable as mode 4 (default) 4 Extended Register Access 0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored). 1: When ECP is selected by bits 7 through 5, the registers at base (address) + 403h, base + 404h and base + 405h are accessible. This option supports run-time configuration within the Parallel Port address space. Reserved Power Mode Control. When the logical device is active: 0: Parallel port clock disabled ECP modes and EPP time-out are not functional when the logical device is active. Registers are maintained. 1: Parallel port clock enabled All operation modes are functional when the logical device is active (default). TRI-STATE Control. This bit controls the TRI-STATE status of the logical device output pins when it is inactive (disabled). 0: Disabled (default) 1: Enabled when device inactive 3-2 1 0 Usage Hints: Parallel Port modes determine which address bits are used for register addresses. In SPP mode, 14 bits are used to decode Parallel Port base addresses. In ECP and EPP modes, 13 address bits are used. Table 2-11 shows which registers and address bits are used in each mode. The settings of the CTR Register bits listed below control selection of Parallel Port modes, as follows: • • When changing to ECP mode from any other mode, bit 2 must be set to 1, and bits 3 and 4 must be set to 0. When changing from SPP to EPP mode, bit 3 must be set to 0. www.national.com 40 SERIAL PORT 2 - LOGICAL DEVICE 2 2.0 Device Architecture and Configuration 2.8 2.8.1 2.8.2 SERIAL PORT 2 - LOGICAL DEVICE 2 General Description Configuration Index (Continued) Serial Port 2 includes IR functionality as described in the Serial Port 2 with IR chapter. Configuration Register or Action Type R/W R/W R/W R/W R/W R/W R/W R/W Reset 00h 02h F8h 03h 03h 04h 04h 02h 30h Activate. See also bit 0 of the SIOCF1 Register. 60h Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b. 61h Base Address LSB Register. Bit 2-0 (for A2-0) are read only, 000b. 70h Interrupt Number 71h Interrupt Type. Bit 1 is R/W; other bits are read only. 74h DMA Channel Select 0 (RX_DMA) 75h DMA Channel Select 1 (TX_DMA) F0h Serial Port 2 Configuration Register 2.8.3 Serial Port 2 Configuration Register Index F0h R/W 7 Bank Select Enable 0 0 0 6 5 Reserved 0 0 4 3 2 Busy Indicator 0 This register is reset by hardware to 02h. Location: Type: Bit Name Reset 1 Power Mode Control 1 0 TRI-STATE Control 0 Bit 7 Description Bank Select Enable. Enables bank switching for Serial Port 2. 0: All attempts to access the extended registers in Serial Port 2 are ignored (default). 1: Enables bank switching for Serial Port 2. Reserved Busy Indicator. This read only bit can be used by power management software to decide when to power-down the Serial Port 2 logical device. 0: No transfer in progress (default). 1: Transfer in progress. Power Mode Control. When the logical device is active in: 0: Low power mode Serial Port 2 Clock disabled. The output signals are set to their default states. The RI input signal can be programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also prevents access to Serial Port 2 registers.) 1: Normal power mode Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default). TRI-STATE Control. This bit controls the TRI-STATE status of the device output pins when it is inactive (disabled). One exception is the IRTX pin. It is driven to 0 when Serial Port 2 is inactive, and is not affected by this bit. 0: Disabled (default) 1: Enabled when device inactive 6-3 2 1 0 41 www.national.com SERIAL PORT 1 - LOGICAL DEVICE 3 2.0 Device Architecture and Configuration 2.9 2.9.1 SERIAL PORT 1 - LOGICAL DEVICE 3 Configuration Index (Continued) Configuration Register or Action Type R/W R/W R/W R/W R/W R/W R/W R/W Reset 00h 03h F8h 04h 03h 04h 04h 02h 30h Activate. See also bit 0 of the SIOCF1 Register. 60h Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b. 61h Base Address LSB Register. Bit 2-0 (for A2-0) are read only, 000b. 70h Interrupt Number 71h Interrupt Type. Bit 1 is R/W; other bits are read only. 74h Report no DMA Assignment 75h Report no DMA Assignment F0h Serial Port 1 Configuration Register 2.9.2 Serial Port 1 Configuration Register Index F0h R/W 7 Bank Select Enable 0 0 0 6 5 Reserved 0 0 4 3 2 Busy Indicator 0 This register is reset by hardware to 02h. Location: Type: Bit Name Reset 1 Power Mode Control 1 0 TRI-STATE Control 0 Bit 7 Description Bank Select Enable. Enables bank switching for Serial Port 1. 0: Disabled (default). 1: Enabled Reserved Busy Indicator. This read only bit can be used by power management software to decide when to power-down the Serial Port 1 logical device. 0: No transfer in progress (default). 1: Transfer in progress. Power Mode Control. When the logical device is active in: 0: Low power mode Serial Port 1 Clock disabled. The output signals are set to their default states. The RI input signal can be programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also prevents access to Serial Port 1 registers.) 1: Normal power mode Serial Port 1 clock enabled. Serial Port 1 is functional when the logical device is active (default). TRI-STATE Control. This bit controls the TRI-STATE status of the device output pins when it is inactive (disabled). One exception is the IRTX pin. It is driven to 0 when Serial Port 1 is inactive, and is not affected by this bit. 0: Disabled (default) 1: Enabled when device inactive 6-3 2 1 0 www.national.com 42 SYSTEM WAKE-UP CONTROL (SWC) - LOGICAL DEVICE 4 2.0 Device Architecture and Configuration 2.10 2.10.1 Configuration Index 30h 60h 61h 70h 71h 74h 75h (Continued) SYSTEM WAKE-UP CONTROL (SWC) - LOGICAL DEVICE 4 Configuration Register or Action Activate. When bit 0 is cleared, the registers of this logical device are not accessible.1 Base Address MSB Register Base Address LSB Register. Bits 3-0 (for A3-0) are read only, 0000b. Interrupt Number (For routing the PWUREQ signal). Interrupt Type. Bit 1 is read/write. Other bits are read only. Report no DMA assignment Report no DMA assignment Type R/W R/W R/W R/W R/W RO RO Reset 00h 00h 00h 00h 03h 04h 04h 1. The logical device registers are maintained, and all wake-up detection mechanisms are functional. 43 www.national.com KEYBOARD AND MOUSE CONTROLLER (KBC) - LOGICAL DEVICES 5 AND 6 2.0 Device Architecture and Configuration 2.11 2.11.1 General Description (Continued) KEYBOARD AND MOUSE CONTROLLER (KBC) - LOGICAL DEVICES 5 AND 6 The KBC is implemented physically as a single hardware module and houses two separate logical devices: a Mouse controller (logical device 5) and a Keyboard controller (logical device 6). The hardware KBC module is integrated to provide the following pin functions: P12, P17, KBRST (P20), GA20 (P21), KBDAT, KBCLK, MDAT, and MCLK. P12 and P17 are implemented as quasi bi-directional pins, meaning that they are driven high by the output buffer for a short period, following a low to high transition of the pins, and then left in TRI-STATE. KBRST and GA20 are implemented as bi-directional, open-drain pins. The Keyboard and Mouse interfaces are implemented as bidirectional, open-drain pins. Their internal connections are shown in Figure 2-5. P10, P11, P13-P16, P22-P27 of the KBC core are not available on dedicated pins; neither are T0 and T1. P10, P11, P22, P23, P26, P27, T0 and T1 are used to implement the Keyboard and Mouse interface. Internal pull-ups are implemented only on P12 and P17. The KBC executes a program fetched from an on-chip 2Kbyte ROM. The code programmed in this ROM is user-customizable. The KBC has two interrupt request signals: one for the Keyboard and one for the Mouse. The interrupt requests are implemented using ports P24 and P25 of the KBC core. The interrupt requests are controlled exclusively by the KBC firmware, except for the type and number, which are affected by configuration registers (see Section 2.11.2). The interrupt requests are implemented as bi-directional signals. When an I/O port is read, all unused bits return the value latched in the output registers of the ports. For KBC firmware that implements interrupt-on-OBF schemes, it is recommended to implement it as follows: 1. Put the data in DBBOUT. 2. Set the appropriate port bit to issue an interrupt request. KBC Internal Interface Bus KBD IRQ PnP Matrix Mouse IRQ P24 P25 STATUS DBBIN DBBOUT P12 P17 P20 P21 P26 T0 P27 P10 P23 T1 P22 P11 P12 P17 KBRST GA20 KBCLK KBDAT MCLK MDAT Figure 2-5. Keyboard and Mouse Interfaces www.national.com 44 KEYBOARD AND MOUSE CONTROLLER (KBC) - LOGICAL DEVICES 5 AND 6 2.0 Device Architecture and Configuration 2.11.2 Configuration Index 30h (Continued) Mouse Configuration Register or Action Activate. See also bit 0 of the SIOCF1. When the Mouse of the KBC is inactive, the IRQ selected by the Mouse Interrupt Number Register (index 70h) is not asserted. This register has no effect on host KBC commands handling the PS/2 Mouse. Mouse Interrupt Number Mouse Interrupt Type. Bits 1,0 are read/write; other bits are read only. Report no DMA assignment Report no DMA assignment Type R/W Reset 00h 70h 71h 74h 75h R/W R/W RO RO 0Ch 02h 04h 04h Index 30h 60h 61h 62h 63h 70h 71h 74h 75h F0h Keyboard Configuration Register or Action Activate. See also bit 0 of the SIOCF1. Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b. Base Address LSB Register. Bits 2-0 are read only 000b. Command Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b. Command Base Address LSB. Bits 2-0 are read only 100b. KBC Interrupt Number KBC Interrupt Type. Bits 1,0 are read/write; others are read only. Report no DMA assignment Report no DMA assignment KBC Configuration Register Type R/W R/W R/W R/W R/W R/W R/W RO RO R/W Reset 01h 00h 60h 00h 64h 01h 02h 04h 04h 40h 2.11.3 KBC Configuration Register This register is reset by hardware to 40h. Location: Type: Bit Name Reset Required Bit 7-6 Bits 76 0 0 1 1 5-1 0 0 1 0 1 Index F0h R/W 7 6 5 4 3 Reserved 0 0 0 0 0 0 2 1 0 TRI-STATE Control 0 KBC Clock Source 0 1 Description KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled). Function 8 MHz 12 MHz (default) 16 MHz Reserved Reserved. Use read-modify-write to change the value of the register. Do not change the value of these bits. Bit 2 must be 0. TRI-STATE Control. If KBC is inactive (disabled) when this bit is set, the KBC pins (KBCLK and KBDAT) are in TRISTATE. If Mouse is inactive (disabled) when this bit is set, the Mouse pins (MCLK and MDAT) are in TRI-STATE. 0: Disabled (default) 1: Enabled when device inactive Usage Hints: When required to change the clock frequency of the KBC, perform the following: 1. Disable the KBC logical device. 2. Change the frequency setting. 3. Enable the KBC logical device. 45 www.national.com GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7 2.0 Device Architecture and Configuration 2.12 2.12.1 General Description (Continued) GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7 The GPIO functional block includes 11 pins, arranged in one 8-bit port and one 3-bit port. Both of these ports are standard. The eight runtime registers of these ports are arranged in the GPIO address space shown in Table 2-12. The GPIO base address is 8-byte aligned. Address bits 2-0 are used to indicate the register offset. Table 2-12. Runtime Registers in GPIO Address Space Offset 00h 01h 02h 03h 04h 05h 06h 07h 2.12.2 Implementation The standard GPIO port has four runtime registers. Each pin is associated with a configuration register that includes seven configuration bits. 2.12.3 Configuration Index 30h 60h 61h 70h 71h 74h 75h F0h F1h Configuration Register or Action Activate. See also bit 0 of the SIOCF1 Register. Base Address MSB Register Base Address LSB Register. Bits 2-0 (for A2-0) are read only, 000b. Interrupt Number (For routing the IRQ from the GPIO). Interrupt Type. Bit 1 is read/write. Other bits are read only. Report no DMA assignment Report no DMA assignment GPIO Pin Configuration Select Register GPIO Pin Configuration Access Register Type R/W R/W R/W R/W R/W R R R/W R/W Reset 00h 00h 00h 00h 03h 04h 04h 00h 00h Mnemonic GPDO1 GPDI1 GPIEN1 GPST1 GPDO2 GPDI2 GPIEN2 GPST2 Name GPIO Data Out 1 Register GPIO Data In 1 Register GPIO Interrupt Enable 1 Register GPIO Status 1 Register GPIO Data Out 2 Register GPIO Data In 2 Register GPIO Interrupt Enable 2 Register GPIO Status 2 Register Reset FFh XXh 00h 00h 07h 0Xh 00h 00h 2 1 Port Type R/W RO R/W R/W1C R/W RO R/W R/W1C Figure 2-6 describes the organization of these registers. www.national.com 46 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7 2.0 Device Architecture and Configuration Pin Configuration Select Register Port Select Pin Select (Continued) 7 6 5 4 3 21 0 Port 1 Configuration Pin Configuration Access Register Port 2 Configuration Reserved Figure 2-6. GPIO Configuration Registers’ Access 2.12.4 GPIO Pin Configuration Select Register This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the GPIO Pin Configuration Access Register). It is reset by hardware to 00h. Location: Type: Bit Name Reset 0 Index F0h R/W 7 Reserved 0 0 6 5 Port Select 0 4 3 Reserved 0 0 2 1 Pin Select 0 0 0 Bit 7-6 5-4 Reserved Description Port Select. These bits select the GPIO port to be configured: 00: Reserved (default) 01, 10: Binary value of the port number, 1-2 respectively 11: Reserved Reserved Pin Select. These bits select the GPIO pin to be configured in the selected port: 0-7: Binary value of the pin number, 0-7 respectively (default=0) 3 2-0 47 www.national.com GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7 2.0 Device Architecture and Configuration 2.12.5 GPIO Pin Configuration Access Register (Continued) This register reflects, for both read and write, the register currently selected by the GPIO Pin Configuration Select Register. All the configuration registers that are accessed via this register have a common bit structure, as shown below. This register is reset by hardware to 44h. Location: Type: Index F1h R/W Bit Name Reset 7 Reserved 0 6 5 4 3 Lock 0 2 Pull-Up Control 1 1 Output Type 0 0 Output Enable 0 IRQ Debounce IRQ Polarity IRQ Type Enable 1 0 0 Bit 7 6 Reserved IRQ Debounce Enable 0: Disabled 1: Enabled (default) Description 5 IRQ Polarity. This bit defines the polarity of the signal that issues an interrupt from the corresponding GPIO pin (falling/low or rising/high). 0: Falling edge or low level input (default) 1: Rising edge or high level input IRQ Type. This bit defines the signal type that issues an interrupt from the corresponding GPIO pin. 0: Edge input (default) 1: Level input Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to 0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O Configuration 3 Register, SIOCF3). 0: No effect (default) 1: Direction, output type, pull-up and output value locked Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin. It supports open-drain output signals with internal pull-ups and TTL input signals 0: Disabled 1: Enabled (default) Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin. 0: Open-drain (default) 1: Push-pull Output Enable. This bit indicates the GPIO pin output state. It has no effect on input. 0: TRI-STATE (default) 1: Output enabled 4 3 2 1 0 www.national.com 48 FAN SPEED CONTROL - LOGICAL DEVICE 8 2.0 Device Architecture and Configuration 2.13 FAN SPEED CONTROL - LOGICAL DEVICE 8 2.13.1 General Description (Continued) This module includes two Fan Speed Controls. The four runtime registers of the two functional blocks are arranged in the address space shown in Table 2-13. The base address is 8-byte aligned. Address bits 2-0 are used to indicate the register offset. Table 2-13. Runtime Registers in Fan Speed Control Address Space Offset 00h 01h 02h 03h Mnemonic FCPSR0 FCDCR0 FCPSR1 FCDCR1 Name Fan Control 0 Pre-Scale Register Fan Control 0 Duty Cycle Register Fan Control 1 Pre-Scale Register Fan Control 1 Duty Cycle Register Reset 00h FFh 00h FFh Function Fan Speed Control 0 Fan Speed Control 1 Type R/W R/W R/W R/W 04h-07h Reserved Table 2-14. Fan Speed Control Runtime Register Bitmap Register Offset 00h 01h 02h 03h 04h07h Mnemonic FCPSR0 FCDCR0 FCPSR1 FCDCR1 Reserved Clock Select 7 Clock Select 6 5 4 Bits 3 Pre-Scale Value Duty Cycle Value Pre-Scale Value Duty Cycle Value 2 1 0 2.13.2 Configuration Index 30h 60h 61h 70h 71h 74h 75h F0h Configuration Register or Action Activate. See also bit 0 of the SIOCF1 Register. Base Address MSB Register Base Address LSB Register. Bits 2-0 (for A2-0) are read only, 000b. Interrupt Number Interrupt Type Report no DMA assignment Report no DMA assignment Fan Speed Control Configuration Register Type R/W R/W R/W RO RO RO RO R/W Reset 00h 00h 00h 00h 00h 04h 04h 00h 49 www.national.com FAN SPEED CONTROL - LOGICAL DEVICE 8 2.0 Device Architecture and Configuration 2.13.3 Fan Speed Control Configuration Register This register is reset by hardware to 00h. Location: Type: Bit Name Reset Index F0h R/W 7 Inverse FANOUT1 0 6 Inverse FANOUT0 0 5 (Continued) 4 3 2 Reserved 1 0 TRI-STATE Control Fan Speed Fan Speed Control 1 Control 0 Enable Enable 0 0 0 0 0 0 Bit 7 Description Inverse FANOUT1 0: The number in FCDCR1 indicates for how many clocks (of 256) FANOUT1 signal is high (default). 1: The number in FCDCR1 indicates for how many clocks (of 256) FANOUT1 signal is low. Inverse FANOUT0 0: The number in FCDCR0 indicates for how many clocks (of 256) FANOUT0 signal is high (default). 1: The number in FCDCR0 indicates for how many clocks (of 256) FANOUT0 signal is low. Fan Speed Control 1 Enable. When the Fan Speed Interface logical device is active: 0: Clock disabled (stopped). The FSC1 registers are accessible and maintained. FANOUT1 signal is 0 when Inverse FANOUT1 bit is 0. FANOUT1 signal is 1 when Inverse FANOUT1 is 1 (default). 1: Clock enabled and registers accessible Fan Speed Control 0 Enable. When the Fan Speed Interface logical device is active: 0: Clock disabled (stopped). The FSC0 registers are accessible and maintained. FANOUT0 signal is 0 when Inverse FANOUT0 bit is 0. FANOUT0 signal is 1 when Inverse FANOUT0 is 1 (default). 1: Clock enabled and registers accessible Reserved TRI-STATE Control. This bit controls the TRI-STATE status of the logical device output pins when it is inactive (disabled). 0: Disabled (default) 1: Enabled when device inactive 6 5 4 3-1 0 www.national.com 50 3.0 System Wake-Up Control (SWC) 3.0 System Wake-Up Control (SWC) 3.1 OVERVIEW The SWC wakes up the system by asserting the Power-Up Request (PWUREQ) output pin, in response to the following maskable system events: • Modem ring (RI1 and RI2 pins) • • • • Telephone ring (RING input pin) Any keyboard activity or specific programmable key sequence Any mouse activity or specific programmable click/s Two general-purpose events (PME1 and PME2 input pins). This chapter describes the general SWC functional block. A device may include a different implementation. For the device specific implementation, see the Device Architecture chapter. 3.2 FUNCTIONAL DESCRIPTION The SWC monitors seven system events or activities. Each one of them is fed into a dedicated detector that decides when this event is active, according to predetermined (either fixed or programmable) criteria. A set of dedicated registers is used to determine the wake-up criteria, including the Keyboard sequence. A Wake-Up Events Status Register (WKSR) and a Wake-Up Events Control Register (WKCR) hold a Status bit and Enable bit respectively, for each one of the events. Upon detection of any active event, the corresponding Status bit is set to 1. If the event is enabled (the corresponding Enable bit is set to 1), the PWUREQ output is asserted. In addition, detection of an active wake-up event may be also routed to any arbitrary IRQ (or SMI over IRQ2 if Serial IRQ is used). Disabling an event prevents it from issuing PWUREQ, but does not affect the Status bits. The PWUREQ signal is active when both the Status and Enable bits equal 1 for at least one event. The SWC logic is powered by VSB. The SWC configuration registers are battery backed, powered by VPP. The setup of the wake-up events, including programmable sequences, is retained throughout power failures (no VSB) as long as the battery is connected. VPP is taken from VSB when power is present; otherwise (power-fail), VBAT is used as the VPP source. System reset does not affect these registers. They are reset only by software reset or power-up of VPP. 3.3 3.3.1 EVENT DETECTION Modem Ring High to low transitions on RI1 or RI2 indicate the detection of ring in external modem connected to Serial Port 1 or 2 respectively and can be used as a wake-up event. 3.3.2 Telephone Ring A telephone ring can be detected by the SWC by processing the raw signal coming directly from the telephone line into the RING input pin. Detection of a pulse-train with a frequency higher than 16 Hz that lasts at least 0.3 sec is used as a wakeup event. The RING pulse-train detection is achieved by monitoring the falling edges on RING in time slots of 62.5 msec (a 16 Hz cycle). A positive detection occurs if falling edges of RING are detected in three consecutive time slots, following a time slot in which no RING falling edge is detected. This detection method guarantees the detection of a RING pulse-train with frequencies higher than 16 Hz. It filters out (does not detect) pulses of less than 10 Hz, and may detect pulses between 10 Hz to 16 Hz. 3.3.3 Keyboard and Mouse Activity The detection of either any activity or a specific predetermined Keyboard or Mouse activity can be used as a wake-up event. The Keyboard wake-up detection can be programmed to detect: • Any keystroke • • A specific programmable sequence of up to eight alphanumeric keystrokes Any programmable sequence of up to 8 bytes of data received from the keyboard. The Mouse wake-up detection can be programmed to detect either any Mouse click or movement, or a specific programmable click (left or right) or double-clicks. 3.3.4 General-Purpose Events A general-purpose event is defined as the detection of falling edge, rising edge, low level, or high level on a specific signal. Each signal’s event is configurable via software. PME1 and PME2 may wake up the system from power-off state, or generate an interrupt if the system is in power-on state. A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software. 51 www.national.com SWC REGISTERS 3.0 System Wake-Up Control (SWC) 3.4 SWC REGISTERS (Continued) SWC register offsets are related to a base address determined by the SWC Base Address Register in the device configuration. The register maps in this chapter use the following abbreviations for Type: • R/W = Read/Write • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write • RO = Read Only • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 3.4.1 SWC Register Map Offset Mnemonic 00h 01h 02h 03h 06h 07h WKCR WKSR WKCFG PS2CTL KDSR MDSR Name Wake-Up Events Control Register Wake-Up Events Status Register Wake-Up Configuration Register PS/2 Protocol Control Register Keyboard Data Shift Register Mouse Data Shift Register Type R/W R/W1C R/W R/W RO RO R/W Section 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 08h- PS2KEY0PS/2 Keyboard Key Data Registers 0Fh PS2KEY7 3.4.2 Wake-Up Events Control Register (WKCR) This register is set to 07h on power-up of VPP or software reset. Detected wake-up events that are enabled activate the PWUREQ signal. Location: Type: Bit Name Reset Offset 00h R/W 7 PME2 Event Enable 0 6 PME1 Event Enable 0 5 Reserved 0 4 Mouse Event Enable 0 3 KBD Event Enable 0 2 RING Event Enable 1 1 RI2 Event Enable 1 0 RI1 Event Enable 1 Bit 7 PME2 Event Enable 0: Disabled (default) 1: Enabled PME1 Event Enable 0: Disabled (default) 1: Enabled Reserved Mouse Event Enable 0: Disabled (default) 1: Enabled KBD Event Enable 0: Disabled (default) 1: Enabled Description 6 5 4 3 www.national.com 52 SWC REGISTERS 3.0 System Wake-Up Control (SWC) Bit 2 RING Event Enable 0: Disabled 1: Enabled (default) RI2 Event Enable 0: Disabled 1: Enabled (default) RI1 Event Enable 0: Disabled 1: Enabled (default) (Continued) Description 1 0 3.4.3 Wake-Up Events Status Register (WKSR) Offset 01h R/W1C 7 PME2 Event Status 0 6 PME1 Event Status 0 5 Reserved 0 4 Mouse Event Status 0 3 KBD Event Status 0 2 RING Event Status 0 1 RI2 Event Status 0 0 RI1 Event Status 0 This register is set to 00h on power-up of VPP or software reset. It indicates which wake-up events occurred. Location: Type: Bit Name Reset Bit 7 PME2 Event Status 0: Event not detected (default) 1: Event detected PME1 Event Status 0: Event not detected (default) 1: Event detected Reserved Mouse Event Status 0: Event not detected (default) 1: Event detected KBD Event Status 0: Event not detected (default) 1: Event detected RING Event Status 0: Event not detected (default) 1: Event detected RI2 Event Status 0: Event not detected (default) 1: Event detected RI1 Event Status 0: Event not detected (default) 1: Event detected Description 6 5 4 3 2 1 0 53 www.national.com SWC REGISTERS 3.0 System Wake-Up Control (SWC) 3.4.4 (Continued) Wake-Up Configuration Register (WKCFG) Offset 02h R/W 7 Reserved 0 6 PME2 Type 0 5 PME2 Polarity 0 4 PME1 Type 0 3 PME1 Polarity 0 2 Swap KBC Inputs 0 0 1 Reserved 0 0 This register is set to 00h on power-up of VPP or software reset. Location: Type: Bit Name Reset Bit 7 6 Reserved PME2 Type 0: Edge 1: Level PME2 Polarity 0: Falling edge, low level 1: Rising edge, high level PME1 Type 0: Edge 1: Level PME1 Polarity 0: Falling edge, low level 1: Rising edge, high level Description 5 4 3 2 Swap KBC Inputs 0: No swapping (default) 1: KBD (KBCLK, KBDAT) and Mouse (MCLK, MDAT) inputs swapped Reserved 1-0 3.4.5 PS/2 Protocol Control Register (PS2CTL) Offset 03h R/W 7 Disable Parity Check 0 6 5 4 3 2 1 0 This register is set to 00h on power-up of VPP or software reset. It configures the PS/2 Keyboard and Mouse wake-up features. Location: Type: Bit Name Reset Mouse Wake-Up Configuration 0 0 0 0 Keyboard Wake-Up Configuration 0 0 0 www.national.com 54 SWC REGISTERS 3.0 System Wake-Up Control (SWC) (Continued) Bit 7 6-4 Disable Parity Check Mouse Wake-Up Configuration Bits 654 0 0 0 0 1 1 1 1 3-0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Configuration Description Disable Mouse wake-up detection Wake-up on any Mouse movement or button click Wake-up on left button click Wake-up on left button double-click Wake-up on right button click Wake-up on right button double-click Wake-up on any button single-click (left, right or middle) Wake-up on any button double-click (left, right or middle) Keyboard Wake-Up Configuration Bits 3210 0000 0001 to 0111 1000 to 1111 Configuration } } Disable Keyboard wake-up detection Special key sequence 2-8 PS/2 scan codes (including scan codes for Shift and Alt keys) Password enabled with 1-8 keys (excluding scan codes for Shift and Alt keys) 3.4.6 Keyboard Data Shift Register (KDSR) This register is set to 00h on power-up of VPP or software reset. It stores the Keyboard data shifted in from the Keyboard during transmission, only when Keyboard wake-up detection is enabled. Location: Type: Bit Name Reset 3.4.7 0 0 0 Offset 06h RO 7 6 5 4 3 2 1 0 Keyboard Data 0 0 0 0 0 Mouse Data Shift Register (MDSR) This register is set to 00h on power-up of VPP or software reset. It stores the Mouse data shifted in from the Mouse during transmission, only when Mouse wake-up detection is enabled. Location: Type: Bit Name Reset 0 0 Offset 07h RO 7 6 5 Reserved 0 0 0 0 4 3 2 1 Mouse Data 0 0 0 55 www.national.com SWC REGISTER BITMAP 3.0 System Wake-Up Control (SWC) 3.4.8 (Continued) PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) The following eight registers (PS2KEY0-PS2KEY7) store the scan codes for the password or key sequence of the Keyboard wake-up feature. The first register (PS2KEY0) stores the scan code for the first key in the password/key sequence. The second register (PS2KEY1) stores the scan code for the second key in the password/key sequence. The third to eighth registers (PS2KEY2 - PS2KEY7) store the scan code for the third to eighth keys in the password/key sequence. These registers are set to 00h on power-up of VPP or software reset. Location: Type: Bit Name Reset 0 0 0 Offset 08h-0Fh R/W 7 6 5 4 3 2 1 0 Scan Code of Keys 0-7 0 0 0 0 0 3.5 SWC REGISTER BITMAP Register Offset 00h Mnemonic WKCR 7 PME2 Event Enable PME2 Event Status Reserved Disable Parity Check 6 PME1 Event Enable PME1 Evemt Status PME2 Type 5 4 Mouse Event Enable Mouse Event Status PME1 Type Bits 3 KBD Event Enable KBD Event Status PME1 Polarity 2 RING Event Enable RING Event Status Swap KBC Inputs 1 RI2 Event Enable RI2 Event Status 0 RI1 Event Enable RI1 Event Status Reserved 01h WKSR Reserved PME2 Polarity 02h 03h WKCFG PS2CTL Reserved Mouse Wake-Up Configuration Keyboard Wake-Up Configuration 06h 07h 08-0F KDSR MDSR PS2KEY0PS2KEY7 Reserved Keyboard Data Mouse Data Scan Code of Keys 0-7 www.national.com 56 4.0 General-Purpose Input/Output (GPIO) Port 4.0 General-Purpose Input/Output (GPIO) Port This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations. For the device specific implementation, see the Device Architecture and Configuration chapter. If there are fewer than 8 bits per port in a configuration, only the corresponding lower bits are implemented and the remaining bits are reserved. For instance, if there are 3 bits per port, only bits 0-2 are implemented, and the remaining 5 bits are reserved. 4.1 OVERVIEW Software capability to manipulate and read pin levels Controllable interrupt assertion based on the pin level or level transition Ability to capture and manipulate interrupts and their associated status Back-drive protected pins. The GPIO port is an 8-bit port which is based on eight pins. It features: • • • • • • GPIO port operation is associated with two sets of registers: Configuration registers, mapped in the Device Configuration space. These registers are used to statically set up the logical behavior of each pin. There is one 8-bit register for each GPIO pin. Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Interrupt Enable (GPIEN) and GPIO Status (GPST). These registers are mapped in the GPIO device IO space (which is determined by the base address registers in the GPIO Device Configuration). They are used to manipulate and/or read the pin values, and to control and handle interrupt generation. Each runtime register corresponds to the 8-pin port, such that bit n in each one of the four registers is associated with GPIOXn pin, where X is the port number. Each GPIO pin is associated with eight configuration bits and the corresponding bit slice of the four runtime registers, as shown in Figure 4-1. The functionality of the GPIO port is divided into basic functionality that includes the manipulation and reading of the GPIO pins. This functionality is described in Section 4.2. The enhanced functionality which includes the interrupt assertion and handling is described in Section 4.3. Bit n GPIOX Base Address GPDOX GPDIX GPIENX GPSTX 8 GPIO Configuration Registers GPIOXn Pin Pin Configuration Access Register GPIOXn CNFG x8 x8 Pin Select Pin Configuration Select Register X = port number; n = 0 to 7 Interrupt Pending x8 Interrupt Request GPIOXn Port Logic Runtime Registers Figure 4-1. GPIO Port Architecture 57 www.national.com BASIC FUNCTIONALITY 4.0 General-Purpose Input/Output (GPIO) Port 4.2 BASIC FUNCTIONALITY (Continued) The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and GPDI. The configuration and operation of a single pin GPIOXn (pin n in port X) is shown in Figure 4-2. GPIO Device Enable Read Only Data In Push-Pull=1 Static Pull-Up Pin Read/Write Data Out Internal Bus Pull-Up Enable Lock Bit 3 Pull-Up Control Output Type Output Enable Bit 0 Bit 2 Bit 1 GPIO Configuration Register Figure 4-2. GPIO Basic Functionality 4.2.1 Configuration Options The GPIO Configuration Register controls the following basic configuration options: • • • • Port Direction - Controlled by the Output Enable bit (bit 0) Output Type - Totem pole vs. open-drain. It is controlled by Output Buffer Type (bit 1) by enabling/disabling the pull-up portion of the output buffer. Weak Static Pull-up - May be added to any type of port (input, open-drain or totem pole). It is controlled by Pull-Up Control (bit 2). Pin Lock - GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The lock is controlled by Lock (bit 3). It disables writes to the GPDO Register bits, and to bits 0-3 of the GPIO Configuration Register (Including the Lock bit itself). Once locked, it can be released by hardware reset only. Operation 4.2.2 The value that is written to the GPDO Register is driven to the pin, if the output is enabled. Reading from the GPDO Register returns its contents, regardless of the pin value or the port configuration. The GPDI Register is a read-only register. Reading from the GPDI Register returns the pin value, regardless of what is driving it (the port itself, configured as an output port, or the external device when the port is configured as an input port). Writing to this register is ignored. Activation of the GPIO port is controlled by external device specific configuration bit (or a combination of bits). When the port is inactive, access to GPDI and GPDO Registers is disabled, and the inputs are blocked. However, there is no change in the port configuration and in the GPDO value, and hence there is no effect on the outputs of the pins. www.national.com 58 INTERRUPT ASSERTION AND HANDLING 4.0 General-Purpose Input/Output (GPIO) Port 4.3 INTERRUPT ASSERTION AND HANDLING (Continued) The enhanced GPIO port supports interrupt assertion and handling. This functionality is based on three configuration bits and a bit slice of runtime registers GPIEN and GPST. The configuration and operation of the interrupt capability is shown in Figure 4-3. 1 0 Interrupt Enable Rising Edge Detector Rising Edge or High Level =1 Status R/W Interrupt Request 0 Input Debouncer Pin Level =1 1 R/W 1 to Clear Interrupt Requests from other GPIO Pins IRQ Debounce Enable Bit 6 IRQ Polarity Bit 5 IRQ Type Bit 4 Internal Bus GPIO Configuration Register Figure 4-3. Interrupt Assertion 4.3.1 Interrupt Configuration Each pin in the GPIO port is a potential interrupt source. The interrupt generator can trigger an interrupt upon predetermined behavior of the source pin. The GPIO Configuration Register determines the interrupt generation trigger type for the interrupt assertion. IRQ Polarity Two trigger types of interrupt assertion are supported: edge and level. An edge interrupt may be asserted upon a source pin transition either from high to low or low to high. A level interrupt may be asserted when the source pin is in active level. The trigger type is determined by IRQ Type (bit 4 of the GPIO Configuration Register). The direction of the transition (for edge) or the polarity of the active level (for level) is determined by IRQ Polarity (bit 5 of the GPIO Configuration Register). IRQ Debounce Enable The input signal for the interrupt can be debounced for about 15 msec. The signal state should be transferred only after a debouncing period during which the signal has no transitions, to ensure that the signal is stable. The debouncer adds 15 msec delay to both assertion and de-assertion level interrupts, and to the assertion of edge interrupts. When working with a level interrupt, it is recommended to disable the debounce if the delay in the interrupt de-assertion is not acceptable. The debounce is controlled by IRQ Debounce Enable (bit 6 of the GPIO Configuration Register). 4.3.2 Interrupt Assertion The interrupt assertion for each GPIO pin is controlled by the corresponding bit in the GPIEN Register. Interrupt assertion by a GPIO pin is enabled if the corresponding bit of this register is set to 1. The GPST Register is a general-purpose edge detector which may be used to reflect the interrupt source pending status for edge-triggered interrupts. The term active edge refers to a change in a GPIO pin level that matches the IRQ Polarity bit (1 for rising edge and 0 for falling edge). Active level refers to the GPIO pin level that matches the IRQ Polarity bit (1 for high level and 0 for low level). The corresponding bit of the GPST Register is set by hardware whenever an active edge is detected, regardless of any other bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored. 59 www.national.com GPIO PORT REGISTERS 4.0 General-Purpose Input/Output (GPIO) Port (Continued) A GPIO pin is in interrupt pending state if the corresponding bit of the GPIEN Register is set and either: • • The IRQ Type is level and the pin is in active level, or The IRQ Type is edge and the corresponding bit of the GPST Register is set. The target IRQ line is asserted if at least one GPIO pin is in interrupt pending state. The selection of the target IRQ line is determined by the IRQ selection procedure of the device configuration. The assertion of the IRQ line is blocked when the GPIO functional block is deactivated. If the output is enabled, the IRQ may be initiated by the software when writing to the GPDO Register. An edge interrupt may be de-asserted by clearing the corresponding GPST bit. However, a level Interrupt source may not be released by software (except for disabling the source), as long as the pin is in active level. When level interrupt is used, it is recommended to disable the input debouncer. Upon de-activation of the GPIO port, the GPST Register is cleared and access to both the GPST and GPIEN Registers is disabled. The target IRQ line is detached from the GPIO and de-asserted. Before enabling the interrupts, it is recommended to set the desired interrupt configuration, and then verify that the status registers are cleared. 4.4 GPIO PORT REGISTERS The register maps in this chapter use the following abbreviations for Type: • R/W = Read/Write • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write • RO = Read Only • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 4.4.1 GPIO Pin Configuration Access Register This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is mapped to the PnP configuration space. The mapping scheme is based on the GPIO Pin Configuration Select Register that functions as an index register, and the specific GPIO Pin Configuration Access Register that reflects the configuration of the currently selected pin. For details on the GPIO Pin Configuration Select Register, refer to the Device Architecture and Configuration chapter. Bits 4-6 are applicable only for the enhanced GPIO port with interrupt support. In the basic port. these bits are reserved, return 0 on read and have no effect on port functionality. Location: Type: Device specific R/W (bit 3 is set only) Bit Name Reset 7 Reserved 0 6 5 4 3 Lock 0 2 Pull-Up Control 1 1 Output Type 0 0 Output Enable 0 IRQ Debounce IRQ Polarity IRQ Type Enable 1 0 0 Bit 7 6 Reserved IRQ Debounce Enable 0: Disabled 1: Enabled (default) Description 5 IRQ Polarity. This bit defines the polarity of the signal that issues an interrupt from the corresponding GPIO pin (falling/low or rising/high). 0: Falling edge or low level input (default) 1: Rising edge or high level input www.national.com 60 GPIO PORT REGISTERS 4.0 General-Purpose Input/Output (GPIO) Port Bit 4 (Continued) Description IRQ Type. This bit defines the signal type that issues an interrupt from the corresponding GPIO pin. 0: Edge input (default) 1: Level input Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to 0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O Configuration 3 Register (SIOCF3). 0: No effect (default) 1: Direction, output type, pull-up and output value locked Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin. It supports open-drain output signals with internal pull-ups and TTL input signals 0: Disabled 1: Enabled (default) Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin. 0: Open-drain (default) 1: Push-pull Output Enable. This bit indicates the GPIO pin output state. It has no effect on input. 0: TRI-STATE (default) 1: Output enabled GPIO Port Runtime Register Map Offset Mnemonic Name GPIO Data Out Register GPIO Data In Register GPIO Interrupt Enable Register GPIO Status Register Type R/W RO R/W R/W1C Section 4.4.3 4.4.4 4.4.5 4.4.6 3 2 1 0 4.4.2 Device specific1 GPDO Device specific1 GPDI Device specific1 GPIEN Device specific1 GPST 1. The location of this register is defined in the Device Architecture and Configuration chapter in Section 2.12.1. 61 www.national.com GPIO PORT REGISTERS 4.0 General-Purpose Input/Output (GPIO) Port 4.4.3 Type: Bit Name Reset 1 1 1 1 GPIO Data Out Register (GPDO) Device specific R/W 7 6 5 4 Location: (Continued) 3 Data Out 1 2 1 0 1 1 1 Bit 7 6 5 4 3 2 1 0 Description Data Out. Bits 7-0 correspond to pins 7-0 respectively. The value of each bit determines the value driven on the corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the bit is locked by the GPIO Configuration Register Lock bit. Reading the bit returns its value, regardless of the pin value and configuration. 0: Corresponding pin driven to low when output enabled 1: Corresponding pin driven or released to high (according to buffer type and static pull-up selection) when output enabled 4.4.4 Type: Bit Name Reset GPIO Data In Register (GPDI) Device specific RO 7 6 5 4 Data In X X X X X X X X 3 2 1 0 Location: Bit 7 6 5 4 3 2 1 0 Description Data In. Bits 7-0 correspond to pins 7-0 respectively. Reading each bit returns the value of the corresponding GPIO pin, regardless of the pin configuration and the GPDO Register value. Write is ignored. 0: Corresponding pin level low 1: Corresponding pin level high www.national.com 62 GPIO PORT REGISTERS 4.0 General-Purpose Input/Output (GPIO) Port 4.4.5 Type: Bit Name Reset 0 0 0 GPIO Interrupt Enable Register (GPIEN) Device specific R/W 7 6 5 4 Location: (Continued) 3 2 1 0 Interrupt Enable 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Description Interrupt Enable. Bits 7-0 correspond to pins 7-0 respectively. Each bit enables Interrupt generation by the corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPST Register. 0: IRQ generation by corresponding GPIO pin masked 1: IRQ generation by corresponding GPIO pin enabled 4.4.6 Type: Bit Name Reset GPIO Status Register (GPST) Device specific R/W1C 7 6 5 4 Status 0 0 0 0 0 0 0 0 3 2 1 0 Location: Bit 7 6 5 4 3 2 1 0 Description Status. Bits 7-0 correspond to pins 7-0 respectively. Each bit is an edge detector that is set to 1 by the hardware upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding GPIO pin. This edge detection is independent of the IRQ Type or the Interrupt Enable bit in the GPIEN Register. However, the bit may reflect the IRQ status for enabled, edge-trigger IRQ sources. Writing 1 to the Status bit clears it to 0. 0: No active edge detected since last cleared 1: Active edge detected 63 www.national.com 5.0 Fan Speed Control 5.0 Fan Speed Control 5.1 OVERVIEW This chapter describes one Fan Speed Control module. A device may include some modules with different implementations. For the device specific implementation, see the Device Architecture and Configuration chapter. The Fan Speed Control is a programmable Pulse Width Modulation (PWM) generator. The PWM output is used to control the fan’s power voltage, which is correlated to the fan’s speed. Converting a 0 to 100% duty cycle PWM signal to an analog voltage range is achieved by an external circuit, as shown in Figure 5-1. Some new types of fans accept direct PWM input without any external circuitry. Fan Fan Speed Control FANOUT External External Circuitry Circuitry Control Figure 5-1. Fan Speed Control - System Configuration 5.2 FUNCTIONAL DESCRIPTION The PWM generator operation is based on a PWM counter and two registers: the Fan Speed Control Pre-Scale Register (FCPSR), used to determine the overall cycle time (or the frequency) of the FANOUT output, and the Fan Speed Control Duty Cycle Register (FCDCR), used to determine the duty cycle of the FANOUT between 0 to 100%. The PWM counter is an 8-bit, free-running counter that runs continuously in a cyclic manner, i.e its cycle equals 256 clock periods. The PWM output is high as long as the count is lower than the FCDCR value, and flips to low as the counter exceeds that value. The duty cycle (expressed as a percentage) is therefore (FCDCR/256)*100. In particular, the PWM output is continuously low when FCDCR=0 and continuously high when FCDCR=FFh. The FANOUT output may be inverted by an external configuration bit, in which case the FANOUT duty cycle is ([256-FCDCR]/256)*100. The PWM counter clock is generated by dividing the input clock, either 24 MHz or 200 KHz (according to Clock Select, bit 7 of the FCPSR Register) using a clock divider. The division factor, which must be between 1 and 124, is defined as PreScale Value+1, where Pre-Scale is the binary value stored in bits 6 to 0 of the FCPSR Register. The resulting PWM output frequency is therefore (24 MHz or 200 kHz/([Pre-Scale Value+1]*256). The default selection of 24 MHz input clock allows a programmable FANOUT frequency in the range of 756 Hz to 93.75 KHz. For lower frequencies, selecting the 200 KHz input clock allows a frequency range of 6 Hz to 781 Hz. See Figure 5-2. The FANOUT frequency must be pre-selected according to the fan type specific requirements prior to enabling the Fan Speed Control. The only run-time change that is required to dynamically control the fan speed is the value of the FCDCR Register. The contents of the FCPSR Register must not be changed when the Fan Speed Control is enabled. 24 MHz 0 200 KHz 1 Clock Divider (1-124) PWM Counter PWM Output Comparator Bit 7 Bits 6-0 Invert FANOUT FCDCR > Counter 0 O 1 FANOUT FCPSR Register FCDCR Register Figure 5-2. PWM Generator (FANOUT) www.national.com 64 FAN SPEED CONTROL REGISTERS 5.0 Fan Speed Control 5.3 (Continued) FAN SPEED CONTROL REGISTERS The register maps in this chapter use the following abbreviations for Type: • R/W = Read/Write • R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. • W = Write • RO = Read Only • R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. 5.3.1 Fan Speed Control Register Map Offset Device specific1 Device specific1 Mnemonic FCPSR FCDCR Name Fan Speed Control Pre-Scale Register Fan Speed Control Duty Cycle Register Type R/W R/W Section 5.3.2 5.3.3 1. The location of this register is defined in the Device Architecture and Configuration chapter in Section 2.13.1. 5.3.2 Type: Bit Name Reset Fan Control Pre-Scale Register (FCPSR) Device specific R/W 7 Clock Select 0 0 0 0 6 5 4 3 Pre-Scale Value 0 0 0 0 2 1 0 Location: Bit 7 Description Clock Select. This bit selects the input clock for the clock divider. 0: 24 MHz 1: 200 KHz Pre-Scale Value. The clock divider for the input clock (24 MHz or 200 KHz) is Pre-Scale Value + 1. Writing 0 transfers the input clock directly to the counter. The maximum clock divider is 124 (7Bh +1). These bits must not be programmed with the values 7Ch, 7Dh, 7Eh and 7Fh as this may produce unpredictable results. The contents of this register should not be changed when the corresponding Fan Speed Control Enable bit of the Fan Speed Control Configuration Register is 1 (See Device Architecture and Configuration chapter). Otherwise, there may be unpredictable results. 6-0 5.3.3 Type: Bit Name Reset Fan Control Duty Cycle Register (FCDCR) Device specific R/W 7 6 5 4 3 2 1 0 Location: Duty Cycle Value 1 1 1 1 1 1 1 1 65 www.national.com FAN SPEED CONTROL BITMAP 5.0 Fan Speed Control (Continued) Bit 7-0 Description Duty Cycle. The binary value of this 8-bit field determines the number of clock cycles, out of a 256-cycle period, during which the PWM output is high (while FANOUT is either equal to or the inverse of the PWM output, depending on the Inverse FANOUT configuration bit). 00h: PWM output is continuously low 01h - FEh: PWM output is high for [Duty Cycle Value] clock cycles and low for [256-Duty Cycle Value] clock cycles FFh: PWM output is continuously high 5.4 FAN SPEED CONTROL BITMAP Register Offset Device specific1 Device specific1 Mnemonic FCPSR FCDCR 7 Clock Select 6 5 4 Bits 3 Pre-Scale Value Duty Cycle Value 2 1 0 1. The location of this register is defined in the Device Architecture and Configuration chapter. www.national.com 66 6.0 Floppy Disk Controller (FDC) 6.0 Floppy Disk Controller (FDC) Refer to PC87307, PC87309 or PC87317 datasheet. 67 www.national.com 7.0 Parallel Port 7.0 Parallel Port Refer to PC87307, PC87309 or PC87317 datasheet. www.national.com 68 8.0 Serial Port 2 with IR 8.0 Serial Port 2 with IR Refer to PC87307, PC87309 or PC87317 datasheet. 69 www.national.com 9.0 Serial Port 1 9.0 Serial Port 1 Refer to PC87307, PC87309 or PC87317 datasheet. www.national.com 70 10.0 Keyboard and Mouse Controller (KBC) 10.0 Keyboard and Mouse Controller (KBC) Refer to PC87307, PC87309 or PC87317 datasheet. 71 www.national.com 11.0 Device Characteristics 11.0 Device Characteristics 11.1 DC ELECTRICAL CHARACTERISTICS Sections 11.1.6 to 11.1.10 summarize the DC characteristics of all device pins described in the Signal/Pin Connection and Description chapter. The characteristics describe the general I/O buffer type. For the exception, refer to the notes at the end of this section. 11.1.1 Recommended Operating Conditions Symbol Parameter VDD VSB VBAT TA Supply Voltage Standby Supply Voltage Battery Supply Voltage Operating Temperature Min 4.5 4.5 2.4 0 Typ 5.0 5.0 3.0 Max 5.5 5.5 3.6 +70 Unit V V V °C 11.1.2 Absolute Maximum Ratings Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all voltages are relative to ground. Symbol Parameter VDD VI VO TSTG PD TL Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation Lead Temperature Soldering (10 sec) ESD Tolerance CZAP = 100 pF RZAP = 1.5 KΩ1 2000 Conditions Min −0.5 −0.5 −0.5 −65 Max TBD VDD + 0.5 VDD + 0.5 +165 1 +260 Unit V V V °C W °C V 1. Value based on test complying with RAI-5-048-RA human body model ESD testing. 11.1.3 Capacitance Symbol Parameter CIN CIN1 CIO CO TA = 25°C, f = 1 MHz Input Pin Capacitance Clock Input Capacitance I/O Pin Capacitance Output Pin Capacitance 5 Min Typ 5 8 10 6 Max 7 12 12 8 Unit pF pF pF pF www.national.com 72 DC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics (Continued) 11.1.4 Power Consumption under Recommended Operating Conditions Symbol ICC ICCLP ISB ISBLP IBAT Parameter VDD Average Main Supply Current VDD Quiescent Main Supply Current in Low Power Mode VSB Average Main Supply Current VSB Quiescent Main Supply Current in Low Power Mode VBAT Battery Supply Current Conditions VIL = 0.5 V, VIH = 2.4 V No Load VIL = VSS, VIH = VDD No Load VIL = 0.5 V, VIH = 2.4 V No Load VIL = VSS, VIH = VSB V No Load VDD, VSB = 0 V, VBAT = 3 V Typ 32 1.3 Max 50 1.7 15 3 250 Unit mA mA mA mA nA 11.1.5 Input, PCI 5V Symbol: INPCI Symbol Parameter VIH VIL lIL1 Input High Voltage Input Low Voltage Input Leakage Current Conditions Min 2.0 -0.5 Max VDD + 0.5 0.8 -/+10 Unit V V µA 0 < Vin < VDD 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with TRI-STATE outputs. 11.1.6 Strap Pin Symbol: INSTRP Symbol Parameter VIH IIL Input High Voltage During Reset: VIN = VDD VIN = VSS Conditions Min 0.6VDD 1 Max VDD 1 250 −10 Unit V µA µA Input Leakage Current 1. Not tested. Guaranteed by design. 11.1.7 Input, TTL Compatible Symbol: INT Symbol Parameter VIH VIL IIL Input High Voltage Input Low Voltage Input Leakage Current VIN = VDD VIN = VSS Conditions Min 2.0 −0.51 Max VDD1 0.8 10 −10 Unit V V µA µA 1. Not tested. Guaranteed by design. 73 www.national.com DC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics Symbol: INTS Symbol Parameter VIH VIL IIL VH Input High Voltage Input Low Voltage Input Leakage Current Input Hysteresis (Continued) 11.1.8 Input with TTL Schmitt Trigger Conditions Min 2.0 −0.5 1 Max VDD1 0.8 10 −10 Unit V V µA µA mV VIN = VDD VIN = VSS 250 1. Not tested. Guaranteed by design. 11.1.9 Output, Totem-Pole Buffer Symbol: Op/n Output, Totem-Pole buffer that is capable of sourcing p mA and sinking n mA Symbol Parameter VOH VOL Output High Voltage Output Low Voltage Conditions IOH = −p mA IOL = n mA Min 2.4 0.4 Max Unit V V 11.1.10 Output, Open-Drain Buffer Symbol: ODn Output, Open-Drain output buffer that is capable of sinking n mA. Output from these signals is open-drain and cannot be forced high. Symbol Parameter VOL Output Low Voltage Conditions IOL = n mA Min Max 0.4 Unit V Notes: 1. All pins are back-drive protected. 2. The following pins have a static pull-up resistor and therefore may have input leakage current (when VIN = VSS) of about -250µA: TBD 3. The following pins have a static pull-down resistor and therefore may have input leakage current (when VIN = VDD) of about 200µA: TBD 4. Output from SLCT, BUSY/WAIT (and PE if bit 2 of PP Confg0 Register is “0”) is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used. 5. Output from ACK, ERR (and PE if bit 2 of PP Confg0 Register is “1”) is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used. 6. IOH on pins P12 and P17 are driven for 10 nsec after the low-to-high transition. 7. Output from STB, AFD, INIT, SLIN is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based (FIFO). Otherwise, output from these signals is Level 2. External 4.7 KΩ pull-up resistors should be used. 8. Output from PD7-0 is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based (FIFO) and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is Level 2. External 4.7 KΩ pull-up resistors should be used. 9. IOH is valid for a GPIO signals only when it is not configured as open-drain. www.national.com 74 AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics (Continued) 11.2 AC ELECTRICAL CHARACTERISTICS 11.2.1 AC Test Conditions Load Circuit (Notes 1, 2, 3) VDD S1 0.1 µf RL AC Testing Input, Output Waveform 2.4 0.4 2.0 0.8 Test Points 2.0 0.8 Input Device Under Test CL Output Figure 11-1. AC Test Conditions, TA = 0 °C to 70 °C, VDD = 5.0 V ±10% Notes: 1. CL = 100 pF, includes jig and scope capacitance. 2. S1 = Open for push-pull output pins. S1 = VDD for high impedance to active low and active low to high impedance measurements. S1 = GND for high impedance to active high and active high to high impedance measurements. RL = 1.0KΩ for µP interface pins. For the FDC open-drive interface pins, S1 = VDD and RL = 150Ω 11.2.2 Clock Timing 48MHz Symbol tCH tCL tCP Parameter Min Clock High Pulse Width1 Clock Low Pulse Width1 Clock Period 1 1. Not tested. Guaranteed by design. 8.4 8.4 20 21.5 Max Unit nsec nsec nsec . tCH tCP CLKIN tCL 75 www.national.com AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics (Continued) 11.2.3 Host Interface I/O Cycle Timing Symbol tAR tAW tDH tDS tHZ tRA tRCU tRD tRDH tRI tRVD tWA tWCU tWI tWR RC WC tWRR tRDYA tRDYI tRWI Parameter Valid Address to Read Active Valid Address to Write Active Data Hold Data Setup Read to Floating Data Bus1 Address Hold from Inactive Read Read Cycle Update1 Read Strobe Width Read Data Hold Read Strobe to Clear IRQ Active Read to Valid Data Address Hold from Inactive Write Write Cycle Update1 Write Strobe to Clear IRQ Write Strobe Width Read Cycle = tAR + tRD + tRCU1 Write Cycle = tAW + tWR + tWC1 RD low after WR high1 RD/WR active to IOCHRDY active2 WAIT inactive to IOCHRDY inactive2 IOCHRDY inactive to RD/WR inactive2 10 60 123 123 80 0 24 40 0 45 55 Min 18 18 0 18 13 0 45 60 10 55 55 25 Max Unit nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec 1. Not tested. Guaranteed by design. 2. Applicable for EPP mode only. www.national.com 76 AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics (Continued) Read AEN A15-0 tAR RD Valid RC tRD tRA OR WR D7-0 tRVD Valid Data tRDH tHZ IRQ tRI tRCU Valid Write AEN A15-0 tAW WR Valid WC tWR tWA tWCU Valid tWRR RD D7-0 Valid Data tDS tDH tWI IRQ IOCHRDY RD/WR WAIT IOCHRDY tRDYA tRDYI tRWI 77 www.national.com AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics (Continued) 11.2.4 Host Interface DMA Cycle Timing Symbol tACH tACS tDCH tDCS tDSW Parameter AEN Hold from RD, WR Inactive AEN Signal Setup DACK Hold from RD, WR Inactive DACK Signal Setup RD, WR Pulse Width DRQ Inactive from RD, WR Active TC Hold from RD, WR Inactive TC Signal Setup Min 0 15 0 15 60 Max Unit nsec nsec nsec nsec nsec tRQS tTCH tTCS 60 0 40 nsec nsec nsec DRQ AEN tDCS DACK tDSW RD, WR tACS tRQ tTCS TC tTCH tDCH tACH www.national.com 78 AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics (Continued) 11.2.5 PCICLK Timing Specifications Symbol tCYC1 tHIGH tLOW Parameter PCICLK Cycle Time PCICLK High Time PCCLK Low Time PCICLK Slew Rate2 Min 30 11 11 1 4 Max ∞ Units ns ns ns V/ns 1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be changed at any time during the operation of the system as long as the clock edges remain “clean” (monotonic) and the minimum cycle and high and low times are not violated. The clock may only be stopped in a low state. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock wavering as shown below. tHIGH 2.4 V 2.0 V 1.5 V 0.8 V tCYC tLOW 2.0 V, p-to-p (minimum) 0.4 V 79 www.national.com AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics 11.2.6 Serial IRQ Timing Symbol tVAL tON tOFF tSU tHI (Continued) Description Output Valid Delay Float to Active Delay Active to Float Delay Input Setup Time Input Hold Time Reference Conditions After RE PCICLK After RE PCICLK After RE PCICLK Before RE PCICLK After RE PCICLK Min (ns) Max (ns) 11 2 28 7 0 Output PCICLK tVAL tON SERIRQ tOFF Input PCICLK tSU Input Valid tHI SERIRQ www.national.com 80 AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics (Continued) 11.2.7 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing Symbol Parameter tBT Single Bit Time in Serial Port and Sharp-IR Receiver Modulation Signal Pulse Width in Sharp-IR and Consumer Remote Control Modulation Signal Period in Sharp-IR and Consumer Remote Control Transmitter Receiver Transmitter Receiver Transmitter, Variable tSPW SIR Signal Pulse Width Transmitter, Fixed Receiver SDRT SIR Data Rate Tolerance. % of Nominal Data Rate. SIR Leading Edge Jitter % of Nominal Bit Duration. Transmitter Receiver Transmitter Receiver Conditions Transmitter Min tBTN − 25 1 Max tBTN + 25 tBTN + 2% tCWN + 25 Unit nsec nsec nsec nsec tBTN − 2% tCWN − 252 500 tCPN − 253 tMMIN4 (3/16) x tBTN − 151 1.48 1.00 tCMW tCPN + 25 tMMAX4 (3/16) x tBTN + 151 1.78 nsec nsec nsec µsec µsec tCMP ± 0.87% ± 2.0% ± 2.5% ± 6.5% tSJT 1. tBTN is the nominal bit time in Serial Port, Sharp-IR, SIR and Consumer Remote Control modes. It is determined by the setting of the Baud Generator Divisor registers 2. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by the MCPW field (bits 7-5) of the IRTXMC register and the TXHSC bit (bit 2) of the RCCFG register. 3. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by the MCFR field (bits 4-0) of the IRTXMC register and the TXHSC bit (bit 2) of the RCCFG register. 4. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall in order for the signal to be accepted by the receiver. These time values are determined by the contents of register IRRXDC and the setting of the RXHSC bit (bit 5) of the RCCFG register tBT Serial Port tCMP tCMW Sharp-IR Consumer Remote Control tSPW SIR 81 www.national.com AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics 11.2.8 Modem Control Timing Symbol tHL tLH tSIM (Continued) Parameter RI2,1 High to Low Transition RI2,1 Low to High Transition Delay to Set IRQ from Modem Input Min 10 10 Max Unit nsec nsec 40 nsec CTS, DSR, DCD tSIM tSIM INTERRUPT (Read MSR) (Read MSR) tSIM RI tHL tLH 11.2.9 FDC Write Data Timing Symbol tHDH tHDS tWDW Parameter HDSEL Hold from WGATE Inactive1 HDSEL Setup to WGATE Active1 Write Data Pulse Width Min 750 100 See tDRP, tICP and tWDW values in table below Max Unit µsec µsec 1. Not tested. Guaranteed by design. HDSEL WGATE tHDS tWDW tHDH WDATA tDRP tICP tWDW Values Data Rate 1 Mbps 500 Kbps 300 Kbps 250 Kbps tDRP 1000 2000 3333 4000 tICP 6 x tCP1 6 x tCP1 10 x tCP1 12 x tCP1 tICP Nominal 125 125 208 250 tWDW 2 x tICP 2 x tICP 2 x tICP 2 x tICP tWDW Minimum 250 250 375 500 Unit nsec nsec nsec nsec 1. tCP is the clock period defined in Section 11.2.2. www.national.com 82 AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics 11.2.10 FDC Drive Control Timing Symbol tDST tIW tSTD tSTP tSTR Parameter (Continued) Min 1 Max Unit µsec nsec msec µsec msec DIR Setup to STEP Active Index Pulse Width 6 100 tSTR 8 1 DIR Hold from STEP Inactive STEP Active High Pulse Width1 STEP Rate Time1 1. Not tested. Guaranteed by design. DIR tDST STEP tSTP tSTR INDEX tIW tSTD 11.2.11 FDC - Read Data Timing Symbol tRDW Parameter Read Data Pulse Width Min 50 Max Unit nsec RDATA tRDW 83 www.national.com AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics (Continued) 11.2.12 Standard Parallel Port Timing Symbol Parameter tPDH tPDS tSW Port Data Hold Port Data Setup Strobe Width Conditions These times are system dependent and are therefore not tested. These times are system dependent and are therefore not tested. These times are system dependent and are therefore not tested. Typ 500 500 500 Max Unit nsec nsec nsec Typical Data Exchange BUSY ACK tPDS PD7-0 tSW STB tPDH 11.2.13 Enhanced Parallel Port Timing Symbol tWW19a tWW19ia tWST19a tWEST tWPDH tWPDS tEPDW tEPDH Parameter WRITE Active from WAIT Low WRITE Inactive from WAIT Low DSTRB or ASTRB Active from WAIT Low DSTRB or ASTRB Active after WRITE Active PD7-0 Hold after WRITE Inactive PD7-0 Valid after WRITE Active PD7-0 Valid Width PD7-0 Hold after DSTRB or ASTRB Inactive 80 0 10 0 15 Min Max 45 45 65 EPP 1.7 EPP 1.9 Unit nsec nsec nsec nsec nsec nsec nsec nsec tWW19a WRITE DSTRB or ASTRB PD7-0 tWPDS WAIT tWW19ia tWST19a tWEST tWPDH tWST19a tEPDH Valid tEPDW www.national.com 84 AC ELECTRICAL CHARACTERISTICS 11.0 Device Characteristics (Continued) 11.2.14 Extended Capabilities Port (ECP) Timing Forward Mode Symbol tECDSF tECDHF tECLHF tECHHF tECHLF tECLLF Parameter Data Setup before STB Active Data Hold after BUSY Inactive BUSY Active after STB Active STB Inactive after BUSY Active BUSY Inactive after STB Active STB Active after BUSY Inactive Min 0 0 75 0 0 0 1 35 Max Unit nsec nsec nsec sec msec nsec tECDHF PD7-0 AFD tECDSF tECLLF tECLHF tECHLF tECHHF STB BUSY Reverse Mode Symbol tECDSR tECDHR tECLHR tECHHR tECHLR tECLLR Parameter Data Setup before ACK Active Data Hold after AFD Active AFD Inactive after ACK Active ACK Inactive after AFD Inactive AFD Active after ACK Inactive ACK Active after AFD Active Min 0 0 75 0 0 0 35 1 Max Unit nsec nsec nsec msec sec nsec tECDHB PD7-0 BUSY tECDSB tECLLB tECLHB tECHLB tECHHB ACK AFD 85 www.national.com PC87351 PC98 and ACPI Compliant SuperI/O with System Wake-Up Control Physical Dimensions All dimensions are in millimeters Plastic Quad Flatpack (PQFP), JEDEC Order Number PC87351-xxx/VLA NS Package Number VLA128A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Fax: 1-800-737-7018 Email: support@nsc.com Tel: 1-800-272-9959 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Europe Fax: (+49) 0-180-530 85 86 Email: europe.support@nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 National Semiconductor Asia Pacific Customer Response Group Fax: 65-250-4466 Email: sea.support@nsc.com Tel: 65-254-4466 National Semiconductor Japan Ltd. Fax: 81-3-5620-6179 Tel: 81-3-5620-6175 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.